diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
| commit | 324bc9771d1f3129aee87ccb73bcf23ea4c3b60e (patch) | |
| tree | e5ca02cc181b18d2806e30b99da07d6072724988 /tests/long/se/20.parser | |
| parent | 337774e192cb9268244d05e828b395060ba1cefb (diff) | |
| download | gem5-324bc9771d1f3129aee87ccb73bcf23ea4c3b60e.tar.xz | |
stats: Update stats to match cache changes
Diffstat (limited to 'tests/long/se/20.parser')
6 files changed, 3314 insertions, 3280 deletions
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index 91596dbee..168253993 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.412080 # Number of seconds simulated -sim_ticks 412080064500 # Number of ticks simulated -final_tick 412080064500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.412076 # Number of seconds simulated +sim_ticks 412076211500 # Number of ticks simulated +final_tick 412076211500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 310711 # Simulator instruction rate (inst/s) -host_op_rate 310711 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 209245414 # Simulator tick rate (ticks/s) -host_mem_usage 301844 # Number of bytes of host memory used -host_seconds 1969.36 # Real time elapsed on the host +host_inst_rate 332870 # Simulator instruction rate (inst/s) +host_op_rate 332870 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 224166223 # Simulator tick rate (ticks/s) +host_mem_usage 300688 # Number of bytes of host memory used +host_seconds 1838.26 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 170880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24123968 # Number of bytes read from this memory -system.physmem.bytes_read::total 24294848 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 170880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 170880 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18781376 # Number of bytes written to this memory -system.physmem.bytes_written::total 18781376 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2670 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 376937 # Number of read requests responded to by this memory -system.physmem.num_reads::total 379607 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293459 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293459 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 414677 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 58541944 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 58956621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 414677 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 414677 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45577007 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45577007 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45577007 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 414677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 58541944 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 104533628 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 379607 # Number of read requests accepted -system.physmem.writeReqs 293459 # Number of write requests accepted -system.physmem.readBursts 379607 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 293459 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24271744 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 23104 # Total number of bytes read from write queue -system.physmem.bytesWritten 18779968 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24294848 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18781376 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 361 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 156480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24143168 # Number of bytes read from this memory +system.physmem.bytes_read::total 24299648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 156480 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 156480 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18790784 # Number of bytes written to this memory +system.physmem.bytes_written::total 18790784 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2445 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 377237 # Number of read requests responded to by this memory +system.physmem.num_reads::total 379682 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293606 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293606 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 379736 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 58589085 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 58968820 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 379736 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 379736 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45600264 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45600264 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45600264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 379736 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 58589085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 104569084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 379682 # Number of read requests accepted +system.physmem.writeReqs 293606 # Number of write requests accepted +system.physmem.readBursts 379682 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 293606 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24277120 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 22528 # Total number of bytes read from write queue +system.physmem.bytesWritten 18788736 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24299648 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18790784 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 352 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 23711 # Per bank write bursts -system.physmem.perBankRdBursts::1 23184 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 51706 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 23686 # Per bank write bursts +system.physmem.perBankRdBursts::1 23158 # Per bank write bursts system.physmem.perBankRdBursts::2 23442 # Per bank write bursts -system.physmem.perBankRdBursts::3 24496 # Per bank write bursts -system.physmem.perBankRdBursts::4 25435 # Per bank write bursts -system.physmem.perBankRdBursts::5 23571 # Per bank write bursts -system.physmem.perBankRdBursts::6 23637 # Per bank write bursts -system.physmem.perBankRdBursts::7 23952 # Per bank write bursts -system.physmem.perBankRdBursts::8 23149 # Per bank write bursts -system.physmem.perBankRdBursts::9 23951 # Per bank write bursts -system.physmem.perBankRdBursts::10 24706 # Per bank write bursts -system.physmem.perBankRdBursts::11 22760 # Per bank write bursts -system.physmem.perBankRdBursts::12 23713 # Per bank write bursts -system.physmem.perBankRdBursts::13 24379 # Per bank write bursts -system.physmem.perBankRdBursts::14 22720 # Per bank write bursts -system.physmem.perBankRdBursts::15 22440 # Per bank write bursts -system.physmem.perBankWrBursts::0 17781 # Per bank write bursts +system.physmem.perBankRdBursts::3 24500 # Per bank write bursts +system.physmem.perBankRdBursts::4 25445 # Per bank write bursts +system.physmem.perBankRdBursts::5 23568 # Per bank write bursts +system.physmem.perBankRdBursts::6 23655 # Per bank write bursts +system.physmem.perBankRdBursts::7 23906 # Per bank write bursts +system.physmem.perBankRdBursts::8 23193 # Per bank write bursts +system.physmem.perBankRdBursts::9 23982 # Per bank write bursts +system.physmem.perBankRdBursts::10 24711 # Per bank write bursts +system.physmem.perBankRdBursts::11 22783 # Per bank write bursts +system.physmem.perBankRdBursts::12 23721 # Per bank write bursts +system.physmem.perBankRdBursts::13 24390 # Per bank write bursts +system.physmem.perBankRdBursts::14 22740 # Per bank write bursts +system.physmem.perBankRdBursts::15 22450 # Per bank write bursts +system.physmem.perBankWrBursts::0 17782 # Per bank write bursts system.physmem.perBankWrBursts::1 17456 # Per bank write bursts -system.physmem.perBankWrBursts::2 17945 # Per bank write bursts -system.physmem.perBankWrBursts::3 18847 # Per bank write bursts +system.physmem.perBankWrBursts::2 17944 # Per bank write bursts +system.physmem.perBankWrBursts::3 18851 # Per bank write bursts system.physmem.perBankWrBursts::4 19513 # Per bank write bursts -system.physmem.perBankWrBursts::5 18587 # Per bank write bursts -system.physmem.perBankWrBursts::6 18727 # Per bank write bursts -system.physmem.perBankWrBursts::7 18653 # Per bank write bursts -system.physmem.perBankWrBursts::8 18413 # Per bank write bursts -system.physmem.perBankWrBursts::9 18933 # Per bank write bursts +system.physmem.perBankWrBursts::5 18590 # Per bank write bursts +system.physmem.perBankWrBursts::6 18777 # Per bank write bursts +system.physmem.perBankWrBursts::7 18659 # Per bank write bursts +system.physmem.perBankWrBursts::8 18440 # Per bank write bursts +system.physmem.perBankWrBursts::9 18941 # Per bank write bursts system.physmem.perBankWrBursts::10 19255 # Per bank write bursts -system.physmem.perBankWrBursts::11 18037 # Per bank write bursts -system.physmem.perBankWrBursts::12 18264 # Per bank write bursts -system.physmem.perBankWrBursts::13 18729 # Per bank write bursts -system.physmem.perBankWrBursts::14 17175 # Per bank write bursts -system.physmem.perBankWrBursts::15 17122 # Per bank write bursts +system.physmem.perBankWrBursts::11 18046 # Per bank write bursts +system.physmem.perBankWrBursts::12 18263 # Per bank write bursts +system.physmem.perBankWrBursts::13 18731 # Per bank write bursts +system.physmem.perBankWrBursts::14 17195 # Per bank write bursts +system.physmem.perBankWrBursts::15 17131 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 412079976500 # Total gap between requests +system.physmem.totGap 412076182000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 379607 # Read request sizes (log2) +system.physmem.readPktSize::6 379682 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 293459 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 377839 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1392 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293606 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 377941 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1374 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,31 +144,31 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 40 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see @@ -193,39 +193,39 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 142258 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 302.629870 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.695929 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.359961 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 50814 35.72% 35.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38804 27.28% 63.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13098 9.21% 72.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8314 5.84% 78.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5760 4.05% 82.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3818 2.68% 84.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2956 2.08% 86.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2613 1.84% 88.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16081 11.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 142258 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17331 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.881888 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 237.076982 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17323 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 3 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 142335 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 302.556532 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.740913 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.275213 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 50726 35.64% 35.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38947 27.36% 63.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13162 9.25% 72.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8307 5.84% 78.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5691 4.00% 82.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3798 2.67% 84.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3047 2.14% 86.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2540 1.78% 88.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16117 11.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 142335 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17335 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.880819 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 236.752171 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17326 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17331 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17331 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.931337 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.860812 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.636907 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17131 98.85% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 149 0.86% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 30 0.17% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 5 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 5 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17335 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17335 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.935333 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.864235 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.642113 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17130 98.82% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 152 0.88% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 27 0.16% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 9 0.05% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 6 0.03% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::36-39 1 0.01% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::52-55 1 0.01% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::56-59 1 0.01% 99.95% # Writes before turning the bus around for reads @@ -235,87 +235,87 @@ system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Wr system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::156-159 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::224-227 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17331 # Writes before turning the bus around for reads -system.physmem.totQLat 4068932250 # Total ticks spent queuing -system.physmem.totMemAccLat 11179794750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1896230000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10729.01 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 17335 # Writes before turning the bus around for reads +system.physmem.totQLat 4058081750 # Total ticks spent queuing +system.physmem.totMemAccLat 11170519250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1896650000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10698.02 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29479.01 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 58.90 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 45.57 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 58.96 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 45.58 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29448.02 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 58.91 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 45.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 58.97 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 45.60 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.82 # Data bus utilization in percentage system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.54 # Average write queue length when enqueuing -system.physmem.readRowHits 314133 # Number of row buffer hits during reads -system.physmem.writeRowHits 216290 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.70 # Row buffer hit rate for writes -system.physmem.avgGap 612243.04 # Average gap between requests -system.physmem.pageHitRate 78.85 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 548364600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 299206875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1493138400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 955858320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26915029440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 62103866355 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 192770777250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 285086241240 # Total energy per rank (pJ) -system.physmem_0.averagePower 691.822973 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 320142846250 # Time in different power states -system.physmem_0.memoryStateTime::REF 13760240000 # Time in different power states +system.physmem.avgWrQLen 19.82 # Average write queue length when enqueuing +system.physmem.readRowHits 314253 # Number of row buffer hits during reads +system.physmem.writeRowHits 216307 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.67 # Row buffer hit rate for writes +system.physmem.avgGap 612035.54 # Average gap between requests +system.physmem.pageHitRate 78.84 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 548334360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 299190375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1492491000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 956130480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26914520880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 61976871495 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 192877504500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 285065043090 # Total energy per rank (pJ) +system.physmem_0.averagePower 691.784602 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 320322978500 # Time in different power states +system.physmem_0.memoryStateTime::REF 13759980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 78176682500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 77989027750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 527105880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 287607375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1464957000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 945613440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26915029440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 59197387905 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 195320319750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 284658020790 # Total energy per rank (pJ) -system.physmem_1.averagePower 690.783804 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 324404039000 # Time in different power states -system.physmem_1.memoryStateTime::REF 13760240000 # Time in different power states +system.physmem_1.actEnergy 527491440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 287817750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1465854000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 945995760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26914520880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 59032825200 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 195460001250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 284634506280 # Total energy per rank (pJ) +system.physmem_1.averagePower 690.739793 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 324635867250 # Time in different power states +system.physmem_1.memoryStateTime::REF 13759980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 73915489750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 73676135250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 123917174 # Number of BP lookups -system.cpu.branchPred.condPredicted 87658941 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6214604 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 71577859 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67272092 # Number of BTB hits +system.cpu.branchPred.lookups 123917200 # Number of BP lookups +system.cpu.branchPred.condPredicted 87658954 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6214605 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 71577882 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67272105 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.984499 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15041850 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1126019 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.984487 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15041853 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1126020 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 149344667 # DTB read hits -system.cpu.dtb.read_misses 549014 # DTB read misses +system.cpu.dtb.read_hits 149344669 # DTB read hits +system.cpu.dtb.read_misses 549013 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 149893681 # DTB read accesses +system.cpu.dtb.read_accesses 149893682 # DTB read accesses system.cpu.dtb.write_hits 57319597 # DTB write hits system.cpu.dtb.write_misses 63704 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 57383301 # DTB write accesses -system.cpu.dtb.data_hits 206664264 # DTB hits -system.cpu.dtb.data_misses 612718 # DTB misses +system.cpu.dtb.data_hits 206664266 # DTB hits +system.cpu.dtb.data_misses 612717 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 207276982 # DTB accesses -system.cpu.itb.fetch_hits 226051197 # ITB hits +system.cpu.dtb.data_accesses 207276983 # DTB accesses +system.cpu.itb.fetch_hits 226051267 # ITB hits system.cpu.itb.fetch_misses 48 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 226051245 # ITB accesses +system.cpu.itb.fetch_accesses 226051315 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -329,24 +329,24 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 485 # Number of system calls -system.cpu.numCycles 824160129 # number of cpu cycles simulated +system.cpu.numCycles 824152423 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 611901617 # Number of instructions committed system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed -system.cpu.discardedOps 12834592 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 12834608 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.346883 # CPI: cycles per instruction -system.cpu.ipc 0.742455 # IPC: instructions per cycle -system.cpu.tickCycles 739333640 # Number of cycles that the object actually ticked -system.cpu.idleCycles 84826489 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.346871 # CPI: cycles per instruction +system.cpu.ipc 0.742462 # IPC: instructions per cycle +system.cpu.tickCycles 739334528 # Number of cycles that the object actually ticked +system.cpu.idleCycles 84817895 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 2535265 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.660702 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 202570424 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4087.660624 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 202570425 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2539361 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 79.772204 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 79.772205 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1635033500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.660702 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.660624 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997964 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997964 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -355,16 +355,16 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 system.cpu.dcache.tags.age_task_id_blocks_1024::2 829 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3145 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 414584973 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 414584973 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 146904267 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146904267 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 414584975 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 414584975 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 146904268 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 146904268 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 55666157 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 55666157 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 202570424 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 202570424 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 202570424 # number of overall hits -system.cpu.dcache.overall_hits::total 202570424 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 202570425 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 202570425 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 202570425 # number of overall hits +system.cpu.dcache.overall_hits::total 202570425 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1908505 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1908505 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1543877 # number of WriteReq misses @@ -373,22 +373,22 @@ system.cpu.dcache.demand_misses::cpu.data 3452382 # n system.cpu.dcache.demand_misses::total 3452382 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 3452382 # number of overall misses system.cpu.dcache.overall_misses::total 3452382 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 37715152000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37715152000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 47725761500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 47725761500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 85440913500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 85440913500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 85440913500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 85440913500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 148812772 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 148812772 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 37724666000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 37724666000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 47726490500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 47726490500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 85451156500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 85451156500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 85451156500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 85451156500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 148812773 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 148812773 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 57210034 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 206022806 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 206022806 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 206022806 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 206022806 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 206022807 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 206022807 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 206022807 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 206022807 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012825 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012825 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026986 # miss rate for WriteReq accesses @@ -397,14 +397,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016757 system.cpu.dcache.demand_miss_rate::total 0.016757 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016757 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016757 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19761.620745 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19761.620745 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30912.929916 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30912.929916 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24748.395021 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24748.395021 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24748.395021 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24748.395021 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19766.605799 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19766.605799 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30913.402104 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30913.402104 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24751.361958 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24751.361958 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24751.361958 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24751.361958 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -413,8 +413,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2339622 # number of writebacks -system.cpu.dcache.writebacks::total 2339622 # number of writebacks +system.cpu.dcache.writebacks::writebacks 2339407 # number of writebacks +system.cpu.dcache.writebacks::total 2339407 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 143967 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 143967 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769054 # number of WriteReq MSHR hits @@ -431,14 +431,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2539361 system.cpu.dcache.demand_mshr_misses::total 2539361 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2539361 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2539361 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33198964500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33198964500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23344010000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 23344010000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56542974500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 56542974500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56542974500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 56542974500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33207035500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33207035500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23344377500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 23344377500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56551413000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 56551413000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56551413000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 56551413000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.011857 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011857 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.013543 # mshr miss rate for WriteReq accesses @@ -447,69 +447,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012326 system.cpu.dcache.demand_mshr_miss_rate::total 0.012326 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012326 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012326 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18814.536440 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18814.536440 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30128.184114 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30128.184114 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22266.615302 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22266.615302 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22266.615302 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22266.615302 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18819.110441 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18819.110441 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30128.658416 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30128.658416 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22269.938382 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22269.938382 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22269.938382 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22269.938382 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 3153 # number of replacements -system.cpu.icache.tags.tagsinuse 1116.819230 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 226046216 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4981 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 45381.693636 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 3156 # number of replacements +system.cpu.icache.tags.tagsinuse 1116.812774 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 226046283 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4984 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 45354.390650 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1116.819230 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.545322 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.545322 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1116.812774 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.545319 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.545319 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1828 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1590 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 452107375 # Number of tag accesses -system.cpu.icache.tags.data_accesses 452107375 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 226046216 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 226046216 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 226046216 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 226046216 # 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number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 245472000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 226051197 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 226051197 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 226051197 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 226051197 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 226051197 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 226051197 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 452107518 # Number of tag accesses +system.cpu.icache.tags.data_accesses 452107518 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 226046283 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 226046283 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 226046283 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 226046283 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 226046283 # number of overall hits +system.cpu.icache.overall_hits::total 226046283 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4984 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4984 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4984 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4984 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4984 # number of overall misses +system.cpu.icache.overall_misses::total 4984 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 231170500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 231170500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 231170500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 231170500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 231170500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 231170500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 226051267 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 226051267 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 226051267 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 226051267 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 226051267 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 226051267 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49281.670347 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49281.670347 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49281.670347 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49281.670347 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49281.670347 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49281.670347 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46382.524077 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 46382.524077 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 46382.524077 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46382.524077 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 46382.524077 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46382.524077 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -518,129 +518,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4981 # 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number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 3156 # number of writebacks +system.cpu.icache.writebacks::total 3156 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4984 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4984 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4984 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4984 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4984 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4984 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 226186500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 226186500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 226186500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 226186500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 226186500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 226186500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48281.670347 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48281.670347 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48281.670347 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48281.670347 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48281.670347 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48281.670347 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45382.524077 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45382.524077 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45382.524077 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 45382.524077 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45382.524077 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 45382.524077 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.938322 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8022.460164 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.650692 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004911 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.244826 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.900430 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32430 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13170 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18832 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.989471 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 41819560 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 41819560 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 2339622 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2339622 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 571899 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 571899 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2311 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 2311 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1590525 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1590525 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2311 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68635.701853 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68179.213483 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68179.213483 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70686.077714 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70686.077714 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68179.213483 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69564.106203 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69554.365436 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68179.213483 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69564.106203 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69554.365436 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265125 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265125 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.490570 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.490570 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.097051 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.097051 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.490570 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148556 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.149226 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.490570 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148556 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.149226 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68621.281082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68621.281082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68539.263804 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68539.263804 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70630.219333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70630.219333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68539.263804 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69531.535878 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69525.146043 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68539.263804 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69531.535878 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69525.146043 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5082760 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2538418 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5082766 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2538421 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 2391 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2391 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 1766182 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2633081 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 252234 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1766185 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2633013 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 3156 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 249951 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 778160 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 778160 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 4981 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4984 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1761201 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13115 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13124 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7613987 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7627102 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 318784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312254912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312573696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 346897 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5429657 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000440 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.020980 # Request fanout histogram +system.cpu.toL2Bus.pkt_count::total 7627111 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 520960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312241152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312762112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 347699 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2892044 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000827 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.028741 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5427266 99.96% 99.96% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2391 0.04% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2889653 99.92% 99.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2391 0.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5429657 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4881002000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2892044 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4883946000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7471500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7476000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3809041500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadResp 173346 # Transaction distribution -system.membus.trans_dist::Writeback 293459 # Transaction distribution -system.membus.trans_dist::CleanEvict 51785 # Transaction distribution -system.membus.trans_dist::ReadExReq 206261 # Transaction distribution -system.membus.trans_dist::ReadExResp 206261 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 173346 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1104458 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1104458 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43076224 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43076224 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 173372 # Transaction distribution +system.membus.trans_dist::WritebackDirty 293606 # Transaction distribution +system.membus.trans_dist::CleanEvict 51706 # Transaction distribution +system.membus.trans_dist::ReadExReq 206310 # Transaction distribution +system.membus.trans_dist::ReadExResp 206310 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 173372 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1104676 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1104676 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43090432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43090432 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 724851 # Request fanout histogram +system.membus.snoop_fanout::samples 724994 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 724851 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 724994 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 724851 # Request fanout histogram -system.membus.reqLayer0.occupancy 2020156500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 724994 # Request fanout histogram +system.membus.reqLayer0.occupancy 2020992000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2008875000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2009252250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 7a68c081f..232b217c8 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.363600 # Number of seconds simulated -sim_ticks 363599502500 # Number of ticks simulated -final_tick 363599502500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.363578 # Number of seconds simulated +sim_ticks 363578056500 # Number of ticks simulated +final_tick 363578056500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 226144 # Simulator instruction rate (inst/s) -host_op_rate 244944 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 162315109 # Simulator tick rate (ticks/s) -host_mem_usage 321124 # Number of bytes of host memory used -host_seconds 2240.08 # Real time elapsed on the host +host_inst_rate 237399 # Simulator instruction rate (inst/s) +host_op_rate 257134 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 170382928 # Simulator tick rate (ticks/s) +host_mem_usage 321244 # Number of bytes of host memory used +host_seconds 2133.89 # Real time elapsed on the host sim_insts 506582156 # Number of instructions simulated sim_ops 548695379 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 219456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9004480 # Number of bytes read from this memory -system.physmem.bytes_read::total 9223936 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219456 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6189376 # Number of bytes written to this memory -system.physmem.bytes_written::total 6189376 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3429 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140695 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144124 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96709 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96709 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 603565 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24764830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25368396 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 603565 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 603565 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 17022510 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 17022510 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 17022510 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 603565 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24764830 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42390905 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 144124 # Number of read requests accepted -system.physmem.writeReqs 96709 # Number of write requests accepted -system.physmem.readBursts 144124 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 96709 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9217920 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6016 # Total number of bytes read from write queue -system.physmem.bytesWritten 6188224 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9223936 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6189376 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 94 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 179648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9032384 # Number of bytes read from this memory +system.physmem.bytes_read::total 9212032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 179648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 179648 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6219008 # Number of bytes written to this memory +system.physmem.bytes_written::total 6219008 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2807 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141131 # Number of read requests responded to by this memory +system.physmem.num_reads::total 143938 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97172 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97172 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 494111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24843039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25337151 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 494111 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 494111 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17105015 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17105015 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17105015 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 494111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24843039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42442165 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 143938 # Number of read requests accepted +system.physmem.writeReqs 97172 # Number of write requests accepted +system.physmem.readBursts 143938 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97172 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9204928 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue +system.physmem.bytesWritten 6217152 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9212032 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6219008 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9331 # Per bank write bursts -system.physmem.perBankRdBursts::1 8969 # Per bank write bursts -system.physmem.perBankRdBursts::2 9003 # Per bank write bursts -system.physmem.perBankRdBursts::3 8675 # Per bank write bursts -system.physmem.perBankRdBursts::4 9453 # Per bank write bursts -system.physmem.perBankRdBursts::5 9352 # Per bank write bursts -system.physmem.perBankRdBursts::6 8945 # Per bank write bursts -system.physmem.perBankRdBursts::7 8102 # Per bank write bursts -system.physmem.perBankRdBursts::8 8582 # Per bank write bursts -system.physmem.perBankRdBursts::9 8674 # Per bank write bursts -system.physmem.perBankRdBursts::10 8765 # Per bank write bursts -system.physmem.perBankRdBursts::11 9476 # Per bank write bursts -system.physmem.perBankRdBursts::12 9348 # Per bank write bursts -system.physmem.perBankRdBursts::13 9513 # Per bank write bursts -system.physmem.perBankRdBursts::14 8719 # Per bank write bursts -system.physmem.perBankRdBursts::15 9123 # Per bank write bursts -system.physmem.perBankWrBursts::0 6195 # Per bank write bursts -system.physmem.perBankWrBursts::1 6094 # Per bank write bursts -system.physmem.perBankWrBursts::2 6011 # Per bank write bursts -system.physmem.perBankWrBursts::3 5821 # Per bank write bursts -system.physmem.perBankWrBursts::4 6181 # Per bank write bursts -system.physmem.perBankWrBursts::5 6188 # Per bank write bursts -system.physmem.perBankWrBursts::6 6015 # Per bank write bursts -system.physmem.perBankWrBursts::7 5499 # Per bank write bursts -system.physmem.perBankWrBursts::8 5743 # Per bank write bursts -system.physmem.perBankWrBursts::9 5830 # Per bank write bursts -system.physmem.perBankWrBursts::10 5965 # Per bank write bursts -system.physmem.perBankWrBursts::11 6463 # Per bank write bursts -system.physmem.perBankWrBursts::12 6312 # Per bank write bursts -system.physmem.perBankWrBursts::13 6285 # Per bank write bursts -system.physmem.perBankWrBursts::14 6003 # Per bank write bursts -system.physmem.perBankWrBursts::15 6086 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 12571 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9337 # Per bank write bursts +system.physmem.perBankRdBursts::1 8920 # Per bank write bursts +system.physmem.perBankRdBursts::2 8993 # Per bank write bursts +system.physmem.perBankRdBursts::3 8670 # Per bank write bursts +system.physmem.perBankRdBursts::4 9385 # Per bank write bursts +system.physmem.perBankRdBursts::5 9354 # Per bank write bursts +system.physmem.perBankRdBursts::6 8954 # Per bank write bursts +system.physmem.perBankRdBursts::7 8104 # Per bank write bursts +system.physmem.perBankRdBursts::8 8602 # Per bank write bursts +system.physmem.perBankRdBursts::9 8629 # Per bank write bursts +system.physmem.perBankRdBursts::10 8738 # Per bank write bursts +system.physmem.perBankRdBursts::11 9458 # Per bank write bursts +system.physmem.perBankRdBursts::12 9338 # Per bank write bursts +system.physmem.perBankRdBursts::13 9514 # Per bank write bursts +system.physmem.perBankRdBursts::14 8722 # Per bank write bursts +system.physmem.perBankRdBursts::15 9109 # Per bank write bursts +system.physmem.perBankWrBursts::0 6210 # Per bank write bursts +system.physmem.perBankWrBursts::1 6096 # Per bank write bursts +system.physmem.perBankWrBursts::2 6031 # Per bank write bursts +system.physmem.perBankWrBursts::3 5885 # Per bank write bursts +system.physmem.perBankWrBursts::4 6239 # Per bank write bursts +system.physmem.perBankWrBursts::5 6240 # Per bank write bursts +system.physmem.perBankWrBursts::6 6045 # Per bank write bursts +system.physmem.perBankWrBursts::7 5507 # Per bank write bursts +system.physmem.perBankWrBursts::8 5786 # Per bank write bursts +system.physmem.perBankWrBursts::9 5860 # Per bank write bursts +system.physmem.perBankWrBursts::10 5977 # Per bank write bursts +system.physmem.perBankWrBursts::11 6497 # Per bank write bursts +system.physmem.perBankWrBursts::12 6353 # Per bank write bursts +system.physmem.perBankWrBursts::13 6323 # Per bank write bursts +system.physmem.perBankWrBursts::14 6005 # Per bank write bursts +system.physmem.perBankWrBursts::15 6089 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 363599476500 # Total gap between requests +system.physmem.totGap 363578030500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 144124 # Read request sizes (log2) +system.physmem.readPktSize::6 143938 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 96709 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143660 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97172 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,37 +144,37 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5613 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5621 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see @@ -193,124 +193,112 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65302 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 235.912652 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.372535 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.914583 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24788 37.96% 37.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18406 28.19% 66.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6849 10.49% 76.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7905 12.11% 88.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2084 3.19% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1111 1.70% 93.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 761 1.17% 94.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 643 0.98% 95.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2755 4.22% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65302 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5583 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.797421 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 381.883100 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5579 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 65452 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 235.611563 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.275569 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 241.348204 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24841 37.95% 37.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18422 28.15% 66.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6870 10.50% 76.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7970 12.18% 88.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2117 3.23% 92.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1100 1.68% 93.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 791 1.21% 94.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 584 0.89% 95.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2757 4.21% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65452 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5612 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.626515 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 380.491009 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5610 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5583 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5583 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.318825 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.224966 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.238810 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2516 45.07% 45.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 99 1.77% 46.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 2663 47.70% 94.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 163 2.92% 97.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 38 0.68% 98.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 18 0.32% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 14 0.25% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 8 0.14% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 6 0.11% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 9 0.16% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 5 0.09% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 4 0.07% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 4 0.07% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 6 0.11% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 2 0.04% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 3 0.05% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 2 0.04% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 4 0.07% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 2 0.04% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 2 0.04% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 2 0.04% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 1 0.02% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 2 0.04% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::53 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::55 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::61 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::62 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5583 # Writes before turning the bus around for reads -system.physmem.totQLat 1538433000 # Total ticks spent queuing -system.physmem.totMemAccLat 4238995500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 720150000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10681.34 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5612 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5612 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.309872 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.213078 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.394006 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 2658 47.36% 47.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 2810 50.07% 97.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 50 0.89% 98.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 29 0.52% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 20 0.36% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 11 0.20% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 6 0.11% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 6 0.11% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 3 0.05% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 7 0.12% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 2 0.04% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-73 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-97 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5612 # Writes before turning the bus around for reads +system.physmem.totQLat 1537591000 # Total ticks spent queuing +system.physmem.totMemAccLat 4234347250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 719135000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10690.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29431.34 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.35 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 17.02 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.37 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 17.02 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29440.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 17.10 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.34 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 17.11 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.80 # Average write queue length when enqueuing -system.physmem.readRowHits 110870 # Number of row buffer hits during reads -system.physmem.writeRowHits 64542 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.98 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.74 # Row buffer hit rate for writes -system.physmem.avgGap 1509757.70 # Average gap between requests -system.physmem.pageHitRate 72.86 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 248293080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 135477375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 560086800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 310832640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 23748226320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47486002320 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 176502477750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 248991396285 # Total energy per rank (pJ) -system.physmem_0.averagePower 684.804658 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 293320694250 # Time in different power states -system.physmem_0.memoryStateTime::REF 12141220000 # Time in different power states +system.physmem.avgWrQLen 19.82 # Average write queue length when enqueuing +system.physmem.readRowHits 110822 # Number of row buffer hits during reads +system.physmem.writeRowHits 64690 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.05 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.57 # Row buffer hit rate for writes +system.physmem.avgGap 1507934.26 # Average gap between requests +system.physmem.pageHitRate 72.83 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 249245640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 135997125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 559174200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 312459120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 23746700640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47224643355 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 176717716500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 248945936580 # Total energy per rank (pJ) +system.physmem_0.averagePower 684.723644 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 293681207750 # Time in different power states +system.physmem_0.memoryStateTime::REF 12140440000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 58133810750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 57750923750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 245148120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 133761375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 562957200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 315401040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 23748226320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 46957937220 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 176965692750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 248929124025 # Total energy per rank (pJ) -system.physmem_1.averagePower 684.633389 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 294092512000 # Time in different power states -system.physmem_1.memoryStateTime::REF 12141220000 # Time in different power states +system.physmem_1.actEnergy 245314440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 133852125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 562247400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 316716480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 23746700640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 46957257495 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 176952265500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 248914354080 # Total energy per rank (pJ) +system.physmem_1.averagePower 684.636777 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 294072895750 # Time in different power states +system.physmem_1.memoryStateTime::REF 12140440000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 57361058000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 57359475250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 131895360 # Number of BP lookups -system.cpu.branchPred.condPredicted 98029927 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6139026 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 68388068 # Number of BTB lookups -system.cpu.branchPred.BTBHits 64396789 # Number of BTB hits +system.cpu.branchPred.lookups 131892190 # Number of BP lookups +system.cpu.branchPred.condPredicted 98029664 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6137262 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68271020 # Number of BTB lookups +system.cpu.branchPred.BTBHits 64393265 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.163779 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9981632 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 18119 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.320057 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9980136 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17826 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -429,98 +417,98 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 727199005 # number of cpu cycles simulated +system.cpu.numCycles 727156113 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506582156 # Number of instructions committed system.cpu.committedOps 548695379 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13199573 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 13195789 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.435501 # CPI: cycles per instruction -system.cpu.ipc 0.696621 # IPC: instructions per cycle -system.cpu.tickCycles 690715590 # Number of cycles that the object actually ticked -system.cpu.idleCycles 36483415 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1139984 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.789434 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171168644 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1144080 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.612478 # Average number of references to valid blocks. +system.cpu.cpi 1.435416 # CPI: cycles per instruction +system.cpu.ipc 0.696662 # IPC: instructions per cycle +system.cpu.tickCycles 690690437 # Number of cycles that the object actually ticked +system.cpu.idleCycles 36465676 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1139983 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.787946 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171168228 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1144079 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.612245 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4896334500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.789434 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.787946 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.993845 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993845 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3499 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3500 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346592332 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346592332 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114650184 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114650184 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53538625 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53538625 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 346591347 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346591347 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114649758 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114649758 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53538635 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53538635 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 2753 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 2753 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168188809 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168188809 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168191562 # number of overall hits -system.cpu.dcache.overall_hits::total 168191562 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 854786 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 854786 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 700681 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 700681 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 15 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 15 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1555467 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1555467 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1555482 # number of overall misses -system.cpu.dcache.overall_misses::total 1555482 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14024022500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14024022500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21893600500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21893600500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35917623000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35917623000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35917623000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35917623000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115504970 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115504970 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 168188393 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168188393 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168191146 # number of overall hits +system.cpu.dcache.overall_hits::total 168191146 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 854719 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 854719 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 700671 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 700671 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 16 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 16 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1555390 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1555390 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1555406 # number of overall misses +system.cpu.dcache.overall_misses::total 1555406 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14046321000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14046321000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21904504500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21904504500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35950825500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35950825500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35950825500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35950825500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115504477 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115504477 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2768 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2768 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2769 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2769 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169744276 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169744276 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169747044 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169747044 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 169743783 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169743783 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169746552 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169746552 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007400 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.007400 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012918 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.012918 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005419 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.005419 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009164 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009164 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009164 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009164 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16406.471912 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16406.471912 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31246.174079 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31246.174079 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23091.215050 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23091.215050 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23090.992374 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23090.992374 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005778 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.005778 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009163 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009163 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009163 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009163 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16433.846679 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16433.846679 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31262.182251 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31262.182251 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23113.704923 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23113.704923 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23113.467159 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23113.467159 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -529,111 +517,111 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1068583 # number of writebacks -system.cpu.dcache.writebacks::total 1068583 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66886 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66886 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344513 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344513 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 411399 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 411399 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 411399 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 411399 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787900 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 787900 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356168 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356168 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1144068 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1144068 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1144080 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1144080 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12337991000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12337991000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11121217500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11121217500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 946000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 946000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23459208500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23459208500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23460154500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23460154500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 1068257 # number of writebacks +system.cpu.dcache.writebacks::total 1068257 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66817 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66817 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344507 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 344507 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 411324 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 411324 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 411324 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 411324 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787902 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 787902 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356164 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356164 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 13 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 13 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1144066 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1144066 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1144079 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1144079 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12362476000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12362476000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11126251500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11126251500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1030500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1030500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23488727500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23488727500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23489758000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23489758000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006821 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006821 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006567 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006567 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004335 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004335 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004695 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004695 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006740 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006740 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006740 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006740 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15659.336210 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15659.336210 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31224.639777 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31224.639777 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78833.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78833.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20505.082303 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20505.082303 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20505.694095 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20505.694095 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15690.372661 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15690.372661 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31239.124392 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31239.124392 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79269.230769 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79269.230769 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20530.919982 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20530.919982 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20531.587417 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20531.587417 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 17702 # number of replacements -system.cpu.icache.tags.tagsinuse 1188.317648 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 199314883 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 19574 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10182.634260 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 17711 # number of replacements +system.cpu.icache.tags.tagsinuse 1188.286888 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 199302654 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 19583 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10177.330031 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1188.317648 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.580233 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.580233 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1188.286888 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.580218 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.580218 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 306 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1404 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 309 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1403 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 398688488 # Number of tag accesses -system.cpu.icache.tags.data_accesses 398688488 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 199314883 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 199314883 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 199314883 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 199314883 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 199314883 # number of overall hits -system.cpu.icache.overall_hits::total 199314883 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19574 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19574 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19574 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19574 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19574 # 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number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 199334457 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 199334457 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 398664057 # Number of tag accesses +system.cpu.icache.tags.data_accesses 398664057 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 199302654 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 199302654 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 199302654 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 199302654 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 199302654 # number of overall hits +system.cpu.icache.overall_hits::total 199302654 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19583 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19583 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19583 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19583 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19583 # number of overall misses +system.cpu.icache.overall_misses::total 19583 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 449788500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 449788500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 449788500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 449788500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 449788500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 449788500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 199322237 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 199322237 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 199322237 # 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average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25101.333401 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25101.333401 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25101.333401 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25101.333401 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22968.314354 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22968.314354 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22968.314354 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22968.314354 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22968.314354 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22968.314354 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -642,128 +630,134 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19574 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 19574 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 19574 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 19574 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 19574 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 19574 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 471759500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 471759500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 471759500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 471759500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 471759500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 471759500 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 17711 # number of writebacks +system.cpu.icache.writebacks::total 17711 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19583 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 19583 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 19583 # 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mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000098 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000098 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24101.333401 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24101.333401 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24101.333401 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24101.333401 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24101.333401 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24101.333401 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21968.314354 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21968.314354 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21968.314354 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21968.314354 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21968.314354 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21968.314354 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 111370 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27634.033642 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1767249 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 142558 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.396702 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 163253473000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23457.713364 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 389.652620 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3786.667658 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.715873 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011891 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.115560 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.843324 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31188 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 323 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4939 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25857 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 19030322 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 19030322 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 1068583 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1068583 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 255591 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 255591 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16143 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 16143 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 747780 # 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number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2907247000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195877500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9809805000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10005682500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195877500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9809805000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10005682500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283161 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283161 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.143339 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.143339 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.051047 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.051047 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.143339 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123358 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123694 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.143339 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123358 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123694 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68394.300605 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68394.300605 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69781.795511 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69781.795511 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72305.188022 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72305.188022 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69781.795511 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69508.506281 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69513.835818 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69781.795511 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69508.506281 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69513.835818 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 2321340 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1157756 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4922 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2616 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2613 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 2321356 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1157764 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4913 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2623 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2620 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 807234 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1165292 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 98842 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356420 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356420 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 19574 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 787660 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56613 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3423459 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3480072 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141610432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142863168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 111370 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2432710 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.005152 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.071609 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 807247 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1165429 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 17475 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 82243 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356415 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356415 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 19583 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 787664 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56641 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3423464 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3480105 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2371712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141589504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 143961216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 112366 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1276028 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.005963 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.077021 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2420180 99.48% 99.48% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12527 0.51% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1268422 99.40% 99.40% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 7603 0.60% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2432710 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2229253000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1276028 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2246646000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 29379463 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 29392963 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1716126986 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1716126983 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadResp 43295 # Transaction distribution -system.membus.trans_dist::Writeback 96709 # Transaction distribution -system.membus.trans_dist::CleanEvict 13242 # Transaction distribution -system.membus.trans_dist::ReadExReq 100829 # Transaction distribution -system.membus.trans_dist::ReadExResp 100829 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 43295 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398199 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 398199 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15413312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15413312 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 43015 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97172 # Transaction distribution +system.membus.trans_dist::CleanEvict 12571 # Transaction distribution +system.membus.trans_dist::ReadExReq 100923 # Transaction distribution +system.membus.trans_dist::ReadExResp 100923 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 43015 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397619 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 397619 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15431040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15431040 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 254075 # Request fanout histogram +system.membus.snoop_fanout::samples 253681 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 254075 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 253681 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 254075 # Request fanout histogram -system.membus.reqLayer0.occupancy 683661500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 253681 # Request fanout histogram +system.membus.reqLayer0.occupancy 685231500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 765035500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 764006500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 153b00611..29a3d1e47 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.233306 # Number of seconds simulated -sim_ticks 233306027000 # Number of ticks simulated -final_tick 233306027000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.234001 # Number of seconds simulated +sim_ticks 234001297000 # Number of ticks simulated +final_tick 234001297000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128535 # Simulator instruction rate (inst/s) -host_op_rate 139249 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59354207 # Simulator tick rate (ticks/s) -host_mem_usage 322028 # Number of bytes of host memory used -host_seconds 3930.74 # Real time elapsed on the host +host_inst_rate 134504 # Simulator instruction rate (inst/s) +host_op_rate 145716 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62295833 # Simulator tick rate (ticks/s) +host_mem_usage 343376 # Number of bytes of host memory used +host_seconds 3756.29 # Real time elapsed on the host sim_insts 505237724 # Number of instructions simulated sim_ops 547350945 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 683648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9174464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16490944 # Number of bytes read from this memory -system.physmem.bytes_read::total 26349056 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 683648 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 683648 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18702784 # Number of bytes written to this memory -system.physmem.bytes_written::total 18702784 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 10682 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 143351 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 257671 # Number of read requests responded to by this memory -system.physmem.num_reads::total 411704 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292231 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292231 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2930263 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 39323733 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 70683746 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 112937742 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2930263 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2930263 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 80164170 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 80164170 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 80164170 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2930263 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 39323733 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 70683746 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 193101912 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 411704 # Number of read requests accepted -system.physmem.writeReqs 292231 # Number of write requests accepted -system.physmem.readBursts 411704 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292231 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26211648 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 137408 # Total number of bytes read from write queue -system.physmem.bytesWritten 18700672 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26349056 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18702784 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2147 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26604 # Per bank write bursts -system.physmem.perBankRdBursts::1 25479 # Per bank write bursts -system.physmem.perBankRdBursts::2 25122 # Per bank write bursts -system.physmem.perBankRdBursts::3 24753 # Per bank write bursts -system.physmem.perBankRdBursts::4 27168 # Per bank write bursts -system.physmem.perBankRdBursts::5 26312 # Per bank write bursts -system.physmem.perBankRdBursts::6 25243 # Per bank write bursts -system.physmem.perBankRdBursts::7 24096 # Per bank write bursts -system.physmem.perBankRdBursts::8 25848 # Per bank write bursts -system.physmem.perBankRdBursts::9 24676 # Per bank write bursts -system.physmem.perBankRdBursts::10 25150 # Per bank write bursts -system.physmem.perBankRdBursts::11 26103 # Per bank write bursts -system.physmem.perBankRdBursts::12 26513 # Per bank write bursts -system.physmem.perBankRdBursts::13 25940 # Per bank write bursts -system.physmem.perBankRdBursts::14 25062 # Per bank write bursts -system.physmem.perBankRdBursts::15 25488 # Per bank write bursts -system.physmem.perBankWrBursts::0 18828 # Per bank write bursts -system.physmem.perBankWrBursts::1 18294 # Per bank write bursts -system.physmem.perBankWrBursts::2 17806 # Per bank write bursts -system.physmem.perBankWrBursts::3 17978 # Per bank write bursts -system.physmem.perBankWrBursts::4 18719 # Per bank write bursts -system.physmem.perBankWrBursts::5 18281 # Per bank write bursts -system.physmem.perBankWrBursts::6 17995 # Per bank write bursts -system.physmem.perBankWrBursts::7 17635 # Per bank write bursts -system.physmem.perBankWrBursts::8 18144 # Per bank write bursts -system.physmem.perBankWrBursts::9 17824 # Per bank write bursts -system.physmem.perBankWrBursts::10 18107 # Per bank write bursts -system.physmem.perBankWrBursts::11 18749 # Per bank write bursts -system.physmem.perBankWrBursts::12 18847 # Per bank write bursts -system.physmem.perBankWrBursts::13 18260 # Per bank write bursts -system.physmem.perBankWrBursts::14 18418 # Per bank write bursts -system.physmem.perBankWrBursts::15 18313 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 517504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10131008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16480064 # Number of bytes read from this memory +system.physmem.bytes_read::total 27128576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 517504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 517504 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18730688 # Number of bytes written to this memory +system.physmem.bytes_written::total 18730688 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8086 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158297 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 257501 # Number of read requests responded to by this memory +system.physmem.num_reads::total 423884 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292667 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292667 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2211543 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 43294666 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 70427234 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 115933443 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2211543 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2211543 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 80045232 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 80045232 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 80045232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2211543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 43294666 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 70427234 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 195978674 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 423884 # Number of read requests accepted +system.physmem.writeReqs 292667 # Number of write requests accepted +system.physmem.readBursts 423884 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292667 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26972992 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 155584 # Total number of bytes read from write queue +system.physmem.bytesWritten 18728832 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27128576 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18730688 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2431 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 98651 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 26584 # Per bank write bursts +system.physmem.perBankRdBursts::1 25337 # Per bank write bursts +system.physmem.perBankRdBursts::2 25274 # Per bank write bursts +system.physmem.perBankRdBursts::3 32197 # Per bank write bursts +system.physmem.perBankRdBursts::4 27335 # Per bank write bursts +system.physmem.perBankRdBursts::5 28299 # Per bank write bursts +system.physmem.perBankRdBursts::6 25126 # Per bank write bursts +system.physmem.perBankRdBursts::7 24198 # Per bank write bursts +system.physmem.perBankRdBursts::8 25368 # Per bank write bursts +system.physmem.perBankRdBursts::9 25926 # Per bank write bursts +system.physmem.perBankRdBursts::10 25318 # Per bank write bursts +system.physmem.perBankRdBursts::11 26278 # Per bank write bursts +system.physmem.perBankRdBursts::12 27572 # Per bank write bursts +system.physmem.perBankRdBursts::13 25872 # Per bank write bursts +system.physmem.perBankRdBursts::14 25056 # Per bank write bursts +system.physmem.perBankRdBursts::15 25713 # Per bank write bursts +system.physmem.perBankWrBursts::0 18662 # Per bank write bursts +system.physmem.perBankWrBursts::1 18231 # Per bank write bursts +system.physmem.perBankWrBursts::2 18003 # Per bank write bursts +system.physmem.perBankWrBursts::3 17875 # Per bank write bursts +system.physmem.perBankWrBursts::4 18721 # Per bank write bursts +system.physmem.perBankWrBursts::5 18310 # Per bank write bursts +system.physmem.perBankWrBursts::6 17836 # Per bank write bursts +system.physmem.perBankWrBursts::7 17744 # Per bank write bursts +system.physmem.perBankWrBursts::8 17983 # Per bank write bursts +system.physmem.perBankWrBursts::9 17940 # Per bank write bursts +system.physmem.perBankWrBursts::10 18239 # Per bank write bursts +system.physmem.perBankWrBursts::11 18938 # Per bank write bursts +system.physmem.perBankWrBursts::12 18976 # Per bank write bursts +system.physmem.perBankWrBursts::13 18211 # Per bank write bursts +system.physmem.perBankWrBursts::14 18390 # Per bank write bursts +system.physmem.perBankWrBursts::15 18579 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 233306009000 # Total gap between requests +system.physmem.totGap 234001244500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 411704 # Read request sizes (log2) +system.physmem.readPktSize::6 423884 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292231 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 311101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 49294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13059 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 86 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292667 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 323806 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 49376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12876 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8979 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5227 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3341 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 70 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,35 +148,35 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 13179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 15360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 20067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17602 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 7238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 18115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 19072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see @@ -197,103 +197,112 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 306850 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 146.361336 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 102.891492 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 182.277612 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 184544 60.14% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 81708 26.63% 86.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 16503 5.38% 92.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7231 2.36% 94.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4881 1.59% 96.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2237 0.73% 96.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1756 0.57% 97.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1532 0.50% 97.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6458 2.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 306850 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17319 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.647035 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 116.821350 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 17318 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17319 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17319 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.871528 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.829762 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.229266 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 10538 60.85% 60.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 299 1.73% 62.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5524 31.90% 94.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 601 3.47% 97.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 136 0.79% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 86 0.50% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 52 0.30% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 38 0.22% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 24 0.14% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 14 0.08% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 5 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17319 # Writes before turning the bus around for reads -system.physmem.totQLat 9105020732 # Total ticks spent queuing -system.physmem.totMemAccLat 16784214482 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2047785000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22231.39 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 322061 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 141.901068 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 99.764285 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 180.057081 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 202493 62.87% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 79759 24.77% 87.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15144 4.70% 92.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7279 2.26% 94.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4961 1.54% 96.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2580 0.80% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1828 0.57% 97.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1538 0.48% 97.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6479 2.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 322061 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17076 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.676095 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 143.384257 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17074 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 17076 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17076 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.137386 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.076722 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.519222 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 9254 54.19% 54.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 359 2.10% 56.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5270 30.86% 87.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1365 7.99% 95.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 405 2.37% 97.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 163 0.95% 98.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 106 0.62% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 62 0.36% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 41 0.24% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 19 0.11% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 11 0.06% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 5 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 3 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 3 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 3 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 2 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17076 # Writes before turning the bus around for reads +system.physmem.totQLat 8693371575 # Total ticks spent queuing +system.physmem.totMemAccLat 16595615325 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2107265000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20627.14 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40981.39 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 112.35 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 80.16 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 112.94 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 80.16 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39377.14 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 115.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 80.04 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 115.93 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 80.05 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.50 # Data bus utilization in percentage -system.physmem.busUtilRead 0.88 # Data bus utilization in percentage for reads +system.physmem.busUtil 1.53 # Data bus utilization in percentage +system.physmem.busUtilRead 0.90 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.84 # Average write queue length when enqueuing -system.physmem.readRowHits 299267 # Number of row buffer hits during reads -system.physmem.writeRowHits 95628 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.07 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.72 # Row buffer hit rate for writes -system.physmem.avgGap 331431.18 # Average gap between requests -system.physmem.pageHitRate 56.27 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1155833280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 630663000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1596964200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 942956640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15237983280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 74824379370 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 74344372500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 168733152270 # Total energy per rank (pJ) -system.physmem_0.averagePower 723.246471 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 123152752220 # Time in different power states -system.physmem_0.memoryStateTime::REF 7790380000 # Time in different power states +system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.60 # Average write queue length when enqueuing +system.physmem.readRowHits 306420 # Number of row buffer hits during reads +system.physmem.writeRowHits 85606 # Number of row buffer hits during writes +system.physmem.readRowHitRate 72.71 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 29.25 # Row buffer hit rate for writes +system.physmem.avgGap 326566.07 # Average gap between requests +system.physmem.pageHitRate 54.90 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1224553680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 668159250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1671883200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 942075360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15283753680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 82043634285 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 68432158500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 170266217955 # Total energy per rank (pJ) +system.physmem_0.averagePower 727.632069 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 113312610225 # Time in different power states +system.physmem_0.memoryStateTime::REF 7813780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 102358687280 # Time in different power states +system.physmem_0.memoryStateTime::ACT 112874154775 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1163673000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 634940625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1597073400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 950279040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15237983280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 74177760825 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 74911581750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 168673291920 # Total energy per rank (pJ) -system.physmem_1.averagePower 722.989890 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 124105976502 # Time in different power states -system.physmem_1.memoryStateTime::REF 7790380000 # Time in different power states +system.physmem_1.actEnergy 1210227480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 660342375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1615325400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 954218880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15283753680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 79914700530 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 70299646500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 169938214845 # Total energy per rank (pJ) +system.physmem_1.averagePower 726.230337 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 116426727240 # Time in different power states +system.physmem_1.memoryStateTime::REF 7813780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 101406021498 # Time in different power states +system.physmem_1.memoryStateTime::ACT 109759940510 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 175092094 # Number of BP lookups -system.cpu.branchPred.condPredicted 131341607 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7444018 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90535143 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83876326 # Number of BTB hits +system.cpu.branchPred.lookups 175128597 # Number of BP lookups +system.cpu.branchPred.condPredicted 131371974 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7444955 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90537565 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83893856 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.645047 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12109430 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104164 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.661931 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12111370 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104180 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -412,129 +421,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 466612055 # number of cpu cycles simulated +system.cpu.numCycles 468002595 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7841296 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 731804732 # Number of instructions fetch has processed -system.cpu.fetch.Branches 175092094 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 95985756 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 450426990 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14940841 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 5959 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 183 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 13996 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 236719309 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 34673 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 465758844 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.701594 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.179451 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7807530 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 731939592 # Number of instructions fetch has processed +system.cpu.fetch.Branches 175128597 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 96005226 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 452073756 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14942657 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 4553 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 179 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 11657 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 236761982 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 33954 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 467369003 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.696062 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.181505 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 93829138 20.15% 20.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132701430 28.49% 48.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57853582 12.42% 61.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 181374694 38.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95368751 20.41% 20.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132719598 28.40% 48.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57874720 12.38% 61.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 181405934 38.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 465758844 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.375241 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.568337 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32366390 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 117283842 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 287098365 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22028374 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6981873 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 24050011 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 496385 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 715808617 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 30003155 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6981873 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63420619 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 54156177 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40346363 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 276695654 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24158158 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 686602803 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13340804 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 9402338 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2387140 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1669358 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1928954 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 831026912 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3019223277 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 723937000 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 467369003 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.374204 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.563965 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32359971 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 118993599 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 286955454 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22077159 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6982820 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 24051378 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 496211 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 715838012 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 30014698 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6982820 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63444256 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 55810223 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40372652 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 276569326 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24189726 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 686622974 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13340540 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 9445783 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2386683 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1668073 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1901045 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 831058832 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3019300335 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 723953090 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 176903161 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1544702 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1535188 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 42285800 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 143529225 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67986348 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12855797 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11202653 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 668172379 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2978330 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 610256171 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5859842 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 123799764 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 319235639 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 698 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 465758844 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.310241 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.101448 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 176935081 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1544712 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1535132 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 42423418 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 143529755 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67982396 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12868793 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11217167 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 668185878 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2978339 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 610253474 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5862945 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 123813272 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 319307246 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 707 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 467369003 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.305721 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.102066 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 148618613 31.91% 31.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 101179975 21.72% 53.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 145721974 31.29% 84.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63321350 13.60% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6916462 1.48% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 470 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 150209828 32.14% 32.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 101164226 21.65% 53.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 145806231 31.20% 84.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63278562 13.54% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6909680 1.48% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 476 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 465758844 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 467369003 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71923603 52.95% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 30 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44560845 32.81% 85.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19351011 14.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71905667 52.96% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44557603 32.82% 85.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19305643 14.22% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413149972 67.70% 67.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 351777 0.06% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413150420 67.70% 67.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 351795 0.06% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued @@ -562,84 +571,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 134213690 21.99% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62540729 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 134216313 21.99% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62534943 10.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 610256171 # Type of FU issued -system.cpu.iq.rate 1.307845 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135835489 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.222588 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1827966224 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 794978756 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594986581 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 610253474 # Type of FU issued +system.cpu.iq.rate 1.303953 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135768943 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.222480 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1829507546 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 795005708 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594983942 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 746091483 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 746022240 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7271635 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 7274295 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27644469 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25562 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29008 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11125871 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27644999 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25509 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28969 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11121919 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 225728 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 22400 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 225058 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 22341 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6981873 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22924718 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 919849 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 672638124 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6982820 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22939909 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 921157 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 672651686 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 143529225 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67986348 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1489788 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 258699 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 524927 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29008 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3821848 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3731355 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7553203 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599403304 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129574600 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10852867 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 143529755 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67982396 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1489797 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 258383 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 526747 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28969 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3822799 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3731713 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7554512 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599398028 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129575309 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10855446 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1487415 # number of nop insts executed -system.cpu.iew.exec_refs 190539133 # number of memory reference insts executed -system.cpu.iew.exec_branches 131373270 # Number of branches executed -system.cpu.iew.exec_stores 60964533 # Number of stores executed -system.cpu.iew.exec_rate 1.284586 # Inst execution rate -system.cpu.iew.wb_sent 596281070 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594986597 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349903865 # num instructions producing a value -system.cpu.iew.wb_consumers 570650112 # num instructions consuming a value +system.cpu.iew.exec_nop 1487469 # number of nop insts executed +system.cpu.iew.exec_refs 190532110 # number of memory reference insts executed +system.cpu.iew.exec_branches 131373386 # Number of branches executed +system.cpu.iew.exec_stores 60956801 # Number of stores executed +system.cpu.iew.exec_rate 1.280758 # Inst execution rate +system.cpu.iew.wb_sent 596278477 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594983958 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349895185 # num instructions producing a value +system.cpu.iew.wb_consumers 570621697 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.275121 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.613167 # average fanout of values written-back +system.cpu.iew.wb_rate 1.271326 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.613182 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 110031903 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 110038028 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6955471 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 448643201 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.223009 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.887847 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6956447 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 450252376 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.218638 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.886273 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 219610457 48.95% 48.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116308832 25.92% 74.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43746420 9.75% 84.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23291517 5.19% 89.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11578245 2.58% 92.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7791027 1.74% 94.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8269909 1.84% 95.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4243315 0.95% 96.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13803479 3.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 221217275 49.13% 49.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116327442 25.84% 74.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43752953 9.72% 84.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23318372 5.18% 89.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11527046 2.56% 92.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7779334 1.73% 94.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8252081 1.83% 95.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4233959 0.94% 96.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13843914 3.07% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 448643201 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 450252376 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581608 # Number of instructions committed system.cpu.commit.committedOps 548694829 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -685,385 +694,391 @@ system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548694829 # Class of committed instruction -system.cpu.commit.bw_lim_events 13803479 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1093559316 # The number of ROB reads -system.cpu.rob.rob_writes 1334598854 # The number of ROB writes -system.cpu.timesIdled 13995 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 853211 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 13843914 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1095134181 # The number of ROB reads +system.cpu.rob.rob_writes 1334612111 # The number of ROB writes +system.cpu.timesIdled 12504 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 633592 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237724 # Number of Instructions Simulated system.cpu.committedOps 547350945 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.923550 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.923550 # CPI: Total CPI of All Threads -system.cpu.ipc 1.082779 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.082779 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 611100755 # number of integer regfile reads -system.cpu.int_regfile_writes 328116502 # number of integer regfile writes +system.cpu.cpi 0.926302 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.926302 # CPI: Total CPI of All Threads +system.cpu.ipc 1.079562 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.079562 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 611088799 # number of integer regfile reads +system.cpu.int_regfile_writes 328120173 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2170188783 # number of cc regfile reads -system.cpu.cc_regfile_writes 376538117 # number of cc regfile writes -system.cpu.misc_regfile_reads 217976814 # number of misc regfile reads +system.cpu.cc_regfile_reads 2170182732 # number of cc regfile reads +system.cpu.cc_regfile_writes 376542810 # number of cc regfile writes +system.cpu.misc_regfile_reads 217972310 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2820876 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.631746 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 169355780 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2821388 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 60.025697 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 498153000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.631746 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999281 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999281 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2820726 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.629844 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 169352944 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2821238 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 60.027883 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 500883000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.629844 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999277 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999277 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 281 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 356248226 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 356248226 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114651895 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114651895 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51723951 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51723951 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2787 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2787 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488560 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488560 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 356245422 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 356245422 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114648159 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114648159 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51724842 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51724842 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2783 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2783 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488558 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488558 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 166375846 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 166375846 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 166378633 # number of overall hits -system.cpu.dcache.overall_hits::total 166378633 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4842252 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4842252 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2515355 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2515355 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 166373001 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 166373001 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 166375784 # number of overall hits +system.cpu.dcache.overall_hits::total 166375784 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4844666 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4844666 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2514464 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2514464 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7357607 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7357607 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7357619 # number of overall misses -system.cpu.dcache.overall_misses::total 7357619 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 56173880000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 56173880000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19052445440 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19052445440 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1310000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1310000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 75226325440 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 75226325440 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 75226325440 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 75226325440 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 119494147 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 119494147 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_misses::cpu.data 67 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 67 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 7359130 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7359130 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7359142 # number of overall misses +system.cpu.dcache.overall_misses::total 7359142 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57569719500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57569719500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18925127941 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18925127941 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 941000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 941000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 76494847441 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 76494847441 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 76494847441 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 76494847441 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119492825 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119492825 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2799 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2799 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488626 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488626 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2795 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2795 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488625 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488625 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173733453 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173733453 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173736252 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173736252 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040523 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040523 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046375 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046375 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004287 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.004287 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.042350 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.042350 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.042349 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.042349 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11600.775837 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11600.775837 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7574.455868 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7574.455868 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19848.484848 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19848.484848 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10224.292415 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10224.292415 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10224.275739 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10224.275739 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 92 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 932011 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 221163 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 4.214136 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 173732131 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173732131 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173734926 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173734926 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040544 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040544 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046359 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046359 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004293 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.004293 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000045 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000045 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.042359 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.042359 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042358 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042358 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11883.114233 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11883.114233 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7526.505824 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7526.505824 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14044.776119 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14044.776119 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10394.550367 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10394.550367 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10394.533417 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10394.533417 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 17 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 905651 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 221227 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4.093763 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2352880 # number of writebacks -system.cpu.dcache.writebacks::total 2352880 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2540436 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2540436 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1995769 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1995769 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4536205 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4536205 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4536205 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4536205 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301816 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2301816 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519586 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519586 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 2820726 # number of writebacks +system.cpu.dcache.writebacks::total 2820726 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2542974 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2542974 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1994900 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1994900 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 67 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 67 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 4537874 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4537874 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4537874 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4537874 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301692 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2301692 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519564 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 519564 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2821402 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2821402 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2821412 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2821412 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28692574000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 28692574000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4617588494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4617588494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 686000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 686000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33310162494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 33310162494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33310848494 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 33310848494 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019263 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019263 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009580 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009580 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003573 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003573 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016240 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016240 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016240 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.016240 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12465.190093 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12465.190093 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8887.053335 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8887.053335 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68600 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68600 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11806.244730 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11806.244730 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11806.446026 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11806.446026 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_misses::cpu.data 2821256 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2821256 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2821266 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2821266 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29568664500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 29568664500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4603651495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4603651495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 644000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 644000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 34172315995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 34172315995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 34172959995 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 34172959995 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019262 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019262 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009579 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009579 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003578 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003578 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016239 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016239 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016239 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.016239 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12846.490538 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12846.490538 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8860.605229 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8860.605229 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 64400 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 64400 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12112.447787 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12112.447787 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12112.633121 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12112.633121 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 73459 # number of replacements -system.cpu.icache.tags.tagsinuse 466.213956 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 236636536 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 73971 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3199.044707 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 114942017500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 466.213956 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.910574 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.910574 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 73505 # number of replacements +system.cpu.icache.tags.tagsinuse 466.324466 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 236680067 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 74017 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3197.644690 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 115567558500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 466.324466 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.910790 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.910790 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 16 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 473512362 # Number of tag accesses -system.cpu.icache.tags.data_accesses 473512362 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 236636536 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 236636536 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 236636536 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 236636536 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 236636536 # number of overall hits -system.cpu.icache.overall_hits::total 236636536 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 82647 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 82647 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 82647 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 82647 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 82647 # number of overall misses -system.cpu.icache.overall_misses::total 82647 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1564864673 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1564864673 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1564864673 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1564864673 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1564864673 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1564864673 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 236719183 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 236719183 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 236719183 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 236719183 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 236719183 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 236719183 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000349 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000349 # 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number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 335947000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 335947000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 538896500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 538896500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10864639500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10864639500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 538896500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11200586500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11739483000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 538896500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11200586500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18662693863 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30402176863 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.041667 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.041667 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007014 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007014 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.144425 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.144425 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.060750 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.060750 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.144425 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.050809 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.053201 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.144425 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.050809 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007070 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007070 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.109263 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.109263 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.067242 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.067242 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.109263 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056109 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.057468 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.109263 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056109 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.148304 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69356.062148 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69356.062148 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92304.151871 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92304.151871 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67648.272957 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67648.272957 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71343.207508 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71343.207508 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67648.272957 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71878.519309 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71585.133249 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67648.272957 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71878.519309 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69356.062148 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70155.690850 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.178650 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53192.648341 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53192.648341 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17178.571429 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17178.571429 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91042.547425 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91042.547425 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66637.380982 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66637.380982 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70272.168969 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70272.168969 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66637.380982 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70756.336151 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70556.137873 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66637.380982 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70756.336151 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53192.648341 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58778.153228 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5789744 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2894372 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23770 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 30234 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 30144 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 2373438 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2645111 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 626124 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 317103 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 521946 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 521946 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 73997 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299442 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220575 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8440808 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8661383 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4733952 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331153152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 335887104 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 717772 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6507488 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.011967 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.108866 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 5789543 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2894272 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23735 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 260412 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244232 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16180 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 2373325 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2649267 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 513929 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 265680 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 392283 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 28 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 28 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 521957 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 521957 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 74046 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299281 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220710 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8440410 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8661120 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9386496 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 359623424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 369009920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 950663 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3845942 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.078099 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.283574 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 6429701 98.80% 98.80% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 77697 1.19% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 90 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3561756 92.61% 92.61% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 268006 6.97% 99.58% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 16180 0.42% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6507488 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5247752000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 111080826 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3845942 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5789002505 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 111143345 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4232108471 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4231890461 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.trans_dist::ReadResp 408044 # Transaction distribution -system.membus.trans_dist::Writeback 292231 # Transaction distribution -system.membus.trans_dist::CleanEvict 102781 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 3660 # Transaction distribution -system.membus.trans_dist::ReadExResp 3660 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 408044 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1218424 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1218424 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45051840 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 45051840 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 420198 # Transaction distribution +system.membus.trans_dist::WritebackDirty 292667 # Transaction distribution +system.membus.trans_dist::CleanEvict 98618 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33 # Transaction distribution +system.membus.trans_dist::UpgradeResp 33 # Transaction distribution +system.membus.trans_dist::ReadExReq 3685 # Transaction distribution +system.membus.trans_dist::ReadExResp 3685 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 420199 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1239118 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1239118 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45859200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45859200 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 806718 # Request fanout histogram +system.membus.snoop_fanout::samples 815202 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 806718 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 815202 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 806718 # Request fanout histogram -system.membus.reqLayer0.occupancy 2171550377 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 815202 # Request fanout histogram +system.membus.reqLayer0.occupancy 2212929834 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2176359308 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 2242544064 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index ad7524f92..d23424e24 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.707537 # Number of seconds simulated -sim_ticks 707536959500 # Number of ticks simulated -final_tick 707536959500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.708526 # Number of seconds simulated +sim_ticks 708526400500 # Number of ticks simulated +final_tick 708526400500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1064510 # Simulator instruction rate (inst/s) -host_op_rate 1152817 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1491485099 # Simulator tick rate (ticks/s) -host_mem_usage 319084 # Number of bytes of host memory used -host_seconds 474.38 # Real time elapsed on the host +host_inst_rate 974268 # Simulator instruction rate (inst/s) +host_op_rate 1055088 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1366955379 # Simulator tick rate (ticks/s) +host_mem_usage 319428 # Number of bytes of host memory used +host_seconds 518.32 # Real time elapsed on the host sim_insts 504986854 # Number of instructions simulated sim_ops 546878105 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 175360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8946752 # Number of bytes read from this memory -system.physmem.bytes_read::total 9122112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 175360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 175360 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6146048 # Number of bytes written to this memory -system.physmem.bytes_written::total 6146048 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2740 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 139793 # Number of read requests responded to by this memory -system.physmem.num_reads::total 142533 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96032 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96032 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 247846 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12644925 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12892771 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 247846 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 247846 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8686540 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8686540 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8686540 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 247846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12644925 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21579311 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8963904 # Number of bytes read from this memory +system.physmem.bytes_read::total 9111296 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 147392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 147392 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6165120 # Number of bytes written to this memory +system.physmem.bytes_written::total 6165120 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2303 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140061 # Number of read requests responded to by this memory +system.physmem.num_reads::total 142364 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96330 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96330 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 208026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12651475 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12859501 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 208026 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 208026 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8701327 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8701327 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8701327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 208026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12651475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21560828 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 1415073919 # number of cpu cycles simulated +system.cpu.numCycles 1417052801 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 504986854 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 172745235 # nu system.cpu.num_load_insts 115884756 # Number of load instructions system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1415073918.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1417052800.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 121548302 # Number of branches fetched @@ -215,14 +215,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548695379 # Class of executed instruction system.cpu.dcache.tags.replacements 1134822 # number of replacements -system.cpu.dcache.tags.tagsinuse 4065.318106 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4065.260615 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 11716435500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318106 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 11750119500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4065.260615 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992495 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992495 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id @@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data 1138917 # n system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses system.cpu.dcache.overall_misses::total 1138918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11820971000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11820971000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8866220000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8866220000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20687191000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20687191000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20687191000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20687191000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12104797500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12104797500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9574077500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9574077500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 21678875000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 21678875000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 21678875000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 21678875000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) @@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15103.641825 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15103.641825 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24886.936507 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24886.936507 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18163.914491 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18163.914491 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18163.898542 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18163.898542 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15466.286636 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15466.286636 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26873.849155 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26873.849155 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19034.639925 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19034.639925 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19034.623213 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19034.623213 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -304,8 +304,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1064880 # number of writebacks -system.cpu.dcache.writebacks::total 1064880 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1064678 # number of writebacks +system.cpu.dcache.writebacks::total 1064678 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782657 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 782657 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses @@ -316,16 +316,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11038314000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11038314000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8509960000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8509960000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19548274000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 19548274000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19548328000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19548328000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11322140500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11322140500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9217817500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9217817500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20539958000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 20539958000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20540019000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20540019000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses @@ -336,26 +336,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14103.641825 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14103.641825 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23886.936507 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23886.936507 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17163.914491 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17163.914491 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17163.946834 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17163.946834 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14466.286636 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14466.286636 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25873.849155 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25873.849155 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18034.639925 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18034.639925 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18034.677650 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18034.677650 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 9788 # number of replacements -system.cpu.icache.tags.tagsinuse 983.371232 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 983.180611 # Cycle average of tags in use system.cpu.icache.tags.total_refs 516599856 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 44839.845152 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 983.371232 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.480162 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.480162 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 983.180611 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.480069 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.480069 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id @@ -377,12 +377,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses system.cpu.icache.overall_misses::total 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 265444000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 265444000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 265444000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 265444000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 265444000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 265444000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 263208000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 263208000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 263208000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 263208000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 263208000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 263208000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 516611377 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 516611377 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 516611377 # number of demand (read+write) accesses @@ -395,12 +395,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23040.013888 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23040.013888 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23040.013888 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23040.013888 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23040.013888 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23040.013888 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22845.933513 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22845.933513 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22845.933513 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22845.933513 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22845.933513 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22845.933513 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -409,92 +409,98 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 9788 # number of writebacks +system.cpu.icache.writebacks::total 9788 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253923000 # 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number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 251687000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22040.013888 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22040.013888 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22040.013888 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22040.013888 # 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number of replacements -system.cpu.l2cache.tags.tagsinuse 27249.077163 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1743796 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 140956 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.371208 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 338494154000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23345.006122 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.705462 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3616.365578 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.712433 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008780 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.110363 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.831576 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31177 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.l2cache.tags.replacements 110394 # number of replacements +system.cpu.l2cache.tags.tagsinuse 27250.637055 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1744409 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 141582 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.320839 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 339114860000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23374.350264 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.190674 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3636.096117 # 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Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18829920 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 1064880 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1064880 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 255527 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 255527 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8781 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 8781 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 743598 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 743598 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8781 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 999125 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1007906 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8781 # 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number of overall misses -system.cpu.l2cache.overall_misses::total 142533 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5292536500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5292536500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 144147000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 144147000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2053419500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2053419500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 144147000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7345956000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7490103000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 144147000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7345956000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7490103000 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 1064880 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1064880 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27176 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 18830546 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18830546 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 1064678 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 1064678 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 9751 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 9751 # 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number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6000938500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 137230000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 137230000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2339453000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2339453000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 137230000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8340391500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8477621500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 137230000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8340391500 # 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number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282751 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.282751 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.237827 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.237827 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.049907 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.049907 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.237827 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.122742 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.123894 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.237827 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.122742 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.123894 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52540.245004 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52540.245004 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52608.394161 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52608.394161 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52570.903738 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52570.903738 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52608.394161 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52548.811457 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52549.956852 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52608.394161 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52548.811457 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52549.956852 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282906 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.282906 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.199896 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.199896 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050179 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050179 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.199896 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.122977 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.123748 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.199896 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.122977 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.123748 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59540.208160 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59540.208160 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59587.494572 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59587.494572 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59568.991419 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59568.991419 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59587.494572 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59548.278964 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59548.913349 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59587.494572 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59548.278964 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59548.913349 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -539,70 +545,71 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 96032 # number of writebacks -system.cpu.l2cache.writebacks::total 96032 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 792 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 792 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100733 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100733 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2740 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2740 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39060 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39060 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2740 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 139793 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 142533 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2740 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 139793 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 142533 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4285206500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4285206500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 116747000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 116747000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1662819500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1662819500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116747000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5948026000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6064773000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116747000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5948026000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6064773000 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 96330 # number of writebacks +system.cpu.l2cache.writebacks::total 96330 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100788 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100788 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2303 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2303 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39273 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39273 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2303 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 140061 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 142364 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2303 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 140061 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 142364 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4993058500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4993058500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 114200000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 114200000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1946723000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1946723000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6939781500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7053981500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6939781500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7053981500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282751 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282751 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.237827 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.237827 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.049907 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.049907 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.237827 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122742 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123894 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.237827 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122742 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123894 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42540.245004 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42540.245004 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42608.394161 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42608.394161 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42570.903738 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42570.903738 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42608.394161 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42548.811457 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42549.956852 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42608.394161 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42548.811457 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42549.956852 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282906 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282906 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.199896 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050179 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050179 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122977 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123748 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122977 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123748 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49540.208160 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49540.208160 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49587.494572 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49587.494572 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49568.991419 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49568.991419 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49587.494572 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49548.278964 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.913349 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49587.494572 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.278964 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.913349 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 2295049 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1144662 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3461 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2140 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2139 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2146 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1160912 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 90016 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1161008 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 9751 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 80784 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution @@ -610,51 +617,51 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 782658 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32793 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3409234 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 3442027 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141043072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 141780416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 109779 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2404828 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.003790 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.061455 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1361408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141030144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142391552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 110394 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1260833 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004489 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.066862 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2395714 99.62% 99.62% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 9113 0.38% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1255174 99.55% 99.55% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5658 0.45% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2404828 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2212404500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1260833 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2221990500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1708377000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 41800 # Transaction distribution -system.membus.trans_dist::Writeback 96032 # Transaction distribution -system.membus.trans_dist::CleanEvict 12399 # Transaction distribution -system.membus.trans_dist::ReadExReq 100733 # Transaction distribution -system.membus.trans_dist::ReadExResp 100733 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 41800 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393497 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 393497 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15268160 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15268160 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 41576 # Transaction distribution +system.membus.trans_dist::WritebackDirty 96330 # Transaction distribution +system.membus.trans_dist::CleanEvict 11920 # Transaction distribution +system.membus.trans_dist::ReadExReq 100788 # Transaction distribution +system.membus.trans_dist::ReadExResp 100788 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 41576 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392978 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 392978 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15276416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15276416 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 251058 # Request fanout histogram +system.membus.snoop_fanout::samples 250615 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 251058 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 250615 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 251058 # Request fanout histogram -system.membus.reqLayer0.occupancy 643796492 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 250615 # Request fanout histogram +system.membus.reqLayer0.occupancy 644475328 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 719009164 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 711820000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 987362254..e3c4d5903 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.403931 # Number of seconds simulated -sim_ticks 403931323500 # Number of ticks simulated -final_tick 403931323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.403830 # Number of seconds simulated +sim_ticks 403830091000 # Number of ticks simulated +final_tick 403830091000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95186 # Simulator instruction rate (inst/s) -host_op_rate 176009 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46498470 # Simulator tick rate (ticks/s) -host_mem_usage 433064 # Number of bytes of host memory used -host_seconds 8686.98 # Real time elapsed on the host +host_inst_rate 95719 # Simulator instruction rate (inst/s) +host_op_rate 176996 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46747318 # Simulator tick rate (ticks/s) +host_mem_usage 431916 # Number of bytes of host memory used +host_seconds 8638.57 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 217984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24500544 # Number of bytes read from this memory -system.physmem.bytes_read::total 24718528 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18869632 # Number of bytes written to this memory -system.physmem.bytes_written::total 18869632 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3406 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382821 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386227 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 294838 # Number of write requests responded to by this memory -system.physmem.num_writes::total 294838 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 539656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 60655222 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 61194878 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 539656 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 539656 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 46714951 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 46714951 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 46714951 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 539656 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 60655222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 107909829 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386228 # Number of read requests accepted -system.physmem.writeReqs 294838 # Number of write requests accepted -system.physmem.readBursts 386228 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 294838 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24699456 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19136 # Total number of bytes read from write queue -system.physmem.bytesWritten 18868032 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24718592 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18869632 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 299 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 163776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24545280 # Number of bytes read from this memory +system.physmem.bytes_read::total 24709056 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 163776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 163776 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18890432 # Number of bytes written to this memory +system.physmem.bytes_written::total 18890432 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2559 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 383520 # Number of read requests responded to by this memory +system.physmem.num_reads::total 386079 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 295163 # Number of write requests responded to by this memory +system.physmem.num_writes::total 295163 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 405557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 60781206 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 61186763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 405557 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 405557 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 46778168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 46778168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 46778168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 405557 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 60781206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 107964931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 386079 # Number of read requests accepted +system.physmem.writeReqs 295163 # Number of write requests accepted +system.physmem.readBursts 386079 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 295163 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24689408 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue +system.physmem.bytesWritten 18889088 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24709056 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18890432 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 196128 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24062 # Per bank write bursts -system.physmem.perBankRdBursts::1 26430 # Per bank write bursts -system.physmem.perBankRdBursts::2 24903 # Per bank write bursts -system.physmem.perBankRdBursts::3 24577 # Per bank write bursts -system.physmem.perBankRdBursts::4 23181 # Per bank write bursts -system.physmem.perBankRdBursts::5 23704 # Per bank write bursts -system.physmem.perBankRdBursts::6 24550 # Per bank write bursts -system.physmem.perBankRdBursts::7 24303 # Per bank write bursts -system.physmem.perBankRdBursts::8 23663 # Per bank write bursts -system.physmem.perBankRdBursts::9 23568 # Per bank write bursts -system.physmem.perBankRdBursts::10 24789 # Per bank write bursts -system.physmem.perBankRdBursts::11 23975 # Per bank write bursts -system.physmem.perBankRdBursts::12 23330 # Per bank write bursts -system.physmem.perBankRdBursts::13 22932 # Per bank write bursts -system.physmem.perBankRdBursts::14 24089 # Per bank write bursts -system.physmem.perBankRdBursts::15 23873 # Per bank write bursts -system.physmem.perBankWrBursts::0 18604 # Per bank write bursts -system.physmem.perBankWrBursts::1 19922 # Per bank write bursts -system.physmem.perBankWrBursts::2 19191 # Per bank write bursts -system.physmem.perBankWrBursts::3 18985 # Per bank write bursts -system.physmem.perBankWrBursts::4 18090 # Per bank write bursts -system.physmem.perBankWrBursts::5 18485 # Per bank write bursts -system.physmem.perBankWrBursts::6 19138 # Per bank write bursts -system.physmem.perBankWrBursts::7 19082 # Per bank write bursts -system.physmem.perBankWrBursts::8 18642 # Per bank write bursts -system.physmem.perBankWrBursts::9 17946 # Per bank write bursts -system.physmem.perBankWrBursts::10 18887 # Per bank write bursts -system.physmem.perBankWrBursts::11 17737 # Per bank write bursts -system.physmem.perBankWrBursts::12 17398 # Per bank write bursts -system.physmem.perBankWrBursts::13 16988 # Per bank write bursts -system.physmem.perBankWrBursts::14 17875 # Per bank write bursts -system.physmem.perBankWrBursts::15 17843 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 251728 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24087 # Per bank write bursts +system.physmem.perBankRdBursts::1 26440 # Per bank write bursts +system.physmem.perBankRdBursts::2 24835 # Per bank write bursts +system.physmem.perBankRdBursts::3 24498 # Per bank write bursts +system.physmem.perBankRdBursts::4 23219 # Per bank write bursts +system.physmem.perBankRdBursts::5 23721 # Per bank write bursts +system.physmem.perBankRdBursts::6 24501 # Per bank write bursts +system.physmem.perBankRdBursts::7 24288 # Per bank write bursts +system.physmem.perBankRdBursts::8 23633 # Per bank write bursts +system.physmem.perBankRdBursts::9 23532 # Per bank write bursts +system.physmem.perBankRdBursts::10 24814 # Per bank write bursts +system.physmem.perBankRdBursts::11 23996 # Per bank write bursts +system.physmem.perBankRdBursts::12 23302 # Per bank write bursts +system.physmem.perBankRdBursts::13 22925 # Per bank write bursts +system.physmem.perBankRdBursts::14 24085 # Per bank write bursts +system.physmem.perBankRdBursts::15 23896 # Per bank write bursts +system.physmem.perBankWrBursts::0 18615 # Per bank write bursts +system.physmem.perBankWrBursts::1 19935 # Per bank write bursts +system.physmem.perBankWrBursts::2 19196 # Per bank write bursts +system.physmem.perBankWrBursts::3 19026 # Per bank write bursts +system.physmem.perBankWrBursts::4 18118 # Per bank write bursts +system.physmem.perBankWrBursts::5 18514 # Per bank write bursts +system.physmem.perBankWrBursts::6 19142 # Per bank write bursts +system.physmem.perBankWrBursts::7 19086 # Per bank write bursts +system.physmem.perBankWrBursts::8 18651 # Per bank write bursts +system.physmem.perBankWrBursts::9 17953 # Per bank write bursts +system.physmem.perBankWrBursts::10 18925 # Per bank write bursts +system.physmem.perBankWrBursts::11 17775 # Per bank write bursts +system.physmem.perBankWrBursts::12 17401 # Per bank write bursts +system.physmem.perBankWrBursts::13 17016 # Per bank write bursts +system.physmem.perBankWrBursts::14 17907 # Per bank write bursts +system.physmem.perBankWrBursts::15 17882 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 403931308500 # Total gap between requests +system.physmem.totGap 403830049500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386228 # Read request sizes (log2) +system.physmem.readPktSize::6 386079 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 294838 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 380968 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 308 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 295163 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 380933 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4500 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -144,46 +144,46 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17651 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see @@ -193,248 +193,248 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 146866 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.637860 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 175.325639 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.046473 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54140 36.86% 36.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 39981 27.22% 64.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13765 9.37% 73.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7667 5.22% 78.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5371 3.66% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3914 2.67% 85.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3025 2.06% 87.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2731 1.86% 88.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16272 11.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 146866 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17494 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.060078 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 218.173610 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17485 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 4 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 3 0.02% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 146827 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 296.793805 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 175.429172 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 322.898216 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54192 36.91% 36.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 39812 27.11% 64.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13750 9.36% 73.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7660 5.22% 78.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5440 3.71% 82.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4000 2.72% 85.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3009 2.05% 87.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2793 1.90% 88.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16171 11.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 146827 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17508 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.033813 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 216.830406 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17497 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 6 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7168-8191 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17494 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17494 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.852235 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.776145 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.682764 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17296 98.87% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 143 0.82% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 28 0.16% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 5 0.03% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 3 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 3 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 1 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 1 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 3 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17508 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17508 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.857551 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.779124 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.831180 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17335 99.01% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 121 0.69% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 25 0.14% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 8 0.05% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 2 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 2 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 2 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::108-111 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17494 # Writes before turning the bus around for reads -system.physmem.totQLat 4291077750 # Total ticks spent queuing -system.physmem.totMemAccLat 11527246500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1929645000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11118.83 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 17508 # Writes before turning the bus around for reads +system.physmem.totQLat 4276128000 # Total ticks spent queuing +system.physmem.totMemAccLat 11509353000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1928860000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11084.60 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29868.83 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 61.15 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 46.71 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 61.20 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 46.71 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29834.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 61.14 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 46.77 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 61.19 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 46.78 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.84 # Data bus utilization in percentage system.physmem.busUtilRead 0.48 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.37 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.35 # Average write queue length when enqueuing -system.physmem.readRowHits 317989 # Number of row buffer hits during reads -system.physmem.writeRowHits 215873 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.22 # Row buffer hit rate for writes -system.physmem.avgGap 593086.88 # Average gap between requests -system.physmem.pageHitRate 78.42 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 567438480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 309614250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1526405400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 981499680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26382567120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 62258546970 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 187743770250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 279769842150 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.623817 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 311776883750 # Time in different power states -system.physmem_0.memoryStateTime::REF 13488020000 # Time in different power states +system.physmem.avgWrQLen 21.79 # Average write queue length when enqueuing +system.physmem.readRowHits 318168 # Number of row buffer hits during reads +system.physmem.writeRowHits 215906 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.15 # Row buffer hit rate for writes +system.physmem.avgGap 592785.02 # Average gap between requests +system.physmem.pageHitRate 78.43 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 567876960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 309853500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1525477200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 982432800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26375955840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 62051510430 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 187864648500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 279677755230 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.569390 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 311979208000 # Time in different power states +system.physmem_0.memoryStateTime::REF 13484640000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 78662661250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 78362495750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 542467800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 295989375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1483341600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 928473840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26382567120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 60448758210 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 189331310250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 279412908195 # Total energy per rank (pJ) -system.physmem_1.averagePower 691.740141 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 314432491250 # Time in different power states -system.physmem_1.memoryStateTime::REF 13488020000 # Time in different power states +system.physmem_1.actEnergy 541779840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 295614000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1483021800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 929672640 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26375955840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 60320910060 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 189382719000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 279329673180 # Total energy per rank (pJ) +system.physmem_1.averagePower 691.707431 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 314516116250 # Time in different power states +system.physmem_1.memoryStateTime::REF 13484640000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 76007072500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 75825587500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 219314839 # Number of BP lookups -system.cpu.branchPred.condPredicted 219314839 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 8530231 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 123981217 # Number of BTB lookups -system.cpu.branchPred.BTBHits 121825604 # Number of BTB hits +system.cpu.branchPred.lookups 219264229 # Number of BP lookups +system.cpu.branchPred.condPredicted 219264229 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 8531047 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 124002696 # Number of BTB lookups +system.cpu.branchPred.BTBHits 121802201 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.261339 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 27068206 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1407908 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.225446 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 27063113 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1406921 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 807862648 # number of cpu cycles simulated +system.cpu.numCycles 807660183 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 175941692 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1208657835 # Number of instructions fetch has processed -system.cpu.fetch.Branches 219314839 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 148893810 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 622000001 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 17769177 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 227 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 92380 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 735169 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1433 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 170789403 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2323822 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 807655519 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.784658 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.367182 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 175911242 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1208663462 # Number of instructions fetch has processed +system.cpu.fetch.Branches 219264229 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 148865314 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 621862787 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 17775835 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 233 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 94904 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 745978 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1264 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 170762091 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2319100 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 807504342 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.785127 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.367664 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 417598750 51.71% 51.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 32531773 4.03% 55.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31857083 3.94% 59.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 32716073 4.05% 63.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26594170 3.29% 67.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 26933309 3.33% 70.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 35181908 4.36% 74.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 31423846 3.89% 78.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 172818607 21.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 417532473 51.71% 51.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 32497368 4.02% 55.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31891068 3.95% 59.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 32657877 4.04% 63.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26554759 3.29% 67.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 26902865 3.33% 70.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 35168137 4.36% 74.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 31391832 3.89% 78.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 172907963 21.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 807655519 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.271475 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.496118 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 120412218 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 371076736 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 225209960 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 82072017 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8884588 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2132095724 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 8884588 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 152556291 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 150817488 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 41958 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 271423783 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 223931411 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2088526658 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 137354 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 138380994 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 24891978 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 50561951 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2190720490 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5278322969 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3357144423 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 60320 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 807504342 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.271481 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.496500 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 120449956 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 370877919 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 225251519 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 82037031 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8887917 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2132109647 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 8887917 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 152555499 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 150771591 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 44475 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 271462113 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 223782747 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2088438662 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 138448 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 138151621 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 24868058 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 50731794 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2190645258 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5278038161 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3357041251 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 59967 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 576679636 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3187 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2956 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 423114583 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 507122992 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 200812983 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 229080264 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 68423458 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2023133283 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22942 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1788928106 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 421261 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 494167524 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 833180412 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 22390 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 807655519 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.214964 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.070282 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 576604404 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3331 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3057 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 422478077 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 507119798 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 200816388 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 229077730 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 68200212 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2023068034 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22911 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1788999576 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 413303 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 494102244 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 832764755 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 22359 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 807504342 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.215467 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.071001 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 238829466 29.57% 29.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 123732265 15.32% 44.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 119115162 14.75% 59.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 107661207 13.33% 72.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 89581047 11.09% 84.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 60232277 7.46% 91.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 42307619 5.24% 96.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 18921199 2.34% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7275277 0.90% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 238908265 29.59% 29.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 123628552 15.31% 44.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 118817632 14.71% 59.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 107769877 13.35% 72.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 89573603 11.09% 84.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 60241832 7.46% 91.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 42310466 5.24% 96.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 18973159 2.35% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7280956 0.90% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 807655519 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 807504342 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11512552 42.68% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12355843 45.81% 88.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3105832 11.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11498712 42.77% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12295029 45.73% 88.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3093590 11.51% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2718297 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1183078959 66.13% 66.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 370517 0.02% 66.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3881151 0.22% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 134 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2718967 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1183065523 66.13% 66.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 369413 0.02% 66.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3881231 0.22% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 133 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 67 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 365 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 60 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 380 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued @@ -456,84 +456,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.52% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 428492741 23.95% 90.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170385875 9.52% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 428545273 23.95% 90.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170418596 9.53% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1788928106 # Type of FU issued -system.cpu.iq.rate 2.214396 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26974227 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015078 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4412876800 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2517572556 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1762303286 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 30419 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 69720 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 5693 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1813170766 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 13270 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 186079397 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1788999576 # Type of FU issued +system.cpu.iq.rate 2.215040 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26887331 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015029 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4412774566 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2517442986 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1762358918 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 29562 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 69250 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 5611 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1813154984 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12956 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 186087729 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 123023075 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 212257 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 371984 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 51652797 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 123020037 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 213128 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 372787 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 51656202 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 22860 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1101 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 22930 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1078 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8884588 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 97906785 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6199562 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2023156225 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 370486 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 507125232 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 200812983 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7241 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1822287 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3474512 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 371984 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4845065 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4137242 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8982307 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1769932780 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 423113153 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 18995326 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8887917 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 97798502 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6162253 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2023090945 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 375323 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 507122194 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 200816388 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7129 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1832886 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3426694 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 372787 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4845812 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4140641 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8986453 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1769991187 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 423150453 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19008389 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 590301691 # number of memory reference insts executed -system.cpu.iew.exec_branches 168980249 # Number of branches executed -system.cpu.iew.exec_stores 167188538 # Number of stores executed -system.cpu.iew.exec_rate 2.190883 # Inst execution rate -system.cpu.iew.wb_sent 1766804374 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1762308979 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1339663552 # num instructions producing a value -system.cpu.iew.wb_consumers 2049989844 # num instructions consuming a value +system.cpu.iew.exec_refs 590375275 # number of memory reference insts executed +system.cpu.iew.exec_branches 168976940 # Number of branches executed +system.cpu.iew.exec_stores 167224822 # Number of stores executed +system.cpu.iew.exec_rate 2.191505 # Inst execution rate +system.cpu.iew.wb_sent 1766866321 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1762364529 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1339720871 # num instructions producing a value +system.cpu.iew.wb_consumers 2049946578 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.181446 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.653498 # average fanout of values written-back +system.cpu.iew.wb_rate 2.182062 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.653539 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 494228972 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 494164798 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8612841 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 740434686 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.064988 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.575030 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 8615583 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 740300612 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.065362 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.575682 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 276267324 37.31% 37.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 172135150 23.25% 60.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 56000087 7.56% 68.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 86333753 11.66% 79.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25859703 3.49% 83.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26527369 3.58% 86.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9854605 1.33% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9004729 1.22% 89.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 78451966 10.60% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 276280439 37.32% 37.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 172026383 23.24% 60.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 56011691 7.57% 68.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86227626 11.65% 79.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25892196 3.50% 83.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26512378 3.58% 86.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9839162 1.33% 88.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8995484 1.22% 89.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 78515253 10.61% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 740434686 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 740300612 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -579,344 +579,350 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 78451966 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2685200393 # The number of ROB reads -system.cpu.rob.rob_writes 4113829657 # The number of ROB writes -system.cpu.timesIdled 2326 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 207129 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 78515253 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2684938858 # The number of ROB reads +system.cpu.rob.rob_writes 4113685431 # The number of ROB writes +system.cpu.timesIdled 1962 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 155841 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.977004 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.977004 # CPI: Total CPI of All Threads -system.cpu.ipc 1.023537 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.023537 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2722489562 # number of integer regfile reads -system.cpu.int_regfile_writes 1435790744 # number of integer regfile writes -system.cpu.fp_regfile_reads 5969 # number of floating regfile reads -system.cpu.fp_regfile_writes 521 # number of floating regfile writes -system.cpu.cc_regfile_reads 596647275 # number of cc regfile reads -system.cpu.cc_regfile_writes 405463698 # number of cc regfile writes -system.cpu.misc_regfile_reads 971582048 # number of misc regfile reads +system.cpu.cpi 0.976760 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.976760 # CPI: Total CPI of All Threads +system.cpu.ipc 1.023793 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.023793 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2722687854 # number of integer regfile reads +system.cpu.int_regfile_writes 1435809850 # number of integer regfile writes +system.cpu.fp_regfile_reads 5827 # number of floating regfile reads +system.cpu.fp_regfile_writes 561 # number of floating regfile writes +system.cpu.cc_regfile_reads 596681162 # number of cc regfile reads +system.cpu.cc_regfile_writes 405470892 # number of cc regfile writes +system.cpu.misc_regfile_reads 971641846 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2530897 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.817920 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 381840179 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2534993 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.627705 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2530997 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.815869 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 381868965 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2535093 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.633119 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1673396500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.817920 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.815869 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.998002 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.998002 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 865 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3173 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3178 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 772772413 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 772772413 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 233184165 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 233184165 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148172813 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148172813 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 381356978 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 381356978 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 381356978 # number of overall hits -system.cpu.dcache.overall_hits::total 381356978 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2774343 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2774343 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 987389 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 987389 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3761732 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3761732 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3761732 # number of overall misses -system.cpu.dcache.overall_misses::total 3761732 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 59119368500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 59119368500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31296279995 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31296279995 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 90415648495 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 90415648495 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 90415648495 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 90415648495 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 235958508 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 235958508 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 772828805 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 772828805 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 233213748 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 233213748 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148173817 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148173817 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 381387565 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 381387565 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 381387565 # number of overall hits +system.cpu.dcache.overall_hits::total 381387565 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2772906 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2772906 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 986385 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 986385 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3759291 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3759291 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3759291 # number of overall misses +system.cpu.dcache.overall_misses::total 3759291 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59174415500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59174415500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31292251995 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31292251995 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 90466667495 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 90466667495 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 90466667495 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 90466667495 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 235986654 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 235986654 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 385118710 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 385118710 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 385118710 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 385118710 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011758 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011758 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006620 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006620 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009768 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009768 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009768 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009768 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21309.322063 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21309.322063 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31695.998229 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31695.998229 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24035.643287 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24035.643287 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24035.643287 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24035.643287 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10106 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 15 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1086 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.305709 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7.500000 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 385146856 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 385146856 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 385146856 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 385146856 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011750 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011750 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006613 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006613 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009761 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009761 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009761 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009761 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21340.216906 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21340.216906 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31724.176660 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31724.176660 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24064.821663 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24064.821663 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24064.821663 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24064.821663 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9788 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 9 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1047 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.348615 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 9 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2330787 # number of writebacks -system.cpu.dcache.writebacks::total 2330787 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1009448 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1009448 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19379 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 19379 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1028827 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1028827 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1028827 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1028827 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764895 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1764895 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 968010 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 968010 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2732905 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2732905 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2732905 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2732905 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33550858500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33550858500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 30073647496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 30073647496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63624505996 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 63624505996 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63624505996 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 63624505996 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007480 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007480 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006490 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006490 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007096 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.007096 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007096 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.007096 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19010.115899 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19010.115899 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31067.496716 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31067.496716 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23280.906580 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23280.906580 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23280.906580 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23280.906580 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2330532 # number of writebacks +system.cpu.dcache.writebacks::total 2330532 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1007920 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1007920 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19403 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 19403 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1027323 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1027323 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1027323 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1027323 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764986 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1764986 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 966982 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 966982 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2731968 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2731968 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2731968 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2731968 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33558631000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33558631000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 30070164497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 30070164497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63628795497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 63628795497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63628795497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 63628795497 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007479 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007479 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006483 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006483 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007093 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.007093 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007093 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.007093 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19013.539484 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19013.539484 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31096.922690 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31096.922690 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23290.461490 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23290.461490 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23290.461490 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23290.461490 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 6655 # number of replacements -system.cpu.icache.tags.tagsinuse 1037.678215 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 170577740 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8265 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 20638.565033 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 6653 # number of replacements +system.cpu.icache.tags.tagsinuse 1037.717066 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 170551460 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8264 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 20637.882381 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1037.678215 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.506679 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.506679 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1610 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 326 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1153 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.786133 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 341785100 # Number of tag accesses -system.cpu.icache.tags.data_accesses 341785100 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 170580521 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 170580521 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 170580521 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 170580521 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 170580521 # number of overall hits -system.cpu.icache.overall_hits::total 170580521 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 208882 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 208882 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 208882 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 208882 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 208882 # number of overall misses -system.cpu.icache.overall_misses::total 208882 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1312211500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1312211500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1312211500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1312211500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1312211500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1312211500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 170789403 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 170789403 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 170789403 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 170789403 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 170789403 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 170789403 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001223 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001223 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001223 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001223 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001223 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001223 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6282.070739 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6282.070739 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6282.070739 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6282.070739 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6282.070739 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6282.070739 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 889 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1037.717066 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.506698 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.506698 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1611 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 321 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1160 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.786621 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 341729418 # Number of tag accesses +system.cpu.icache.tags.data_accesses 341729418 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 170554639 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 170554639 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 170554639 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 170554639 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 170554639 # number of overall hits +system.cpu.icache.overall_hits::total 170554639 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 207451 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 207451 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 207451 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 207451 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 207451 # number of overall misses +system.cpu.icache.overall_misses::total 207451 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1211820000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1211820000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1211820000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1211820000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1211820000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1211820000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 170762090 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 170762090 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 170762090 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 170762090 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 170762090 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 170762090 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001215 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001215 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001215 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001215 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001215 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001215 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 5841.475818 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 5841.475818 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 5841.475818 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 5841.475818 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 5841.475818 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 5841.475818 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 674 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 74.083333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 74.888889 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2585 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2585 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2585 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2585 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2585 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2585 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 206297 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 206297 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 206297 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 206297 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 206297 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 206297 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 989635000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 989635000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 989635000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 989635000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 989635000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 989635000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001208 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001208 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001208 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001208 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001208 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001208 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4797.137137 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4797.137137 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4797.137137 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4797.137137 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4797.137137 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4797.137137 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 6653 # number of writebacks +system.cpu.icache.writebacks::total 6653 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2211 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2211 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2211 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2211 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2211 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2211 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 205240 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 205240 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 205240 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 205240 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 205240 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 205240 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 926829000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 926829000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 926829000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 926829000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 926829000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 926829000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001202 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001202 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001202 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4515.830248 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4515.830248 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4515.830248 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4515.830248 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4515.830248 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4515.830248 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 353544 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29619.458392 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3891749 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 385874 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.085543 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 189343942500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 20941.541383 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 242.518808 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8435.398201 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.639085 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007401 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.257428 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.903914 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32330 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13379 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18648 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.986633 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 43295860 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 43295860 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 2330787 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2330787 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1834 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1834 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 563915 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 563915 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4843 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 4843 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1588207 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1588207 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 4843 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2152122 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2156965 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 4843 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2152122 # number of overall hits -system.cpu.l2cache.overall_hits::total 2156965 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 196078 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 196078 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206573 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206573 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3410 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3410 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 176298 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 176298 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3410 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 382871 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 386281 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3410 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 382871 # number of overall misses -system.cpu.l2cache.overall_misses::total 386281 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 13890000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 13890000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16378927500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 16378927500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 280136500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 280136500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14178823000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 14178823000 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26951247500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990733 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990733 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268107 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268107 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.412941 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.412941 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099914 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099914 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.412941 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151034 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151884 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.412941 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151034 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151884 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22050.960694 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22050.960694 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69288.810735 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69288.810735 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72156.543427 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72156.543427 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70425.319629 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70425.319629 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72156.543427 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69812.131240 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69832.815141 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72156.543427 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69812.131240 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69832.815141 # average overall mshr miss latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990659 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990659 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268566 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268566 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.310755 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.310755 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100102 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100102 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.310755 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151304 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151820 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.310755 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151304 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151820 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22053.123649 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22053.123649 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69319.986565 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69319.986565 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72005.273438 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72005.273438 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70327.210711 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70327.210711 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72005.273438 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69783.830289 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69798.558254 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72005.273438 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69783.830289 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69798.558254 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5476754 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2732107 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 213805 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3607 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3607 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5474858 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2731062 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 212394 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3599 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3599 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 1970799 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2625625 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 253914 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 197912 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 197912 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 770488 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 770488 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 206297 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764505 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220789 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7985563 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8206352 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 528000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311409920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 311937920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 551588 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5830298 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.072755 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.259734 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 1969834 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2625695 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 6263 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 249937 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 196875 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 196875 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 770497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 770497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 205240 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764596 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 219739 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7984230 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8203969 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 927936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311400000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312327936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 552340 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3292546 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.124310 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.329935 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5406114 92.72% 92.72% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 424184 7.28% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2883249 87.57% 87.57% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 409297 12.43% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5830298 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5097760193 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3292546 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5102581952 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 309447487 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 307865483 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3901446077 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3901080066 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 179703 # Transaction distribution -system.membus.trans_dist::Writeback 294838 # Transaction distribution -system.membus.trans_dist::CleanEvict 57117 # Transaction distribution -system.membus.trans_dist::UpgradeReq 196128 # Transaction distribution -system.membus.trans_dist::UpgradeResp 196128 # Transaction distribution -system.membus.trans_dist::ReadExReq 206523 # Transaction distribution -system.membus.trans_dist::ReadExResp 206523 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 179705 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1516665 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1516665 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1516665 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43588096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43588096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43588096 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 179198 # Transaction distribution +system.membus.trans_dist::WritebackDirty 295163 # Transaction distribution +system.membus.trans_dist::CleanEvict 56643 # Transaction distribution +system.membus.trans_dist::UpgradeReq 195085 # Transaction distribution +system.membus.trans_dist::UpgradeResp 195085 # Transaction distribution +system.membus.trans_dist::ReadExReq 206880 # Transaction distribution +system.membus.trans_dist::ReadExResp 206880 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 179199 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1514133 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1514133 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1514133 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43599424 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43599424 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43599424 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 934311 # Request fanout histogram +system.membus.snoop_fanout::samples 932970 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 934311 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 932970 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 934311 # Request fanout histogram -system.membus.reqLayer0.occupancy 2245481708 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 932970 # Request fanout histogram +system.membus.reqLayer0.occupancy 2244779968 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2435298904 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2432276830 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 22535a108..1b9df2638 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.647861 # Number of seconds simulated -sim_ticks 1647861059500 # Number of ticks simulated -final_tick 1647861059500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.650527 # Number of seconds simulated +sim_ticks 1650526667500 # Number of ticks simulated +final_tick 1650526667500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 657040 # Simulator instruction rate (inst/s) -host_op_rate 1214941 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1309397988 # Simulator tick rate (ticks/s) -host_mem_usage 327616 # Number of bytes of host memory used -host_seconds 1258.49 # Real time elapsed on the host +host_inst_rate 726731 # Simulator instruction rate (inst/s) +host_op_rate 1343807 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1450624585 # Simulator tick rate (ticks/s) +host_mem_usage 327760 # Number of bytes of host memory used +host_seconds 1137.80 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988702 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 120384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24254848 # Number of bytes read from this memory -system.physmem.bytes_read::total 24375232 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 120384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 120384 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18763136 # Number of bytes written to this memory -system.physmem.bytes_written::total 18763136 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1881 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 378982 # Number of read requests responded to by this memory -system.physmem.num_reads::total 380863 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293174 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293174 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 73055 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14718989 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14792043 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 73055 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 73055 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11386358 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11386358 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11386358 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 73055 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14718989 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 26178401 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory +system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 115776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 115776 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18765248 # Number of bytes written to this memory +system.physmem.bytes_written::total 18765248 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1809 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 379046 # Number of read requests responded to by this memory +system.physmem.num_reads::total 380855 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293207 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293207 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 70145 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14697699 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14767844 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 70145 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 70145 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 11369249 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11369249 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11369249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 70145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 14697699 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 26137092 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 3295722119 # number of cpu cycles simulated +system.cpu.numCycles 3301053335 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 826877110 # Number of instructions committed @@ -60,7 +60,7 @@ system.cpu.num_mem_refs 533262343 # nu system.cpu.num_load_insts 384102157 # Number of load instructions system.cpu.num_store_insts 149160186 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 3295722118.998000 # Number of busy cycles +system.cpu.num_busy_cycles 3301053334.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 149758583 # Number of branches fetched @@ -100,14 +100,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1528988702 # Class of executed instruction system.cpu.dcache.tags.replacements 2514362 # number of replacements -system.cpu.dcache.tags.tagsinuse 4086.415711 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4086.386622 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 8211725500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415711 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 8246025500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4086.386622 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997653 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997653 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id @@ -133,14 +133,14 @@ system.cpu.dcache.demand_misses::cpu.data 2518458 # n system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses system.cpu.dcache.overall_misses::total 2518458 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29707934500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29707934500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18949311500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18949311500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 48657246000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 48657246000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 48657246000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 48657246000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 30918235500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 30918235500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20395021500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20395021500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 51313257000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 51313257000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 51313257000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 51313257000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) @@ -157,14 +157,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17197.923891 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17197.923891 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23954.813512 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23954.813512 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19320.253107 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19320.253107 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19320.253107 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19320.253107 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17898.567165 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17898.567165 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25782.410966 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 25782.410966 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20374.871052 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20374.871052 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20374.871052 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20374.871052 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -173,8 +173,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2323227 # number of writebacks -system.cpu.dcache.writebacks::total 2323227 # number of writebacks +system.cpu.dcache.writebacks::writebacks 2323200 # number of writebacks +system.cpu.dcache.writebacks::total 2323200 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses @@ -183,14 +183,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27980520500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27980520500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18158267500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 18158267500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46138788000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 46138788000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46138788000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 46138788000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29190821500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 29190821500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19603977500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19603977500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48794799000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 48794799000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48794799000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 48794799000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses @@ -199,24 +199,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16197.923891 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16197.923891 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22954.813512 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22954.813512 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18320.253107 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18320.253107 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18320.253107 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18320.253107 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16898.567165 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16898.567165 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24782.410966 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24782.410966 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19374.871052 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19374.871052 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19374.871052 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19374.871052 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1253 # number of replacements -system.cpu.icache.tags.tagsinuse 881.348726 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 881.361122 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1068344251 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 379653.251955 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 881.348726 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.430346 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.430346 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 881.361122 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.430352 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id @@ -238,12 +238,12 @@ system.cpu.icache.demand_misses::cpu.inst 2814 # n system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses system.cpu.icache.overall_misses::total 2814 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 115655000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 115655000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 115655000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 115655000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 115655000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 115655000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 125252000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 125252000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 125252000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 125252000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 125252000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 125252000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1068347065 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1068347065 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1068347065 # number of demand (read+write) accesses @@ -256,12 +256,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41099.857854 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41099.857854 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41099.857854 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41099.857854 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41099.857854 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41099.857854 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44510.305615 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 44510.305615 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 44510.305615 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 44510.305615 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 44510.305615 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 44510.305615 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -270,92 +270,98 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 1253 # number of writebacks +system.cpu.icache.writebacks::total 1253 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 112841000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 112841000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 112841000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 112841000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 112841000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 112841000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122438000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 122438000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122438000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 122438000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122438000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 122438000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40099.857854 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40099.857854 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40099.857854 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 40099.857854 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40099.857854 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 40099.857854 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43510.305615 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43510.305615 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43510.305615 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 43510.305615 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43510.305615 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 43510.305615 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 348182 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29285.938694 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3846845 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 380537 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.108991 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 755943397500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 20928.501607 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.116925 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8218.320163 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.638687 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004246 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.250803 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.893736 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32355 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.l2cache.tags.replacements 348438 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29288.473875 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3847001 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 380798 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.102472 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 756996028500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 20940.344841 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.252047 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8216.876987 # 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Number of tag accesses -system.cpu.l2cache.tags.data_accesses 41466677 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 2323227 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2323227 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 584717 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 584717 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 933 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 933 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1554759 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1554759 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 933 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2139476 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2140409 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 933 # 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number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 378982 # number of overall misses -system.cpu.l2cache.overall_misses::total 380863 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10832173000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10832173000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 98817000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 98817000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9064428500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 9064428500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 98817000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 19896601500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 19995418500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 98817000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 19896601500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 19995418500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 2323227 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2323227 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24060 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 41466938 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 41466938 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 2323200 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2323200 # 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n system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2518458 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260829 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.260829 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.668443 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.668443 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099950 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099950 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.668443 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.150482 # 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number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 379046 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 380855 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10214627500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10214627500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 89562500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 89562500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8548195500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8548195500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 89562500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18762823000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18852385500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 89562500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18762823000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18852385500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260829 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260829 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.668443 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.668443 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099950 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099950 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.668443 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150482 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151060 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.668443 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150482 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151060 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.026657 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.026657 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42534.290271 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42534.290271 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500.237468 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500.237468 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42534.290271 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.122697 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.291443 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42534.290271 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.122697 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.291443 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260865 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260865 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.642857 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099970 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099970 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150507 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151057 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150507 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151057 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.026653 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.026653 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49509.397457 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49509.397457 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234524 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234524 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49509.397457 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.121357 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.165417 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49509.397457 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.121357 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.165417 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 5036887 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2515615 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -462,8 +468,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2616401 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 247396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2616408 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 246392 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 791044 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 791044 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution @@ -471,53 +478,53 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 1727414 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7551278 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 7558159 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 180096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309867840 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 310047936 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 348182 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5385069 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000321 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.017916 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309866112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 310126400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 348438 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2869710 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000602 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.024538 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5383340 99.97% 99.97% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1729 0.03% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2867981 99.94% 99.94% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1729 0.06% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5385069 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4841670500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2869710 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4842896500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3777687000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 174536 # Transaction distribution -system.membus.trans_dist::Writeback 293174 # Transaction distribution -system.membus.trans_dist::CleanEvict 53553 # Transaction distribution -system.membus.trans_dist::ReadExReq 206327 # Transaction distribution -system.membus.trans_dist::ReadExResp 206327 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 174536 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108453 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108453 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1108453 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43138368 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43138368 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43138368 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 174499 # Transaction distribution +system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution +system.membus.trans_dist::CleanEvict 53507 # Transaction distribution +system.membus.trans_dist::ReadExReq 206356 # Transaction distribution +system.membus.trans_dist::ReadExResp 206356 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 174499 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1108424 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139968 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139968 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43139968 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 727623 # Request fanout histogram +system.membus.snoop_fanout::samples 727569 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 727623 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 727569 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 727623 # Request fanout histogram -system.membus.reqLayer0.occupancy 1900350576 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 727569 # Request fanout histogram +system.membus.reqLayer0.occupancy 1900428500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1904342076 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1904275000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |