diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2017-02-19 05:30:32 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2017-02-19 05:30:32 -0500 |
| commit | f2e2410a505ef48516f121ce1b2232ba7aa389af (patch) | |
| tree | dbe4c8482b37e854302410318fc474f507310724 /tests/long/se/20.parser | |
| parent | 184c6d7ebd7faa0869f294526a54a239a216b7c8 (diff) | |
| download | gem5-f2e2410a505ef48516f121ce1b2232ba7aa389af.tar.xz | |
stats: Get all stats updated to reflect current behaviour
Line everything up again.
Diffstat (limited to 'tests/long/se/20.parser')
| -rw-r--r-- | tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt | 1170 | ||||
| -rw-r--r-- | tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt | 1794 | ||||
| -rw-r--r-- | tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt | 1709 |
3 files changed, 2334 insertions, 2339 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 5f5ab2bca..4152fbfe4 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,106 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.368600 # Number of seconds simulated -sim_ticks 368600047500 # Number of ticks simulated -final_tick 368600047500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.368651 # Number of seconds simulated +sim_ticks 368651185500 # Number of ticks simulated +final_tick 368651185500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 377886 # Simulator instruction rate (inst/s) -host_op_rate 409300 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 274959159 # Simulator tick rate (ticks/s) -host_mem_usage 276756 # Number of bytes of host memory used -host_seconds 1340.56 # Real time elapsed on the host +host_inst_rate 378825 # Simulator instruction rate (inst/s) +host_op_rate 410318 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 275680946 # Simulator tick rate (ticks/s) +host_mem_usage 276920 # Number of bytes of host memory used +host_seconds 1337.24 # Real time elapsed on the host sim_insts 506579366 # Number of instructions simulated sim_ops 548692589 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 179840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9053376 # Number of bytes read from this memory -system.physmem.bytes_read::total 9233216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 179840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 179840 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6241792 # Number of bytes written to this memory -system.physmem.bytes_written::total 6241792 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2810 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141459 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144269 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97528 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97528 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 487900 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24561516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25049416 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 487900 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 487900 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 16933780 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 16933780 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 16933780 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 487900 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24561516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41983196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 144269 # Number of read requests accepted -system.physmem.writeReqs 97528 # Number of write requests accepted -system.physmem.readBursts 144269 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97528 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9225856 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue -system.physmem.bytesWritten 6240448 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9233216 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6241792 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 179712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9049216 # Number of bytes read from this memory +system.physmem.bytes_read::total 9228928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 179712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 179712 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6241472 # Number of bytes written to this memory +system.physmem.bytes_written::total 6241472 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2808 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141394 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144202 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97523 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97523 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 487485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24546825 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25034310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 487485 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 487485 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 16930563 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 16930563 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 16930563 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 487485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24546825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41964873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 144202 # Number of read requests accepted +system.physmem.writeReqs 97523 # Number of write requests accepted +system.physmem.readBursts 144202 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97523 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9222208 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue +system.physmem.bytesWritten 6240000 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9228928 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6241472 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9372 # Per bank write bursts -system.physmem.perBankRdBursts::1 8929 # Per bank write bursts -system.physmem.perBankRdBursts::2 8963 # Per bank write bursts -system.physmem.perBankRdBursts::3 8667 # Per bank write bursts -system.physmem.perBankRdBursts::4 9424 # Per bank write bursts -system.physmem.perBankRdBursts::5 9372 # Per bank write bursts -system.physmem.perBankRdBursts::6 8974 # Per bank write bursts -system.physmem.perBankRdBursts::7 8127 # Per bank write bursts -system.physmem.perBankRdBursts::8 8635 # Per bank write bursts -system.physmem.perBankRdBursts::9 8697 # Per bank write bursts -system.physmem.perBankRdBursts::10 8761 # Per bank write bursts -system.physmem.perBankRdBursts::11 9485 # Per bank write bursts -system.physmem.perBankRdBursts::12 9346 # Per bank write bursts -system.physmem.perBankRdBursts::13 9545 # Per bank write bursts -system.physmem.perBankRdBursts::14 8729 # Per bank write bursts -system.physmem.perBankRdBursts::15 9128 # Per bank write bursts -system.physmem.perBankWrBursts::0 6253 # Per bank write bursts -system.physmem.perBankWrBursts::1 6118 # Per bank write bursts -system.physmem.perBankWrBursts::2 6042 # Per bank write bursts -system.physmem.perBankWrBursts::3 5901 # Per bank write bursts -system.physmem.perBankWrBursts::4 6273 # Per bank write bursts -system.physmem.perBankWrBursts::5 6263 # Per bank write bursts -system.physmem.perBankWrBursts::6 6069 # Per bank write bursts +system.physmem.perBankRdBursts::0 9327 # Per bank write bursts +system.physmem.perBankRdBursts::1 8931 # Per bank write bursts +system.physmem.perBankRdBursts::2 8953 # Per bank write bursts +system.physmem.perBankRdBursts::3 8672 # Per bank write bursts +system.physmem.perBankRdBursts::4 9421 # Per bank write bursts +system.physmem.perBankRdBursts::5 9371 # Per bank write bursts +system.physmem.perBankRdBursts::6 8975 # Per bank write bursts +system.physmem.perBankRdBursts::7 8126 # Per bank write bursts +system.physmem.perBankRdBursts::8 8631 # Per bank write bursts +system.physmem.perBankRdBursts::9 8699 # Per bank write bursts +system.physmem.perBankRdBursts::10 8760 # Per bank write bursts +system.physmem.perBankRdBursts::11 9484 # Per bank write bursts +system.physmem.perBankRdBursts::12 9351 # Per bank write bursts +system.physmem.perBankRdBursts::13 9541 # Per bank write bursts +system.physmem.perBankRdBursts::14 8731 # Per bank write bursts +system.physmem.perBankRdBursts::15 9124 # Per bank write bursts +system.physmem.perBankWrBursts::0 6232 # Per bank write bursts +system.physmem.perBankWrBursts::1 6121 # Per bank write bursts +system.physmem.perBankWrBursts::2 6045 # Per bank write bursts +system.physmem.perBankWrBursts::3 5902 # Per bank write bursts +system.physmem.perBankWrBursts::4 6267 # Per bank write bursts +system.physmem.perBankWrBursts::5 6264 # Per bank write bursts +system.physmem.perBankWrBursts::6 6070 # Per bank write bursts system.physmem.perBankWrBursts::7 5535 # Per bank write bursts system.physmem.perBankWrBursts::8 5819 # Per bank write bursts -system.physmem.perBankWrBursts::9 5920 # Per bank write bursts +system.physmem.perBankWrBursts::9 5921 # Per bank write bursts system.physmem.perBankWrBursts::10 5985 # Per bank write bursts -system.physmem.perBankWrBursts::11 6510 # Per bank write bursts -system.physmem.perBankWrBursts::12 6360 # Per bank write bursts -system.physmem.perBankWrBursts::13 6344 # Per bank write bursts -system.physmem.perBankWrBursts::14 6013 # Per bank write bursts +system.physmem.perBankWrBursts::11 6509 # Per bank write bursts +system.physmem.perBankWrBursts::12 6365 # Per bank write bursts +system.physmem.perBankWrBursts::13 6345 # Per bank write bursts +system.physmem.perBankWrBursts::14 6018 # Per bank write bursts system.physmem.perBankWrBursts::15 6102 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 368600022000 # Total gap between requests +system.physmem.totGap 368651160000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 144269 # Read request sizes (log2) +system.physmem.readPktSize::6 144202 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97528 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143801 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97523 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143745 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -145,32 +145,32 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2868 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5746 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 5746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see @@ -194,116 +194,116 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63970 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 241.763327 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 162.115864 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.210402 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22774 35.60% 35.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18302 28.61% 64.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7461 11.66% 75.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8049 12.58% 88.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2117 3.31% 91.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1180 1.84% 93.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 776 1.21% 94.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 623 0.97% 95.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2688 4.20% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63970 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5740 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.113240 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 375.658190 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5737 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 64014 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 241.533165 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 161.867212 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 241.438904 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22835 35.67% 35.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18294 28.58% 64.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7516 11.74% 75.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7993 12.49% 88.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2085 3.26% 91.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1176 1.84% 93.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 786 1.23% 94.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 642 1.00% 95.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2687 4.20% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64014 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5742 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.094566 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 375.615355 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5739 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5740 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5740 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.987282 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.957535 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.009458 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2852 49.69% 49.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 159 2.77% 52.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 2701 47.06% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 19 0.33% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 6 0.10% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5740 # Writes before turning the bus around for reads -system.physmem.totQLat 3577410500 # Total ticks spent queuing -system.physmem.totMemAccLat 6280298000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 720770000 # Total ticks spent in databus transfers -system.physmem.avgQLat 24816.59 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5742 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5742 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.980146 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.950575 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.005103 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2875 50.07% 50.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 152 2.65% 52.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 2688 46.81% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 17 0.30% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 6 0.10% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5742 # Writes before turning the bus around for reads +system.physmem.totQLat 3587327500 # Total ticks spent queuing +system.physmem.totMemAccLat 6289146250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 720485000 # Total ticks spent in databus transfers +system.physmem.avgQLat 24895.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43566.59 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.03 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 43645.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.02 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 16.93 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.05 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.03 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 16.93 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.06 # Average write queue length when enqueuing -system.physmem.readRowHits 110541 # Number of row buffer hits during reads -system.physmem.writeRowHits 67141 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.68 # Row buffer hit rate for reads +system.physmem.avgWrQLen 19.95 # Average write queue length when enqueuing +system.physmem.readRowHits 110436 # Number of row buffer hits during reads +system.physmem.writeRowHits 67138 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.64 # Row buffer hit rate for reads system.physmem.writeRowHitRate 68.84 # Row buffer hit rate for writes -system.physmem.avgGap 1524419.34 # Average gap between requests -system.physmem.pageHitRate 73.52 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 229615260 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 122028225 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 512851920 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 252929880 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 7711888080.000002 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3985232520 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 353635200 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 24742392420 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 8329190880 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 68838786810 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 115080429525 # Total energy per rank (pJ) -system.physmem_0.averagePower 312.209478 # Core power per rank (mW) -system.physmem_0.totalIdleTime 358934929250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 533175250 # Time in different power states -system.physmem_0.memoryStateTime::REF 3272498000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 282985158000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 21690772000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 5858998750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 54259445500 # Time in different power states -system.physmem_1.actEnergy 227194800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 120737925 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 516407640 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 256056660 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 7588960080.000002 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3990680010 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 342748800 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 24389261460 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 8128903200 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 69135043560 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 114698287785 # Total energy per rank (pJ) -system.physmem_1.averagePower 311.172742 # Core power per rank (mW) -system.physmem_1.totalIdleTime 358951299500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 511434000 # Time in different power states -system.physmem_1.memoryStateTime::REF 3220288000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 284296687500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 21168817000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 5916972250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 53485848750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 132103819 # Number of BP lookups -system.cpu.branchPred.condPredicted 98193306 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5910048 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 68601561 # Number of BTB lookups -system.cpu.branchPred.BTBHits 60590477 # Number of BTB hits +system.physmem.avgGap 1525084.95 # Average gap between requests +system.physmem.pageHitRate 73.49 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 229772340 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 122107920 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 512480640 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 252835920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 7717419840.000002 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4012679730 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 354856800 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 24782953050 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8303052480 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 68829850950 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 115120015110 # Total energy per rank (pJ) +system.physmem_0.averagePower 312.273551 # Core power per rank (mW) +system.physmem_0.totalIdleTime 358922434750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 536706250 # Time in different power states +system.physmem_0.memoryStateTime::REF 3274898000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 282951785250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 21622731000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 5916696250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 54348368750 # Time in different power states +system.physmem_1.actEnergy 227351880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 120825210 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 516371940 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 256114080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 7627682400.000002 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3951722790 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 344311680 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 24510614460 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 8148381600 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 69110361900 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 114816583080 # Total energy per rank (pJ) +system.physmem_1.averagePower 311.450463 # Core power per rank (mW) +system.physmem_1.totalIdleTime 359082796500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 515499000 # Time in different power states +system.physmem_1.memoryStateTime::REF 3236866000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 284111116500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 21219892250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 5815970250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 53751841500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 132096754 # Number of BP lookups +system.cpu.branchPred.condPredicted 98183062 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5916233 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68556674 # Number of BTB lookups +system.cpu.branchPred.BTBHits 60606255 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.322301 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 10017121 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 18743 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3891575 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 3883028 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 8547 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 54138 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 88.403144 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 10020256 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 19127 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 3891736 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 3883139 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 8597 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 54132 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -333,7 +333,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -363,7 +363,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -393,7 +393,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -424,16 +424,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 368600047500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 737200095 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 368651185500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 737302371 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506579366 # Number of instructions committed system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed -system.cpu.discardedOps 12939783 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 12932918 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.455251 # CPI: cycles per instruction -system.cpu.ipc 0.687167 # IPC: instructions per cycle +system.cpu.cpi 1.455453 # CPI: cycles per instruction +system.cpu.ipc 0.687071 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 375609862 68.46% 68.46% # Class of committed instruction system.cpu.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction @@ -473,346 +473,346 @@ system.cpu.op_class_0::FloatMemWrite 16 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 548692589 # Class of committed instruction -system.cpu.tickCycles 694074449 # Number of cycles that the object actually ticked -system.cpu.idleCycles 43125646 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1141337 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.214598 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171083823 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1145433 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.361703 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5072633500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.214598 # Average occupied blocks per requestor +system.cpu.tickCycles 694166450 # Number of cycles that the object actually ticked +system.cpu.idleCycles 43135921 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1141334 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.216677 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171085721 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1145430 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.363751 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5072789500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.216677 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.993705 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993705 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 543 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 548 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3502 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346338043 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346338043 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 114566012 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114566012 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53537935 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53537935 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2794 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2794 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 346341652 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346341652 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 114567880 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114567880 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53537967 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53537967 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2792 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2792 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168103947 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168103947 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168106741 # number of overall hits -system.cpu.dcache.overall_hits::total 168106741 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 811353 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 811353 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 701114 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 701114 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 168105847 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168105847 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168108639 # number of overall hits +system.cpu.dcache.overall_hits::total 168108639 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 811293 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 811293 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 701082 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 701082 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 15 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 15 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1512467 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1512467 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1512482 # number of overall misses -system.cpu.dcache.overall_misses::total 1512482 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14511839000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14511839000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24015670000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24015670000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 38527509000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 38527509000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 38527509000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 38527509000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115377365 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115377365 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1512375 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1512375 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1512390 # number of overall misses +system.cpu.dcache.overall_misses::total 1512390 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14512864500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14512864500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24025186500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24025186500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 38538051000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 38538051000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 38538051000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 38538051000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115379173 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115379173 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2809 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2809 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2807 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2807 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169616414 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169616414 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169619223 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169619223 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 169618222 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169618222 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169621029 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169621029 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007032 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.007032 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012926 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.012926 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005340 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.005340 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008917 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008917 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008917 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008917 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17885.974416 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17885.974416 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34253.587862 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34253.587862 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25473.289004 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25473.289004 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25473.036373 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25473.036373 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005344 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.005344 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008916 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008916 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008916 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008916 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17888.561223 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17888.561223 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34268.725342 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34268.725342 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25481.809075 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25481.809075 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25481.556345 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25481.556345 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1068942 # number of writebacks -system.cpu.dcache.writebacks::total 1068942 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22320 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 22320 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344726 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344726 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 367046 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 367046 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 367046 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 367046 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 789033 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 789033 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356388 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356388 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 1068964 # number of writebacks +system.cpu.dcache.writebacks::total 1068964 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22242 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 22242 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344715 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 344715 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 366957 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 366957 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 366957 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 366957 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 789051 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 789051 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356367 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356367 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1145421 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1145421 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1145433 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1145433 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13416892000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 13416892000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12196191500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12196191500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 4297000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 4297000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25613083500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25613083500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25617380500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 25617380500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1145418 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1145418 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1145430 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1145430 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13418418500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 13418418500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12201205500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12201205500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 4179500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 4179500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25619624000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25619624000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25623803500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 25623803500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006839 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006839 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006571 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006571 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004272 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004272 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006570 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006570 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004275 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004275 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006753 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006753 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17004.221623 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17004.221623 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34221.667116 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34221.667116 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 358083.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 358083.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22361.283319 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22361.283319 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22364.800473 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22364.800473 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 18178 # number of replacements -system.cpu.icache.tags.tagsinuse 1186.508929 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 199149019 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 20050 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 9932.619401 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17005.768322 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17005.768322 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34237.753496 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34237.753496 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 348291.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 348291.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22367.052028 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22367.052028 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22370.466550 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22370.466550 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 18132 # number of replacements +system.cpu.icache.tags.tagsinuse 1186.493230 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 199187334 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 20004 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 9957.375225 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1186.508929 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.579350 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.579350 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1186.493230 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.579342 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.579342 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 311 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1400 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 318 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1398 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 398358188 # Number of tag accesses -system.cpu.icache.tags.data_accesses 398358188 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 199149019 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 199149019 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 199149019 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 199149019 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 199149019 # number of overall hits -system.cpu.icache.overall_hits::total 199149019 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 20050 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 20050 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 20050 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 20050 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 20050 # number of overall misses -system.cpu.icache.overall_misses::total 20050 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 544279500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 544279500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 544279500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 544279500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 544279500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 544279500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 199169069 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 199169069 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 199169069 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 199169069 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 199169069 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 199169069 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000101 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000101 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000101 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000101 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000101 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000101 # 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number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1165434 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283095 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.283095 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140422 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140422 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.051280 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.051280 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.140422 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.123453 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.123744 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140422 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 94706.676097 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 111111.071556 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94380.808588 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 94706.676097 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 97528 # number of writebacks -system.cpu.l2cache.writebacks::total 97528 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 97523 # number of writebacks +system.cpu.l2cache.writebacks::total 97523 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 13 # number of ReadSharedReq MSHR hits @@ -823,126 +823,126 @@ system.cpu.l2cache.demand_mshr_hits::total 14 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100978 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100978 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2810 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2810 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40481 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40481 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2810 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 141459 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 144269 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2810 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 141459 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 144269 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7969873500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7969873500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 284301000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 284301000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3953966500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3953966500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 284301000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11923840000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12208141000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 284301000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11923840000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12208141000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283139 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283139 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140150 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140150 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.051320 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.051320 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140150 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123785 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140150 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123785 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.830597 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.830597 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101174.733096 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101174.733096 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 97674.625133 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 97674.625133 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101174.733096 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84291.844280 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84620.680812 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101174.733096 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84291.844280 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84620.680812 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 2324998 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159585 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100957 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100957 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2808 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2808 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40437 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40437 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2808 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 141394 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 144202 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2808 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 141394 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 144202 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7975130500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7975130500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 283956000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 283956000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3955182000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3955182000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 283956000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11930312500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12214268500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 283956000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11930312500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12214268500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283095 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283095 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140372 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140372 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.051263 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.051263 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140372 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123442 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123732 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140372 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123442 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123732 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78995.319790 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78995.319790 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101123.931624 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101123.931624 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 97810.965205 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 97810.965205 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101123.931624 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84376.370284 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84702.490257 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101123.931624 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84376.370284 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84702.490257 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 2324900 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159536 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4992 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 2618 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2615 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 808845 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 1166470 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 18178 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 87628 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356638 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356638 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 20050 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 788795 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58278 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432203 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3490481 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2446592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141720000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 144166592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 112761 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6241792 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1278244 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.006015 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.077350 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 808815 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1166487 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 18132 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 87547 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356619 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356619 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 20004 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 788811 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58140 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432194 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3490334 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2440704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141721216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 144161920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 112700 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6241472 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1278134 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.006011 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.077328 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1270559 99.40% 99.40% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 7682 0.60% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1270454 99.40% 99.40% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 7677 0.60% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1278244 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2249619000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1278134 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2249546000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 30098453 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 30029453 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1718157983 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1718153483 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 254412 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 110315 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 254284 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 110251 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 43291 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97528 # Transaction distribution -system.membus.trans_dist::CleanEvict 12615 # Transaction distribution -system.membus.trans_dist::ReadExReq 100978 # Transaction distribution -system.membus.trans_dist::ReadExResp 100978 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 43291 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398681 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 398681 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15475008 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15475008 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 43245 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97523 # Transaction distribution +system.membus.trans_dist::CleanEvict 12559 # Transaction distribution +system.membus.trans_dist::ReadExReq 100957 # Transaction distribution +system.membus.trans_dist::ReadExResp 100957 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 43245 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398486 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 398486 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15470400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15470400 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 144269 # Request fanout histogram +system.membus.snoop_fanout::samples 144202 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 144269 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 144202 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 144269 # Request fanout histogram -system.membus.reqLayer0.occupancy 685127000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 144202 # Request fanout histogram +system.membus.reqLayer0.occupancy 684899000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 765884750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 765515250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 3dfc36814..d29a9ad2d 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.236024 # Number of seconds simulated -sim_ticks 236023688000 # Number of ticks simulated -final_tick 236023688000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.235850 # Number of seconds simulated +sim_ticks 235850129000 # Number of ticks simulated +final_tick 235850129000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 256452 # Simulator instruction rate (inst/s) -host_op_rate 277829 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 119803336 # Simulator tick rate (ticks/s) -host_mem_usage 301968 # Number of bytes of host memory used -host_seconds 1970.09 # Real time elapsed on the host +host_inst_rate 254127 # Simulator instruction rate (inst/s) +host_op_rate 275309 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 118629630 # Simulator tick rate (ticks/s) +host_mem_usage 302132 # Number of bytes of host memory used +host_seconds 1988.12 # Real time elapsed on the host sim_insts 505234934 # Number of instructions simulated sim_ops 547348155 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 640832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10509760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16394496 # Number of bytes read from this memory -system.physmem.bytes_read::total 27545088 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 640832 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 640832 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18630208 # Number of bytes written to this memory -system.physmem.bytes_written::total 18630208 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 10013 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 164215 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 256164 # Number of read requests responded to by this memory -system.physmem.num_reads::total 430392 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 291097 # Number of write requests responded to by this memory -system.physmem.num_writes::total 291097 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2715117 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 44528412 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 69461231 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 116704761 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2715117 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2715117 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 78933637 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 78933637 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 78933637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2715117 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 44528412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 69461231 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 195638397 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 430392 # Number of read requests accepted -system.physmem.writeReqs 291097 # Number of write requests accepted -system.physmem.readBursts 430392 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 291097 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 27379648 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 165440 # Total number of bytes read from write queue -system.physmem.bytesWritten 18628032 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 27545088 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18630208 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2585 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 651264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10497792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16410048 # Number of bytes read from this memory +system.physmem.bytes_read::total 27559104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 651264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 651264 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18653440 # Number of bytes written to this memory +system.physmem.bytes_written::total 18653440 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10176 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 164028 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 256407 # Number of read requests responded to by this memory +system.physmem.num_reads::total 430611 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 291460 # Number of write requests responded to by this memory +system.physmem.num_writes::total 291460 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2761347 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 44510436 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 69578287 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 116850070 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2761347 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2761347 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 79090226 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 79090226 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 79090226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2761347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 44510436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 69578287 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 195940296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 430611 # Number of read requests accepted +system.physmem.writeReqs 291460 # Number of write requests accepted +system.physmem.readBursts 430611 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 291460 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 27396288 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 162816 # Total number of bytes read from write queue +system.physmem.bytesWritten 18651392 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27559104 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18653440 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2544 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 9 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 27300 # Per bank write bursts -system.physmem.perBankRdBursts::1 26589 # Per bank write bursts -system.physmem.perBankRdBursts::2 25489 # Per bank write bursts -system.physmem.perBankRdBursts::3 32817 # Per bank write bursts -system.physmem.perBankRdBursts::4 28238 # Per bank write bursts -system.physmem.perBankRdBursts::5 30052 # Per bank write bursts -system.physmem.perBankRdBursts::6 25322 # Per bank write bursts -system.physmem.perBankRdBursts::7 24428 # Per bank write bursts -system.physmem.perBankRdBursts::8 25638 # Per bank write bursts -system.physmem.perBankRdBursts::9 25508 # Per bank write bursts -system.physmem.perBankRdBursts::10 25695 # Per bank write bursts -system.physmem.perBankRdBursts::11 26146 # Per bank write bursts -system.physmem.perBankRdBursts::12 27543 # Per bank write bursts -system.physmem.perBankRdBursts::13 26122 # Per bank write bursts -system.physmem.perBankRdBursts::14 24924 # Per bank write bursts -system.physmem.perBankRdBursts::15 25996 # Per bank write bursts -system.physmem.perBankWrBursts::0 18688 # Per bank write bursts -system.physmem.perBankWrBursts::1 18252 # Per bank write bursts -system.physmem.perBankWrBursts::2 17892 # Per bank write bursts -system.physmem.perBankWrBursts::3 17877 # Per bank write bursts -system.physmem.perBankWrBursts::4 18635 # Per bank write bursts -system.physmem.perBankWrBursts::5 18189 # Per bank write bursts -system.physmem.perBankWrBursts::6 17877 # Per bank write bursts -system.physmem.perBankWrBursts::7 17743 # Per bank write bursts -system.physmem.perBankWrBursts::8 17943 # Per bank write bursts -system.physmem.perBankWrBursts::9 17697 # Per bank write bursts -system.physmem.perBankWrBursts::10 18014 # Per bank write bursts -system.physmem.perBankWrBursts::11 18785 # Per bank write bursts -system.physmem.perBankWrBursts::12 18684 # Per bank write bursts -system.physmem.perBankWrBursts::13 18184 # Per bank write bursts -system.physmem.perBankWrBursts::14 18324 # Per bank write bursts -system.physmem.perBankWrBursts::15 18279 # Per bank write bursts +system.physmem.perBankRdBursts::0 27102 # Per bank write bursts +system.physmem.perBankRdBursts::1 26174 # Per bank write bursts +system.physmem.perBankRdBursts::2 25664 # Per bank write bursts +system.physmem.perBankRdBursts::3 33006 # Per bank write bursts +system.physmem.perBankRdBursts::4 27996 # Per bank write bursts +system.physmem.perBankRdBursts::5 29984 # Per bank write bursts +system.physmem.perBankRdBursts::6 25487 # Per bank write bursts +system.physmem.perBankRdBursts::7 24586 # Per bank write bursts +system.physmem.perBankRdBursts::8 25526 # Per bank write bursts +system.physmem.perBankRdBursts::9 25681 # Per bank write bursts +system.physmem.perBankRdBursts::10 25862 # Per bank write bursts +system.physmem.perBankRdBursts::11 26092 # Per bank write bursts +system.physmem.perBankRdBursts::12 27614 # Per bank write bursts +system.physmem.perBankRdBursts::13 26106 # Per bank write bursts +system.physmem.perBankRdBursts::14 25123 # Per bank write bursts +system.physmem.perBankRdBursts::15 26064 # Per bank write bursts +system.physmem.perBankWrBursts::0 18530 # Per bank write bursts +system.physmem.perBankWrBursts::1 18172 # Per bank write bursts +system.physmem.perBankWrBursts::2 17960 # Per bank write bursts +system.physmem.perBankWrBursts::3 17946 # Per bank write bursts +system.physmem.perBankWrBursts::4 18535 # Per bank write bursts +system.physmem.perBankWrBursts::5 18092 # Per bank write bursts +system.physmem.perBankWrBursts::6 17937 # Per bank write bursts +system.physmem.perBankWrBursts::7 17864 # Per bank write bursts +system.physmem.perBankWrBursts::8 17881 # Per bank write bursts +system.physmem.perBankWrBursts::9 17814 # Per bank write bursts +system.physmem.perBankWrBursts::10 18253 # Per bank write bursts +system.physmem.perBankWrBursts::11 18685 # Per bank write bursts +system.physmem.perBankWrBursts::12 18794 # Per bank write bursts +system.physmem.perBankWrBursts::13 18180 # Per bank write bursts +system.physmem.perBankWrBursts::14 18427 # Per bank write bursts +system.physmem.perBankWrBursts::15 18358 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 236023635500 # Total gap between requests +system.physmem.totGap 235850076500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 430392 # Read request sizes (log2) +system.physmem.readPktSize::6 430611 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 291097 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 318668 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 60537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13344 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8917 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6198 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3249 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 78 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 10 # What read queue length does an incoming req see +system.physmem.writePktSize::6 291460 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 318665 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 60579 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9026 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3288 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 74 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -149,37 +149,37 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 14859 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17602 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 18085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 18833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12035 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 14838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17893 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 18126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see @@ -198,127 +198,123 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 328591 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 140.009775 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 98.675291 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 178.430270 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 209431 63.74% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 79588 24.22% 87.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14900 4.53% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7308 2.22% 94.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4939 1.50% 96.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2586 0.79% 97.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1820 0.55% 97.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1543 0.47% 98.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6476 1.97% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 328591 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17028 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.118628 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 145.022717 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17026 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 329170 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 139.885214 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 98.537517 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 178.782393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 210239 63.87% 63.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 79533 24.16% 88.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14816 4.50% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7238 2.20% 94.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4909 1.49% 96.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2469 0.75% 96.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1818 0.55% 97.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1563 0.47% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6585 2.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 329170 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17054 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.096224 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 145.074041 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17052 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17028 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17028 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.093199 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.022957 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.821852 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 10045 58.99% 58.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 6192 36.36% 95.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 538 3.16% 98.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 158 0.93% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 50 0.29% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 18 0.11% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 8 0.05% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 3 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 4 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 3 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::70-71 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::90-91 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-93 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17028 # Writes before turning the bus around for reads -system.physmem.totQLat 14230918095 # Total ticks spent queuing -system.physmem.totMemAccLat 22252299345 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2139035000 # Total ticks spent in databus transfers -system.physmem.avgQLat 33264.81 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17054 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17054 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.088542 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.022727 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.689258 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 9980 58.52% 58.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 6296 36.92% 95.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 558 3.27% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 128 0.75% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 50 0.29% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 15 0.09% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 10 0.06% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 6 0.04% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 2 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 3 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::62-63 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::74-75 2 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17054 # Writes before turning the bus around for reads +system.physmem.totQLat 14249250266 # Total ticks spent queuing +system.physmem.totMemAccLat 22275506516 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2140335000 # Total ticks spent in databus transfers +system.physmem.avgQLat 33287.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 52014.81 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 116.00 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 78.92 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 116.70 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 78.93 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 52037.43 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 116.16 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 79.08 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 116.85 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 79.09 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.52 # Data bus utilization in percentage +system.physmem.busUtil 1.53 # Data bus utilization in percentage system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.62 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.76 # Average write queue length when enqueuing -system.physmem.readRowHits 308090 # Number of row buffer hits during reads -system.physmem.writeRowHits 82180 # Number of row buffer hits during writes -system.physmem.readRowHitRate 72.02 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 28.23 # Row buffer hit rate for writes -system.physmem.avgGap 327134.07 # Average gap between requests -system.physmem.pageHitRate 54.29 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1195143180 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 635214690 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1572477900 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 757698660 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15717574080.000004 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 13455213090 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 610838880 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 46153778370 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 17481507840 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 15586959435 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 113172096165 # Total energy per rank (pJ) -system.physmem_0.averagePower 479.494648 # Core power per rank (mW) -system.physmem_0.totalIdleTime 204913310074 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 902504711 # Time in different power states -system.physmem_0.memoryStateTime::REF 6666906000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 58174043250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 45524259021 # Time in different power states -system.physmem_0.memoryStateTime::ACT 23540851965 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 101215123053 # Time in different power states -system.physmem_1.actEnergy 1151060820 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 611788155 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1482064080 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 761650200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15007050240.000004 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13420176330 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 597461760 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 42655727700 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 16961144160 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 17790500985 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 110444200560 # Total energy per rank (pJ) -system.physmem_1.averagePower 467.936931 # Core power per rank (mW) -system.physmem_1.totalIdleTime 205025277615 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 898721445 # Time in different power states -system.physmem_1.memoryStateTime::REF 6366412000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 67312288506 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 44168958563 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23733276940 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 93544030546 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 174594111 # Number of BP lookups -system.cpu.branchPred.condPredicted 131059017 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7233933 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90232346 # Number of BTB lookups -system.cpu.branchPred.BTBHits 78999638 # Number of BTB hits +system.physmem.avgWrQLen 21.62 # Average write queue length when enqueuing +system.physmem.readRowHits 308139 # Number of row buffer hits during reads +system.physmem.writeRowHits 82177 # Number of row buffer hits during writes +system.physmem.readRowHitRate 71.98 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 28.20 # Row buffer hit rate for writes +system.physmem.avgGap 326630.04 # Average gap between requests +system.physmem.pageHitRate 54.25 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1195207440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 635245050 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1570792860 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 757087920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15735398640.000004 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 13510945980 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 615046560 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 46117601610 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 17430135360 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 15587831640 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 113161874670 # Total energy per rank (pJ) +system.physmem_0.averagePower 479.804155 # Core power per rank (mW) +system.physmem_0.totalIdleTime 204603400415 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 912794276 # Time in different power states +system.physmem_0.memoryStateTime::REF 6674692000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 58078463500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 45390268663 # Time in different power states +system.physmem_0.memoryStateTime::ACT 23659127059 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 101134783502 # Time in different power states +system.physmem_1.actEnergy 1155130620 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 613955100 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1485605520 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 764166240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15039011520.000004 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13474802850 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 604322400 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 42537889890 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 17081497440 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 17718944700 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 110481339780 # Total energy per rank (pJ) +system.physmem_1.averagePower 468.438739 # Core power per rank (mW) +system.physmem_1.totalIdleTime 204713337667 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 914400899 # Time in different power states +system.physmem_1.memoryStateTime::REF 6380142000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 66945121250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 44482448304 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23842248434 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 93285768113 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 174426540 # Number of BP lookups +system.cpu.branchPred.condPredicted 130958868 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7258964 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 89936054 # Number of BTB lookups +system.cpu.branchPred.BTBHits 78903188 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.551351 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12106114 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104453 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 4688512 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 4673325 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 15187 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 53879 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 87.732544 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12071651 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104612 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 4685817 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 4672093 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 13724 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 53795 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -348,7 +344,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -378,7 +374,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -408,7 +404,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -439,134 +435,134 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 472047377 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 235850129000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 471700259 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7665841 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 727531021 # Number of instructions fetch has processed -system.cpu.fetch.Branches 174594111 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 95779077 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 455980909 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14521279 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 6370 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 74 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 14846 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 235277273 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 36996 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 470928679 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.672614 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.189870 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7689412 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 726848478 # Number of instructions fetch has processed +system.cpu.fetch.Branches 174426540 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 95646932 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 455559849 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14571167 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 7088 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 169 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 15067 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 235109896 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 36736 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 470557168 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.672087 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.189865 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 101212688 21.49% 21.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132055507 28.04% 49.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57355152 12.18% 61.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 180305332 38.29% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 101222144 21.51% 21.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 131885544 28.03% 49.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57421464 12.20% 61.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 180028016 38.26% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 470928679 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.369866 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.541225 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32549304 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 125870927 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 282926168 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22809881 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6772399 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 23857268 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 495900 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 710989368 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29087460 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6772399 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63357486 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 61253040 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40466365 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 273530421 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 25548968 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 682720764 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 12849971 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 10025216 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2519363 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1823930 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 2318589 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 827514324 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3000521547 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 718647704 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 470557168 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.369783 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.540912 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32637512 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 125886415 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 282414401 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22855437 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6763403 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 71909343 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 530427 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 710086582 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29127059 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6763403 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63488458 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 61155779 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40463668 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 273022741 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 25663119 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 681926435 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 12775010 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 10060236 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2531231 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1813266 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 2373970 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 826391408 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2997146717 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 717894841 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654095674 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 173418650 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1545803 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1536177 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 43812625 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 142363196 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67528532 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12884136 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11268568 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 664776091 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2979332 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608934070 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5749195 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 120407268 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 306545068 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1700 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 470928679 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.293049 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.104484 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 172295734 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1545774 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1536126 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 43961162 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 142203026 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67513624 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12913434 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11193544 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 664083030 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2979301 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608560988 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5743597 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 119714176 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 304959820 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1669 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 470557168 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.293277 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.104886 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 154505965 32.81% 32.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 100895056 21.42% 54.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 145511490 30.90% 85.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63049261 13.39% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6966284 1.48% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 623 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 154355830 32.80% 32.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 100909501 21.44% 54.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 145256303 30.87% 85.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63003898 13.39% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 7030993 1.49% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 643 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 470928679 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 470557168 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71893204 53.11% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 30 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44308845 32.73% 85.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19163928 14.16% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 14 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71776446 52.99% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44249945 32.67% 85.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19436717 14.35% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 9 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 22 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 412595854 67.76% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 352107 0.06% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 412327933 67.75% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 351836 0.06% 67.81% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.81% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.81% # Type of FU issued @@ -596,84 +592,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.81% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.81% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 133581364 21.94% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62404700 10.25% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 26 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 133457436 21.93% 89.74% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62423748 10.26% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 16 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 16 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608934070 # Type of FU issued -system.cpu.iq.rate 1.289985 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135366043 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.222300 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1829911935 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 788191546 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594211471 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 122 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 100 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 608560988 # Type of FU issued +system.cpu.iq.rate 1.290143 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135463169 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.222596 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1828885813 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 786805257 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 593918713 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 97 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 70 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 744300035 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 78 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7286788 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 744024094 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 63 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 7272380 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 26479913 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 24891 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29414 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10668312 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 26319743 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24134 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29234 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10653404 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 225406 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 23080 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 224604 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 23301 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6772399 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 23806628 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 967662 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 669248404 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6763403 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 23756716 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 981361 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 668554311 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 142363196 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67528532 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1490790 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 256473 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 573815 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29414 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3591193 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3742987 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7334180 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 598436406 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129089013 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10497664 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 142203026 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67513624 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1490759 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 256987 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 586437 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29234 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3560929 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3767464 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7328393 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 598121332 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 128978812 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10439656 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1492981 # number of nop insts executed -system.cpu.iew.exec_refs 190011710 # number of memory reference insts executed -system.cpu.iew.exec_branches 131264327 # Number of branches executed -system.cpu.iew.exec_stores 60922697 # Number of stores executed -system.cpu.iew.exec_rate 1.267746 # Inst execution rate -system.cpu.iew.wb_sent 595457934 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594211487 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349573647 # num instructions producing a value -system.cpu.iew.wb_consumers 571370339 # num instructions consuming a value -system.cpu.iew.wb_rate 1.258796 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611816 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 107140247 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1491980 # number of nop insts executed +system.cpu.iew.exec_refs 189925083 # number of memory reference insts executed +system.cpu.iew.exec_branches 131214447 # Number of branches executed +system.cpu.iew.exec_stores 60946271 # Number of stores executed +system.cpu.iew.exec_rate 1.268011 # Inst execution rate +system.cpu.iew.wb_sent 595160432 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 593918729 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349300209 # num instructions producing a value +system.cpu.iew.wb_consumers 571006140 # num instructions consuming a value +system.cpu.iew.wb_rate 1.259102 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611728 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 106531473 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6745693 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 454265599 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.207866 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.884244 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6736784 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 453954004 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.208695 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.885174 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 225450125 49.63% 49.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116407668 25.63% 75.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43488632 9.57% 84.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23202465 5.11% 89.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11495162 2.53% 92.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7755603 1.71% 94.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8270201 1.82% 95.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4246101 0.93% 96.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13949642 3.07% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 225266208 49.62% 49.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116316093 25.62% 75.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43463338 9.57% 84.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23021553 5.07% 89.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11663985 2.57% 92.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7751412 1.71% 94.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8276330 1.82% 95.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4247049 0.94% 96.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13948036 3.07% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 454265599 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 453954004 # Number of insts commited each cycle system.cpu.commit.committedInsts 506578818 # Number of instructions committed system.cpu.commit.committedOps 548692039 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -723,560 +719,558 @@ system.cpu.commit.op_class_0::FloatMemWrite 16 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548692039 # Class of committed instruction -system.cpu.commit.bw_lim_events 13949642 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1096141105 # The number of ROB reads -system.cpu.rob.rob_writes 1328357052 # The number of ROB writes -system.cpu.timesIdled 14656 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1118698 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 13948036 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1095222342 # The number of ROB reads +system.cpu.rob.rob_writes 1327086117 # The number of ROB writes +system.cpu.timesIdled 14782 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1143091 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505234934 # Number of Instructions Simulated system.cpu.committedOps 547348155 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.934313 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.934313 # CPI: Total CPI of All Threads -system.cpu.ipc 1.070306 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.070306 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 610147261 # number of integer regfile reads -system.cpu.int_regfile_writes 327343686 # number of integer regfile writes +system.cpu.cpi 0.933626 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.933626 # CPI: Total CPI of All Threads +system.cpu.ipc 1.071093 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.071093 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 609897818 # number of integer regfile reads +system.cpu.int_regfile_writes 327085541 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2166295309 # number of cc regfile reads -system.cpu.cc_regfile_writes 376541599 # number of cc regfile writes -system.cpu.misc_regfile_reads 217608578 # number of misc regfile reads +system.cpu.cc_regfile_reads 2165040622 # number of cc regfile reads +system.cpu.cc_regfile_writes 376344417 # number of cc regfile writes +system.cpu.misc_regfile_reads 217537377 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2817163 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.628180 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168869146 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2817675 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 59.932088 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 504794000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.628180 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999274 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999274 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2817480 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.627959 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168773991 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2817992 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 59.891579 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 504701000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.627959 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999273 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999273 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 355269881 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 355269881 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 114167630 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114167630 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51721570 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51721570 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2787 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2787 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488559 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488559 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 355076080 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 355076080 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 114071383 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114071383 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51722665 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51722665 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2778 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2778 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488556 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488556 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 165889200 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 165889200 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 165891987 # number of overall hits -system.cpu.dcache.overall_hits::total 165891987 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4839460 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4839460 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2517479 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2517479 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7356939 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7356939 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7356950 # number of overall misses -system.cpu.dcache.overall_misses::total 7356950 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 63959252000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 63959252000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19900951428 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19900951428 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1024000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1024000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83860203428 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83860203428 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83860203428 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83860203428 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 119007090 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 119007090 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 165794048 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 165794048 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 165796826 # number of overall hits +system.cpu.dcache.overall_hits::total 165796826 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4838662 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4838662 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2516384 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2516384 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 10 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 10 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 65 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 65 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 7355046 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7355046 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7355056 # number of overall misses +system.cpu.dcache.overall_misses::total 7355056 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 63735397500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 63735397500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19938555937 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19938555937 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 846000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 846000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83673953437 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83673953437 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83673953437 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83673953437 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 118910045 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 118910045 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2798 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2798 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488625 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488625 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2788 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2788 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488621 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488621 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173246139 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173246139 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173248937 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173248937 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040665 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040665 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046415 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046415 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003931 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.003931 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 173149094 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173149094 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173151882 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173151882 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040692 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040692 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046394 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046394 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003587 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.003587 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.042465 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.042465 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.042465 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.042465 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13216.196022 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13216.196022 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7905.111196 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7905.111196 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15515.151515 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15515.151515 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11398.790098 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 11398.790098 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11398.773055 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 11398.773055 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1096029 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.042478 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.042478 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042477 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042477 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13172.111939 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13172.111939 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7923.494958 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7923.494958 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13015.384615 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13015.384615 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11376.401104 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11376.401104 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11376.385637 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11376.385637 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 14 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1100252 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 221098 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 4.957209 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2817163 # number of writebacks -system.cpu.dcache.writebacks::total 2817163 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2541567 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2541567 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1997678 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1997678 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4539245 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4539245 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4539245 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4539245 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2297893 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2297893 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519801 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519801 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2817694 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2817694 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2817704 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2817704 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32776399000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32776399000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4786328496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4786328496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1261500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1261500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37562727496 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 37562727496 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37563988996 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 37563988996 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019309 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019309 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009584 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009584 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003574 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003574 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016264 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.016264 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14263.675028 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14263.675028 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9208.001708 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9208.001708 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 126150 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 126150 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13331.017313 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13331.017313 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13331.417706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13331.417706 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 76621 # number of replacements -system.cpu.icache.tags.tagsinuse 466.068009 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 235191085 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 77133 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3049.162939 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 116620130500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 466.068009 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.910289 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.910289 # Average percentage of cache occupancy +system.cpu.dcache.blocked::no_targets 221126 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4.975679 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2817480 # number of writebacks +system.cpu.dcache.writebacks::total 2817480 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2540507 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2540507 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1996523 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1996523 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 65 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 65 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 4537030 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4537030 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4537030 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4537030 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2298155 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2298155 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519861 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 519861 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 9 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 9 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2818016 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2818016 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2818025 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2818025 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32727255000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32727255000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4791332496 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4791332496 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1174000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1174000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37518587496 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 37518587496 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37519761496 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 37519761496 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019327 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019327 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009585 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009585 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003228 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003228 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016275 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016275 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016275 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.016275 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14240.664794 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14240.664794 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9216.564612 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9216.564612 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 130444.444444 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 130444.444444 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13313.830545 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13313.830545 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13314.204628 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13314.204628 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 76537 # number of replacements +system.cpu.icache.tags.tagsinuse 465.899675 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 235023805 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 77049 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3050.316098 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 116553680500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 465.899675 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.909960 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.909960 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 118 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 263 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 14 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 470631453 # Number of tag accesses -system.cpu.icache.tags.data_accesses 470631453 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 235191085 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 235191085 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 235191085 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 235191085 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 235191085 # number of overall hits -system.cpu.icache.overall_hits::total 235191085 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 86061 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 86061 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 86061 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 86061 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 86061 # number of overall misses -system.cpu.icache.overall_misses::total 86061 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1945774184 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1945774184 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1945774184 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1945774184 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1945774184 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1945774184 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 235277146 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 235277146 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 235277146 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 235277146 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 235277146 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 235277146 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 470296624 # Number of tag accesses +system.cpu.icache.tags.data_accesses 470296624 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 235023805 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 235023805 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 235023805 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 235023805 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 235023805 # number of overall hits +system.cpu.icache.overall_hits::total 235023805 # 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average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22737.250305 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22737.250305 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22737.250305 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22737.250305 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22737.250305 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 201943 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 336 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 7203 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.293703 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 191.375000 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 76621 # number of writebacks -system.cpu.icache.writebacks::total 76621 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8898 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 8898 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 8898 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 8898 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 8898 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 8898 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77163 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 77163 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 77163 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 77163 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 77163 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 77163 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1533201777 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1533201777 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1533201777 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1533201777 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1533201777 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1533201777 # number of overall MSHR miss cycles +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.035957 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 42 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 76537 # number of writebacks +system.cpu.icache.writebacks::total 76537 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8885 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 8885 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 8885 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 8885 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 8885 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 8885 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77082 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 77082 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 77082 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 77082 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 77082 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 77082 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1551815800 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1551815800 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1551815800 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1551815800 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1551815800 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1551815800 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000328 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000328 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000328 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19869.649664 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19869.649664 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19869.649664 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19869.649664 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19869.649664 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19869.649664 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 8513489 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 8514918 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 429 # number of redundant prefetches already in prefetch queue +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20132.012662 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20132.012662 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20132.012662 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20132.012662 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20132.012662 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20132.012662 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 8513754 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 8515198 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 454 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 744218 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 389920 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15006.987953 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2697445 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 405523 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.651768 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 744250 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 390446 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15006.522104 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2698185 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 406039 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.645138 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14934.817227 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 72.170726 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.911549 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004405 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.915954 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 103 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15500 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 15 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 49 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 35 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 249 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 665 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5454 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6553 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2579 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.006287 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946045 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 95362177 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 95362177 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2356317 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2356317 # 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number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 6142 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 356126 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 356126 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 33 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3684 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3684 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10176 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10176 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 160345 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 160345 # 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number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 462922500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 462922500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 973097500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 973097500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 13944331500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 13944331500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 973097500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14407254000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15380351500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 973097500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14407254000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 21400232213 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 36780583713 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007060 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007060 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.129820 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.129820 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069927 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069927 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.129820 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058280 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060186 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.129820 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058280 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007057 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007057 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.132077 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.132077 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069837 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069837 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.132077 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058208 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060174 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.132077 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058208 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.183107 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59945.212612 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 59945.212612 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15568.965517 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15568.965517 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 127356.309362 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 127356.309362 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 95312.144213 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 95312.144213 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87186.572603 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87186.572603 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 95312.144213 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88087.985263 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88503.162523 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 95312.144213 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88087.985263 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59945.212612 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69332.064095 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5788651 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893810 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 26608 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 99788 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99240 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 548 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 2372852 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2647414 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 537467 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 98823 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 402669 # Transaction distribution +system.cpu.l2cache.overall_mshr_miss_rate::total 0.183186 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60091.743408 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 60091.743408 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15666.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15666.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 125657.573290 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 125657.573290 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 95626.719733 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 95626.719733 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 86964.554554 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 86964.554554 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 95626.719733 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87833.578209 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88288.806291 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 95626.719733 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87833.578209 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60091.743408 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69354.014216 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5789124 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2894045 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 26043 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 99823 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99226 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 597 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 2373057 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2641890 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 543587 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 98986 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 403295 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 29 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 29 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 521984 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 521984 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 77163 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295691 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230912 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8452572 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8683484 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9839936 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360629696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 370469632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 792623 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 18632384 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 3687456 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.034433 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.183151 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeReq 33 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 33 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 522015 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 522015 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 77082 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295977 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230663 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8453531 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8684194 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9829184 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360670272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 370499456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 793778 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 18655808 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 3688848 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.034290 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.182859 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3561035 96.57% 96.57% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 125873 3.41% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 548 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3562956 96.59% 96.59% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 125295 3.40% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 597 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3687456 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5788109505 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3688848 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5788579005 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 115773436 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 115655928 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4226542968 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4227026456 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 820344 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 413808 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 821093 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 414041 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 426709 # Transaction distribution -system.membus.trans_dist::WritebackDirty 291097 # Transaction distribution -system.membus.trans_dist::CleanEvict 98823 # Transaction distribution -system.membus.trans_dist::UpgradeReq 32 # Transaction distribution -system.membus.trans_dist::ReadExReq 3682 # Transaction distribution -system.membus.trans_dist::ReadExResp 3682 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 426710 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1250735 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1250735 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46175232 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 46175232 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 426929 # Transaction distribution +system.membus.trans_dist::WritebackDirty 291460 # Transaction distribution +system.membus.trans_dist::CleanEvict 98986 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36 # Transaction distribution +system.membus.trans_dist::ReadExReq 3681 # Transaction distribution +system.membus.trans_dist::ReadExResp 3681 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 426930 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1251703 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1251703 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46212480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 46212480 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 430424 # Request fanout histogram +system.membus.snoop_fanout::samples 430647 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 430424 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 430647 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 430424 # Request fanout histogram -system.membus.reqLayer0.occupancy 2210945378 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 430647 # Request fanout histogram +system.membus.reqLayer0.occupancy 2213026745 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2277916539 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2279181090 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 1d6cdc3c5..eaf30dab2 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.487172 # Number of seconds simulated -sim_ticks 487172057000 # Number of ticks simulated -final_tick 487172057000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.487051 # Number of seconds simulated +sim_ticks 487050729500 # Number of ticks simulated +final_tick 487050729500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 151495 # Simulator instruction rate (inst/s) -host_op_rate 280342 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 89259825 # Simulator tick rate (ticks/s) -host_mem_usage 322228 # Number of bytes of host memory used -host_seconds 5457.91 # Real time elapsed on the host +host_inst_rate 151835 # Simulator instruction rate (inst/s) +host_op_rate 280970 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 89437473 # Simulator tick rate (ticks/s) +host_mem_usage 318556 # Number of bytes of host memory used +host_seconds 5445.71 # Real time elapsed on the host sim_insts 826847303 # Number of instructions simulated sim_ops 1530082520 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 155008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24650432 # Number of bytes read from this memory -system.physmem.bytes_read::total 24805440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 155008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 155008 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18909504 # Number of bytes written to this memory -system.physmem.bytes_written::total 18909504 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2422 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 385163 # Number of read requests responded to by this memory -system.physmem.num_reads::total 387585 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 295461 # Number of write requests responded to by this memory -system.physmem.num_writes::total 295461 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 318179 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 50599027 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50917206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 318179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 318179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 38814837 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 38814837 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 38814837 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 318179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 50599027 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 89732043 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 387585 # Number of read requests accepted -system.physmem.writeReqs 295461 # Number of write requests accepted -system.physmem.readBursts 387585 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 295461 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24785280 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20160 # Total number of bytes read from write queue -system.physmem.bytesWritten 18907584 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24805440 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18909504 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 315 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 156352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24658560 # Number of bytes read from this memory +system.physmem.bytes_read::total 24814912 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 156352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 156352 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18911424 # Number of bytes written to this memory +system.physmem.bytes_written::total 18911424 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2443 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 385290 # Number of read requests responded to by this memory +system.physmem.num_reads::total 387733 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 295491 # Number of write requests responded to by this memory +system.physmem.num_writes::total 295491 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 321018 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 50628320 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50949338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 321018 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 321018 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 38828448 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 38828448 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 38828448 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 321018 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 50628320 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 89777786 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 387733 # Number of read requests accepted +system.physmem.writeReqs 295491 # Number of write requests accepted +system.physmem.readBursts 387733 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 295491 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24795072 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19840 # Total number of bytes read from write queue +system.physmem.bytesWritten 18909504 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24814912 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18911424 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 310 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24645 # Per bank write bursts -system.physmem.perBankRdBursts::1 26417 # Per bank write bursts -system.physmem.perBankRdBursts::2 24674 # Per bank write bursts -system.physmem.perBankRdBursts::3 24501 # Per bank write bursts -system.physmem.perBankRdBursts::4 23296 # Per bank write bursts -system.physmem.perBankRdBursts::5 23619 # Per bank write bursts -system.physmem.perBankRdBursts::6 24746 # Per bank write bursts -system.physmem.perBankRdBursts::7 24503 # Per bank write bursts -system.physmem.perBankRdBursts::8 23866 # Per bank write bursts -system.physmem.perBankRdBursts::9 23595 # Per bank write bursts -system.physmem.perBankRdBursts::10 24803 # Per bank write bursts -system.physmem.perBankRdBursts::11 23982 # Per bank write bursts -system.physmem.perBankRdBursts::12 23298 # Per bank write bursts -system.physmem.perBankRdBursts::13 23005 # Per bank write bursts -system.physmem.perBankRdBursts::14 24008 # Per bank write bursts -system.physmem.perBankRdBursts::15 24312 # Per bank write bursts -system.physmem.perBankWrBursts::0 19007 # Per bank write bursts -system.physmem.perBankWrBursts::1 19956 # Per bank write bursts -system.physmem.perBankWrBursts::2 19034 # Per bank write bursts -system.physmem.perBankWrBursts::3 18984 # Per bank write bursts -system.physmem.perBankWrBursts::4 18157 # Per bank write bursts -system.physmem.perBankWrBursts::5 18431 # Per bank write bursts -system.physmem.perBankWrBursts::6 19162 # Per bank write bursts -system.physmem.perBankWrBursts::7 19114 # Per bank write bursts -system.physmem.perBankWrBursts::8 18737 # Per bank write bursts -system.physmem.perBankWrBursts::9 17973 # Per bank write bursts -system.physmem.perBankWrBursts::10 18902 # Per bank write bursts -system.physmem.perBankWrBursts::11 17777 # Per bank write bursts -system.physmem.perBankWrBursts::12 17406 # Per bank write bursts -system.physmem.perBankWrBursts::13 16997 # Per bank write bursts -system.physmem.perBankWrBursts::14 17829 # Per bank write bursts +system.physmem.perBankRdBursts::0 24612 # Per bank write bursts +system.physmem.perBankRdBursts::1 26389 # Per bank write bursts +system.physmem.perBankRdBursts::2 24828 # Per bank write bursts +system.physmem.perBankRdBursts::3 24571 # Per bank write bursts +system.physmem.perBankRdBursts::4 23534 # Per bank write bursts +system.physmem.perBankRdBursts::5 23661 # Per bank write bursts +system.physmem.perBankRdBursts::6 24754 # Per bank write bursts +system.physmem.perBankRdBursts::7 24509 # Per bank write bursts +system.physmem.perBankRdBursts::8 23888 # Per bank write bursts +system.physmem.perBankRdBursts::9 23557 # Per bank write bursts +system.physmem.perBankRdBursts::10 24834 # Per bank write bursts +system.physmem.perBankRdBursts::11 24002 # Per bank write bursts +system.physmem.perBankRdBursts::12 23243 # Per bank write bursts +system.physmem.perBankRdBursts::13 22894 # Per bank write bursts +system.physmem.perBankRdBursts::14 23905 # Per bank write bursts +system.physmem.perBankRdBursts::15 24242 # Per bank write bursts +system.physmem.perBankWrBursts::0 18972 # Per bank write bursts +system.physmem.perBankWrBursts::1 19954 # Per bank write bursts +system.physmem.perBankWrBursts::2 19038 # Per bank write bursts +system.physmem.perBankWrBursts::3 19006 # Per bank write bursts +system.physmem.perBankWrBursts::4 18208 # Per bank write bursts +system.physmem.perBankWrBursts::5 18444 # Per bank write bursts +system.physmem.perBankWrBursts::6 19174 # Per bank write bursts +system.physmem.perBankWrBursts::7 19116 # Per bank write bursts +system.physmem.perBankWrBursts::8 18744 # Per bank write bursts +system.physmem.perBankWrBursts::9 17955 # Per bank write bursts +system.physmem.perBankWrBursts::10 18923 # Per bank write bursts +system.physmem.perBankWrBursts::11 17774 # Per bank write bursts +system.physmem.perBankWrBursts::12 17399 # Per bank write bursts +system.physmem.perBankWrBursts::13 16985 # Per bank write bursts +system.physmem.perBankWrBursts::14 17804 # Per bank write bursts system.physmem.perBankWrBursts::15 17965 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 487171969500 # Total gap between requests +system.physmem.totGap 487050613500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 387585 # Read request sizes (log2) +system.physmem.readPktSize::6 387733 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 295461 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 5721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 295491 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381263 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 5754 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 361 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -145,27 +145,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6088 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17686 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 17693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -194,360 +194,362 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 146660 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 297.911141 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 176.290070 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.324639 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 53183 36.26% 36.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40977 27.94% 64.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13739 9.37% 73.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7432 5.07% 78.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5223 3.56% 82.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3827 2.61% 84.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2941 2.01% 86.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2699 1.84% 88.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16639 11.35% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 146660 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17684 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.898835 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 18.149529 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 215.763207 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17677 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 3 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 146416 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 298.484100 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 176.719176 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.748192 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 52816 36.07% 36.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 41066 28.05% 64.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13865 9.47% 73.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7498 5.12% 78.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4985 3.40% 82.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3806 2.60% 84.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2894 1.98% 86.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2818 1.92% 88.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16668 11.38% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 146416 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17678 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.914866 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 18.161180 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 216.039339 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17672 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17684 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17684 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.706119 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.679236 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.959383 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 11362 64.25% 64.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 284 1.61% 65.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5921 33.48% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 108 0.61% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 8 0.05% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17684 # Writes before turning the bus around for reads -system.physmem.totQLat 9753002000 # Total ticks spent queuing -system.physmem.totMemAccLat 17014314500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1936350000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25183.99 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17678 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17678 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.713486 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.686282 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.965426 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 11315 64.01% 64.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 269 1.52% 65.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5957 33.70% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 123 0.70% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 10 0.06% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 3 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17678 # Writes before turning the bus around for reads +system.physmem.totQLat 9794922250 # Total ticks spent queuing +system.physmem.totMemAccLat 17059103500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1937115000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25282.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43933.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 50.88 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 38.81 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.92 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 38.81 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44032.24 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 50.91 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 38.82 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.95 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 38.83 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.70 # Data bus utilization in percentage system.physmem.busUtilRead 0.40 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.30 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.76 # Average write queue length when enqueuing -system.physmem.readRowHits 316112 # Number of row buffer hits during reads -system.physmem.writeRowHits 219918 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.43 # Row buffer hit rate for writes -system.physmem.avgGap 713234.50 # Average gap between requests -system.physmem.pageHitRate 78.51 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 536813760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 285300510 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1402303140 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 792630900 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 13522080000.000004 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 8880806910 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 733930560 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 36188602890 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 17013808320 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 84109110615 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 163471886265 # Total energy per rank (pJ) -system.physmem_0.averagePower 335.552673 # Core power per rank (mW) -system.physmem_0.totalIdleTime 465770843500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 1167963000 # Time in different power states -system.physmem_0.memoryStateTime::REF 5742590000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 342103131000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 44306910500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 14490068000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 79361394500 # Time in different power states -system.physmem_1.actEnergy 510417180 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 271274190 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1362804660 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 749518920 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 13134242160.000004 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 8898960840 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 723582720 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 34400258100 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 16618152960 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 85296284295 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 161971426545 # Total energy per rank (pJ) -system.physmem_1.averagePower 332.472734 # Core power per rank (mW) -system.physmem_1.totalIdleTime 465759347500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 1160536750 # Time in different power states -system.physmem_1.memoryStateTime::REF 5578620000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 347043695250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 43276363250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14673424500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 75439417250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 297986094 # Number of BP lookups -system.cpu.branchPred.condPredicted 297986094 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 23626998 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 229902551 # Number of BTB lookups +system.physmem.avgWrQLen 20.96 # Average write queue length when enqueuing +system.physmem.readRowHits 316322 # Number of row buffer hits during reads +system.physmem.writeRowHits 220133 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.65 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.50 # Row buffer hit rate for writes +system.physmem.avgGap 712871.05 # Average gap between requests +system.physmem.pageHitRate 78.55 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 538191780 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 286032945 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1405566120 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 792980640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 13571251200.000004 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 8851881120 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 742850400 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 36305173020 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 16998972000 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 84070895340 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 163568832135 # Total energy per rank (pJ) +system.physmem_0.averagePower 335.835307 # Core power per rank (mW) +system.physmem_0.totalIdleTime 465691902250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 1184996500 # Time in different power states +system.physmem_0.memoryStateTime::REF 5763492000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 341808238000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 44268234250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 14409717250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 79616051500 # Time in different power states +system.physmem_1.actEnergy 507311280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 269615775 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1360634100 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 749325780 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 13094905200.000004 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 8819547870 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 717418080 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 34208424030 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 16648938720 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 85396744800 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 161777173725 # Total energy per rank (pJ) +system.physmem_1.averagePower 332.156722 # Core power per rank (mW) +system.physmem_1.totalIdleTime 465831856000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 1145526000 # Time in different power states +system.physmem_1.memoryStateTime::REF 5561926000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 347456670000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 43356567250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14511269750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 75018770500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 299198029 # Number of BP lookups +system.cpu.branchPred.condPredicted 299198029 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 24258277 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 226066805 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 40347150 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4410395 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 229902551 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 119869207 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 110033344 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 11602477 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 40193400 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4437789 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 226066805 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 118144411 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 107922394 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 11883156 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 487172057000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 974344115 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 487050729500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 974101460 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 229691872 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1587782946 # Number of instructions fetch has processed -system.cpu.fetch.Branches 297986094 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 160216357 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 719926348 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 48165553 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1415 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 32240 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 400644 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 8846 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 32 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 216441049 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6311436 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 974144173 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.051993 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.490984 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 230169557 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1594277830 # Number of instructions fetch has processed +system.cpu.fetch.Branches 299198029 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 158337811 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 718471067 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 49469999 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 2698 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 34945 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 480096 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 4714 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 69 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 216546560 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6526632 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 8 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 973898145 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.063667 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.497102 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 482346160 49.51% 49.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 36602331 3.76% 53.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 36258722 3.72% 56.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33122325 3.40% 60.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28552285 2.93% 63.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 29954375 3.07% 66.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40147511 4.12% 70.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 37554957 3.86% 74.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 249605507 25.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 481357803 49.43% 49.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 36544666 3.75% 53.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 36285723 3.73% 56.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 32866211 3.37% 60.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28367371 2.91% 63.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 29577354 3.04% 66.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 39843150 4.09% 70.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 36876934 3.79% 74.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 252178933 25.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 974144173 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.305832 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.629592 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 165741449 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 390914156 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 312062305 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 81343487 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 24082776 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2744526803 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 24082776 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 201646050 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 200648481 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15573 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 351553209 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 196198084 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2627040726 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 843366 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 120856771 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 22890286 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 43959941 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2707701926 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6592856104 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4207544155 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2527327 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 973898145 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.307153 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.636665 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 166490369 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 388298779 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 313723542 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 80650456 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 24734999 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2751923456 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 24734999 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 202899221 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 199700520 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14210 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 351959746 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 194589449 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2631585273 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 503822 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 119585114 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 21729790 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 44646970 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2710512651 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6600728549 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4213051781 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1976674 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1616961572 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1090740354 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1231 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1132 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 368340883 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 608352131 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 244132697 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 253219333 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 76661135 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2419790234 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 118502 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1999387601 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3615961 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 889826216 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1510217601 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 117950 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 974144173 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.052456 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.105356 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1093551079 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 884 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 794 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 367177164 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 608809294 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 243550763 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 252688912 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 75518257 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2418516015 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 104540 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1999668107 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3656750 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 888538035 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1505526254 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 103988 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 973898145 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.053262 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.107501 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 345565196 35.47% 35.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 135254480 13.88% 49.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 130135429 13.36% 62.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 118774957 12.19% 74.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 97965180 10.06% 84.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 67350848 6.91% 91.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 45621638 4.68% 96.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 22618956 2.32% 98.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10857489 1.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 345655298 35.49% 35.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 135232191 13.89% 49.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 129689064 13.32% 62.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 119012847 12.22% 74.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 97852872 10.05% 84.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 66913699 6.87% 91.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 45825912 4.71% 96.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 22646304 2.33% 98.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11069958 1.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 974144173 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 973898145 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11247867 43.19% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11962828 45.93% 89.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2737897 10.51% 99.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 96082 0.37% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11137608 43.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11929198 46.06% 89.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2740827 10.58% 99.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 92541 0.36% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2913186 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1333691578 66.71% 66.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 358355 0.02% 66.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 4798525 0.24% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 471253849 23.57% 90.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 185928557 9.30% 99.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 5 0.00% 99.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 443541 0.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2900375 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1333719780 66.70% 66.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 357536 0.02% 66.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 4798411 0.24% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 4 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 471767183 23.59% 90.69% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 185670018 9.29% 99.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 6 0.00% 99.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 454793 0.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1999387601 # Type of FU issued -system.cpu.iq.rate 2.052034 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26044674 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013026 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5001332322 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3306265401 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1924007332 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1247688 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4044576 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 235696 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2021979456 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 539633 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 179731986 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1999668107 # Type of FU issued +system.cpu.iq.rate 2.052833 # Inst issue rate +system.cpu.iq.fu_busy_cnt 25900174 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012952 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5001578236 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3304560217 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1922724831 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1213047 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 3212370 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 280288 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2022120560 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 547346 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 180407023 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 224269113 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 336817 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 641986 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94974502 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 224726218 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 356451 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 693943 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94392568 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 32014 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 878 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 33314 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 814 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 24082776 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 149888848 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6862033 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2419908736 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1314714 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 608352426 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 244132697 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 41176 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1469227 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4543982 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 641986 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8726699 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 20674839 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 29401538 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1945912356 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 456814163 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 53475245 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 24734999 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 149663879 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6607902 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2418620555 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1417513 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 608809531 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 243550763 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 36150 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1478128 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4302509 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 693943 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8551096 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 21778410 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 30329506 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1944942401 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 457167604 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 54725706 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 635656680 # number of memory reference insts executed -system.cpu.iew.exec_branches 185192217 # Number of branches executed -system.cpu.iew.exec_stores 178842517 # Number of stores executed -system.cpu.iew.exec_rate 1.997151 # Inst execution rate -system.cpu.iew.wb_sent 1934768958 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1924243028 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1457137045 # num instructions producing a value -system.cpu.iew.wb_consumers 2204058928 # num instructions consuming a value -system.cpu.iew.wb_rate 1.974911 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.661115 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 889901292 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 635670117 # number of memory reference insts executed +system.cpu.iew.exec_branches 185387955 # Number of branches executed +system.cpu.iew.exec_stores 178502513 # Number of stores executed +system.cpu.iew.exec_rate 1.996653 # Inst execution rate +system.cpu.iew.wb_sent 1933639401 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1923005119 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1456045504 # num instructions producing a value +system.cpu.iew.wb_consumers 2200626785 # num instructions consuming a value +system.cpu.iew.wb_rate 1.974132 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.661650 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 888612801 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 23658010 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 841376599 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.818547 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.459268 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 24293835 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 840170563 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.821157 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.461954 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 361645102 42.98% 42.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 184788916 21.96% 64.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57757386 6.86% 71.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 87297113 10.38% 82.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 30407785 3.61% 85.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26554015 3.16% 88.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10439709 1.24% 90.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9044560 1.07% 91.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 73442013 8.73% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 361187525 42.99% 42.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 184077910 21.91% 64.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57677028 6.86% 71.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 87256558 10.39% 82.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 30345133 3.61% 85.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26488854 3.15% 88.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10500866 1.25% 90.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9042630 1.08% 91.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 73594059 8.76% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 841376599 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 840170563 # Number of insts commited each cycle system.cpu.commit.committedInsts 826847303 # Number of instructions committed system.cpu.commit.committedOps 1530082520 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -597,495 +599,494 @@ system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1530082520 # Class of committed instruction -system.cpu.commit.bw_lim_events 73442013 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3187918398 # The number of ROB reads -system.cpu.rob.rob_writes 4974407602 # The number of ROB writes -system.cpu.timesIdled 2034 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 199942 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 73594059 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3185271825 # The number of ROB reads +system.cpu.rob.rob_writes 4972894886 # The number of ROB writes +system.cpu.timesIdled 2025 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 203315 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826847303 # Number of Instructions Simulated system.cpu.committedOps 1530082520 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.178385 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.178385 # CPI: Total CPI of All Threads -system.cpu.ipc 0.848619 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.848619 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2928729782 # number of integer regfile reads -system.cpu.int_regfile_writes 1576941499 # number of integer regfile writes -system.cpu.fp_regfile_reads 236699 # number of floating regfile reads -system.cpu.fp_regfile_writes 4 # number of floating regfile writes -system.cpu.cc_regfile_reads 617876716 # number of cc regfile reads -system.cpu.cc_regfile_writes 419949697 # number of cc regfile writes -system.cpu.misc_regfile_reads 1064375270 # number of misc regfile reads +system.cpu.cpi 1.178091 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.178091 # CPI: Total CPI of All Threads +system.cpu.ipc 0.848831 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.848831 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2927263565 # number of integer regfile reads +system.cpu.int_regfile_writes 1575987355 # number of integer regfile writes +system.cpu.fp_regfile_reads 281295 # number of floating regfile reads +system.cpu.fp_regfile_writes 5 # number of floating regfile writes +system.cpu.cc_regfile_reads 617980900 # number of cc regfile reads +system.cpu.cc_regfile_writes 419571241 # number of cc regfile writes +system.cpu.misc_regfile_reads 1064489388 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2546054 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.989792 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 421112007 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2550150 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.132250 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1890456500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.989792 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998044 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998044 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2545571 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.077195 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 420813077 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2549667 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.046289 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1863239500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.077195 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998066 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998066 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 594 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3458 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 606 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3449 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 851486020 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 851486020 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 272742549 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 272742549 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148366794 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148366794 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 421109343 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 421109343 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 421109343 # number of overall hits -system.cpu.dcache.overall_hits::total 421109343 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2567175 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2567175 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 791417 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 791417 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3358592 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3358592 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3358592 # number of overall misses -system.cpu.dcache.overall_misses::total 3358592 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 63549852500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 63549852500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26385909500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26385909500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 89935762000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 89935762000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 89935762000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 89935762000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 275309724 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 275309724 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 850870799 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 850870799 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 272443625 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 272443625 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148366897 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148366897 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 420810522 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 420810522 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 420810522 # number of overall hits +system.cpu.dcache.overall_hits::total 420810522 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2558730 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2558730 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 791314 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 791314 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3350044 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3350044 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3350044 # number of overall misses +system.cpu.dcache.overall_misses::total 3350044 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 62817542000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 62817542000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26367570500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26367570500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 89185112500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 89185112500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 89185112500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 89185112500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 275002355 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 275002355 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 424467935 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 424467935 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 424467935 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 424467935 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009325 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009325 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005306 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007912 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007912 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007912 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007912 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24754.780060 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24754.780060 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33340.084304 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33340.084304 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26777.817014 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26777.817014 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26777.817014 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26777.817014 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12440 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 10775 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 917 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.565976 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 769.642857 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2337949 # number of writebacks -system.cpu.dcache.writebacks::total 2337949 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 800910 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 800910 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5810 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 5810 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 806720 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 806720 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 806720 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 806720 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766265 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1766265 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785607 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 785607 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2551872 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2551872 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2551872 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2551872 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37580006000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 37580006000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25494312000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 25494312000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63074318000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 63074318000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63074318000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 63074318000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006416 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006416 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006012 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006012 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006012 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006012 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21276.538911 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21276.538911 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32451.737319 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32451.737319 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24716.881568 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24716.881568 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24716.881568 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24716.881568 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 4004 # number of replacements -system.cpu.icache.tags.tagsinuse 1085.037164 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 216431030 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5719 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 37844.208778 # Average number of references to valid blocks. +system.cpu.dcache.demand_accesses::cpu.data 424160566 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 424160566 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 424160566 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 424160566 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009304 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009304 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005305 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005305 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.007898 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007898 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007898 # 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number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 901 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.088790 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 1004.384615 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2337865 # number of writebacks +system.cpu.dcache.writebacks::total 2337865 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 792851 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 792851 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5950 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 5950 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 798801 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 798801 # 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number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25475564000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 25475564000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63101626000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 63101626000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63101626000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 63101626000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006421 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006421 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005265 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005265 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006015 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006015 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006015 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006015 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21307.270770 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21307.270770 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32437.906499 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32437.906499 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24733.679230 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24733.679230 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24733.679230 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24733.679230 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 3942 # number of replacements +system.cpu.icache.tags.tagsinuse 1083.391017 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 216536709 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5668 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 38203.371383 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1085.037164 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.529803 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.529803 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1715 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1083.391017 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.529000 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.529000 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1726 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1557 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.837402 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 432889551 # Number of tag accesses -system.cpu.icache.tags.data_accesses 432889551 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 216431266 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 216431266 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 216431266 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 216431266 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 216431266 # number of overall hits -system.cpu.icache.overall_hits::total 216431266 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9783 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9783 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9783 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9783 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9783 # number of overall misses -system.cpu.icache.overall_misses::total 9783 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 586259000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 586259000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 586259000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 586259000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 586259000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 586259000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 216441049 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 216441049 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 216441049 # 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number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 216536917 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 216536917 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 216536917 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 216536917 # number of overall hits +system.cpu.icache.overall_hits::total 216536917 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9643 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9643 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9643 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9643 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9643 # number of overall misses +system.cpu.icache.overall_misses::total 9643 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 597021000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 597021000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 597021000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 597021000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 597021000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 597021000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 216546560 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 216546560 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 216546560 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 216546560 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 216546560 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 216546560 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59926.300726 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 59926.300726 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 59926.300726 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 59926.300726 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 59926.300726 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 59926.300726 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 654 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 486 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 65.400000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 486 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 4004 # number of writebacks -system.cpu.icache.writebacks::total 4004 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2330 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2330 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2330 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2330 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2330 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2330 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7453 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7453 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7453 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7453 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7453 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7453 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 386965000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 386965000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 386965000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 386965000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 386965000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 386965000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51920.703073 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51920.703073 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51920.703073 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51920.703073 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51920.703073 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51920.703073 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 356023 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30628.268694 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4712326 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 388791 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.120461 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 83034365000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 73.003370 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 193.382004 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30361.883320 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.002228 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005902 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.926571 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.934701 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61912.371669 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61912.371669 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61912.371669 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61912.371669 # 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average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 295461 # number of writebacks -system.cpu.l2cache.writebacks::total 295461 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 11 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 11 # number of CleanEvict MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 8 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 8 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206765 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206765 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2422 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2422 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 178399 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 178399 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2422 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 385164 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 387586 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2422 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 385164 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 387586 # number of overall MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 159000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 159000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16164902000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16164902000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 314877000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 314877000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16422421000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16422421000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 314877000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32587323000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 32902200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 314877000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32587323000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 32902200000 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 295491 # number of writebacks +system.cpu.l2cache.writebacks::total 295491 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206826 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206826 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2443 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2443 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 178467 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 178467 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2443 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 385293 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 387736 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2443 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 385293 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 387736 # number of overall MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 120000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 120000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16149197500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16149197500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 327396000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 327396000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16475140000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16475140000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 327396000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32624337500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 32951733500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 327396000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32624337500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 32951733500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.004646 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.004646 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263696 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263696 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.429966 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.429966 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.101016 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.101016 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.429966 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151036 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151651 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.429966 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151036 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151651 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19875 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19875 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78180.069161 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78180.069161 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 130007.018993 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 130007.018993 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92054.445372 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92054.445372 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 130007.018993 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84606.357292 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84890.063109 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 130007.018993 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84606.357292 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84890.063109 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5109383 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2550327 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23034 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3629 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3621 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1773498 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2633410 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4004 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 268667 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 1722 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 1722 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 784105 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 784105 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 7453 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1766045 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17090 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7649798 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7666888 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 616768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312838336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 313455104 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 357843 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 19025984 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2915348 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009238 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.095698 # Request fanout histogram +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.003807 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.003807 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263797 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263797 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.437030 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.437030 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.101078 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.101078 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.437030 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151115 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151741 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.437030 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151115 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151741 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78081.080232 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78081.080232 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 134013.917315 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 134013.917315 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92314.769677 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92314.769677 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 134013.917315 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84674.098673 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84984.973023 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 134013.917315 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84674.098673 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84984.973023 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5107999 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2549734 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 19983 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3565 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3558 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1772876 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2633356 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 3942 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 268356 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 1576 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 1576 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 784034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 784034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 7243 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1765633 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16775 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7648057 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7664832 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 610048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312802048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 313412096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 357794 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 19017216 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2914627 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.008154 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.089959 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2888424 99.08% 99.08% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 26916 0.92% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 8 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2890867 99.18% 99.18% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 23753 0.81% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2915348 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4896697394 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2914627 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4895855901 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 11180498 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10867494 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3826086106 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3825288599 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 740706 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 353592 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 740964 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 353722 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 180821 # Transaction distribution -system.membus.trans_dist::WritebackDirty 295461 # Transaction distribution -system.membus.trans_dist::CleanEvict 57651 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 180910 # Transaction distribution +system.membus.trans_dist::WritebackDirty 295491 # Transaction distribution +system.membus.trans_dist::CleanEvict 57731 # Transaction distribution system.membus.trans_dist::UpgradeReq 9 # Transaction distribution -system.membus.trans_dist::ReadExReq 206764 # Transaction distribution -system.membus.trans_dist::ReadExResp 206764 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 180821 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1128291 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1128291 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1128291 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43714944 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43714944 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43714944 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 206823 # Transaction distribution +system.membus.trans_dist::ReadExResp 206823 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 180910 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1128697 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1128697 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1128697 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43726336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43726336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43726336 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 387594 # Request fanout histogram +system.membus.snoop_fanout::samples 387742 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 387594 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 387742 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 387594 # Request fanout histogram -system.membus.reqLayer0.occupancy 1998981000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 387742 # Request fanout histogram +system.membus.reqLayer0.occupancy 1998138500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 2050982000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2051606500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- |