diff options
author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
---|---|---|
committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt | |
parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt')
-rw-r--r-- | tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt | 403 |
1 files changed, 249 insertions, 154 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index a04efd18a..58ea20ddf 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.139995 # Nu sim_ticks 139995113500 # Number of ticks simulated final_tick 139995113500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 118986 # Simulator instruction rate (inst/s) -host_tick_rate 41783300 # Simulator tick rate (ticks/s) -host_mem_usage 214012 # Number of bytes of host memory used -host_seconds 3350.50 # Real time elapsed on the host +host_inst_rate 154307 # Simulator instruction rate (inst/s) +host_op_rate 154307 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54186341 # Simulator tick rate (ticks/s) +host_mem_usage 215920 # Number of bytes of host memory used +host_seconds 2583.59 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated +sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read 469184 # Number of bytes read from this memory system.physmem.bytes_inst_read 214784 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -68,9 +70,10 @@ system.cpu.comNops 23089775 # Nu system.cpu.comNonSpec 215 # Number of Non-Speculative instructions committed system.cpu.comInts 112239074 # Number of Integer instructions committed system.cpu.comFloats 50439198 # Number of Floating Point instructions committed -system.cpu.committedInsts 398664595 # Number of Instructions Simulated (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 398664595 # Number of Instructions Simulated (Total) +system.cpu.committedInsts 398664595 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) +system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) system.cpu.cpi 0.702320 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.cpi_total 0.702320 # CPI: Total CPI of All Threads @@ -124,26 +127,39 @@ system.cpu.icache.total_refs 48855472 # To system.cpu.icache.sampled_refs 3897 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 12536.687708 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1829.847469 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.893480 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 48855472 # number of ReadReq hits -system.cpu.icache.demand_hits 48855472 # number of demand (read+write) hits -system.cpu.icache.overall_hits 48855472 # number of overall hits -system.cpu.icache.ReadReq_misses 4376 # number of ReadReq misses -system.cpu.icache.demand_misses 4376 # number of demand (read+write) misses -system.cpu.icache.overall_misses 4376 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 214318500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 214318500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 214318500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 48859848 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 48859848 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 48859848 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000090 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000090 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000090 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 48975.891225 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 48975.891225 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 48975.891225 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1829.847469 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.893480 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.893480 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 48855472 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 48855472 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 48855472 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 48855472 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 48855472 # number of overall hits +system.cpu.icache.overall_hits::total 48855472 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4376 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4376 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4376 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4376 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4376 # number of overall misses +system.cpu.icache.overall_misses::total 4376 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 214318500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 214318500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 214318500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 214318500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 214318500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 214318500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 48859848 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 48859848 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 48859848 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 48859848 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 48859848 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 48859848 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000090 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000090 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000090 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48975.891225 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48975.891225 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48975.891225 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 45000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -152,27 +168,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets 45000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 479 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 479 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 479 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 3897 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 3897 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 3897 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 185285000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 185285000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 185285000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000080 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000080 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 47545.547857 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 47545.547857 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 47545.547857 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 479 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 479 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 479 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 479 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 479 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 479 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3897 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 3897 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 3897 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 3897 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 3897 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 3897 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 185285000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 185285000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 185285000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 185285000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 185285000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 185285000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47545.547857 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47545.547857 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47545.547857 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.tagsinuse 3284.892021 # Cycle average of tags in use @@ -180,32 +199,49 @@ system.cpu.dcache.total_refs 168261959 # To system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 40525.519990 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3284.892021 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.801976 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 94753265 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 73508694 # number of WriteReq hits -system.cpu.dcache.demand_hits 168261959 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 168261959 # number of overall hits -system.cpu.dcache.ReadReq_misses 1224 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 12035 # number of WriteReq misses -system.cpu.dcache.demand_misses 13259 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 13259 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 63830500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 626731500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 690562000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 690562000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 94754489 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 168275218 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 168275218 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000164 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000079 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000079 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 52149.101307 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 52075.737432 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 52082.509993 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 52082.509993 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 3284.892021 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.801976 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.801976 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 94753265 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94753265 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73508694 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73508694 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168261959 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168261959 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168261959 # number of overall hits +system.cpu.dcache.overall_hits::total 168261959 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1224 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1224 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 12035 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 12035 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 13259 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 13259 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 13259 # number of overall misses +system.cpu.dcache.overall_misses::total 13259 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 63830500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 63830500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 626731500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 626731500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 690562000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 690562000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 690562000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 690562000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 168275218 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168275218 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168275218 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000013 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000164 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000079 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000079 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52149.101307 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52075.737432 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52082.509993 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52082.509993 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 82468500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -214,32 +250,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 44625.811688 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 649 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 274 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 8833 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 9107 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 9107 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 46185000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 169537500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 215722500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 215722500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48615.789474 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52947.376640 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 51956.286127 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 51956.286127 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 649 # number of writebacks +system.cpu.dcache.writebacks::total 649 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 274 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 274 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8833 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 8833 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 9107 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 9107 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 9107 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 9107 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 46185000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 46185000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 169537500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 169537500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215722500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 215722500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215722500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 215722500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48615.789474 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52947.376640 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51956.286127 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51956.286127 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 13 # number of replacements system.cpu.l2cache.tagsinuse 3900.004949 # Cycle average of tags in use @@ -247,36 +291,75 @@ system.cpu.l2cache.total_refs 729 # To system.cpu.l2cache.sampled_refs 4720 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.154449 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3529.472340 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 370.532609 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.107711 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.011308 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 658 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 649 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 60 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 718 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 718 # number of overall hits -system.cpu.l2cache.ReadReq_misses 4186 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 3145 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 7331 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 7331 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 219209500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 164966000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 384175500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 384175500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 4844 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 649 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 3205 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 8049 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 8049 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.864162 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.981279 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.910796 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.910796 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52367.295748 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52453.418124 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52404.242259 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52404.242259 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 370.532609 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2905.642885 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 623.829454 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.088673 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019038 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.119019 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 541 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 117 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 658 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 541 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 177 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 718 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 541 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 177 # number of overall hits +system.cpu.l2cache.overall_hits::total 718 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3356 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 830 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4186 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 3145 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 3145 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3356 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3975 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7331 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3356 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3975 # number of overall misses +system.cpu.l2cache.overall_misses::total 7331 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 175581500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43628000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 219209500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 164966000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 164966000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 175581500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 208594000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 384175500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 175581500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 208594000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 384175500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 3897 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 4844 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 3205 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 3205 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 3897 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8049 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 3897 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 8049 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.861175 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.876452 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981279 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.861175 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.957370 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.861175 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.957370 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.682956 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52563.855422 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52453.418124 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.682956 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52476.477987 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.682956 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52476.477987 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -285,30 +368,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 4186 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 3145 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 7331 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 7331 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 168226500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 126764000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 294990500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 294990500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.864162 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.981279 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.910796 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.910796 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40187.888199 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40306.518283 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40238.780521 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40238.780521 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3356 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 830 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4186 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3145 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3145 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3356 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3975 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7331 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3356 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3975 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7331 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134709500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33517000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 168226500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126764000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126764000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134709500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160281000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 294990500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134709500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160281000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 294990500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.861175 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876452 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.861175 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.861175 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40139.898689 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40381.927711 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40306.518283 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40139.898689 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40322.264151 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40139.898689 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40322.264151 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |