diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:14:42 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:14:42 -0400 |
| commit | 8fe556338db4cc50a3f1ba20306bc5e464941f2b (patch) | |
| tree | d95b1933c18d142f9c533f32ac7b84bd1f2d0da5 /tests/long/se/30.eon/ref/alpha/tru64/inorder-timing | |
| parent | 66e331c7bb7d503c35808325e1bfaa9f18f4bdb9 (diff) | |
| download | gem5-8fe556338db4cc50a3f1ba20306bc5e464941f2b.tar.xz | |
stats: Update stats to reflect use of SimpleDRAM
This patch bumps the stats to match the use of SimpleDRAM instead of
SimpleMemory in all inorder and O3 regressions, and also all
full-system regressions. A number of performance-related stats change,
and a whole bunch of stats are added for the memory controller.
Diffstat (limited to 'tests/long/se/30.eon/ref/alpha/tru64/inorder-timing')
| -rw-r--r-- | tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt | 598 |
1 files changed, 378 insertions, 220 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index c1850cccb..1c69e7033 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.141181 # Number of seconds simulated -sim_ticks 141180939500 # Number of ticks simulated -final_tick 141180939500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.141149 # Number of seconds simulated +sim_ticks 141148809500 # Number of ticks simulated +final_tick 141148809500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139974 # Simulator instruction rate (inst/s) -host_op_rate 139974 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49569488 # Simulator tick rate (ticks/s) -host_mem_usage 218836 # Number of bytes of host memory used -host_seconds 2848.14 # Real time elapsed on the host +host_inst_rate 76319 # Simulator instruction rate (inst/s) +host_op_rate 76319 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27020959 # Simulator tick rate (ticks/s) +host_mem_usage 222760 # Number of bytes of host memory used +host_seconds 5223.68 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 214592 # Number of bytes read from this memory @@ -19,14 +19,172 @@ system.physmem.bytes_inst_read::total 214592 # Nu system.physmem.num_reads::cpu.inst 3353 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7322 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1519979 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1799223 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3319202 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1519979 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1519979 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1519979 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1799223 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3319202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1520325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1799633 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3319957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1520325 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1520325 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1520325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1799633 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3319957 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7322 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 7322 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 468608 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 468608 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 464 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 518 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 520 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 382 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 397 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 457 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 443 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 405 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 457 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 588 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 397 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 529 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 418 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 395 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 487 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 141148757500 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 7322 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 5336 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1506 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 331 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 28738807 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 171664807 # Sum of mem lat for all requests +system.physmem.totBusLat 29288000 # Total cycles spent in databus access +system.physmem.totBankLat 113638000 # Total cycles spent in bank access +system.physmem.avgQLat 3924.99 # Average queueing delay per request +system.physmem.avgBankLat 15520.08 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 23445.07 # Average memory access latency +system.physmem.avgRdBW 3.32 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.32 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 6437 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.91 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 19277350.11 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -35,18 +193,18 @@ system.cpu.dtb.read_hits 94755019 # DT system.cpu.dtb.read_misses 21 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 94755040 # DTB read accesses -system.cpu.dtb.write_hits 73522102 # DTB write hits +system.cpu.dtb.write_hits 73522092 # DTB write hits system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73522137 # DTB write accesses -system.cpu.dtb.data_hits 168277121 # DTB hits +system.cpu.dtb.write_accesses 73522127 # DTB write accesses +system.cpu.dtb.data_hits 168277111 # DTB hits system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168277177 # DTB accesses -system.cpu.itb.fetch_hits 49111833 # ITB hits +system.cpu.dtb.data_accesses 168277167 # DTB accesses +system.cpu.itb.fetch_hits 49111843 # ITB hits system.cpu.itb.fetch_misses 88782 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 49200615 # ITB accesses +system.cpu.itb.fetch_accesses 49200625 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,26 +218,26 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 282361880 # number of cpu cycles simulated +system.cpu.numCycles 282297620 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 53870354 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 30921657 # Number of conditional branches predicted +system.cpu.branch_predictor.lookups 53870359 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 30921660 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 16037209 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 33426941 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 15653987 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 33426943 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 15653988 # Number of BTB hits system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 18 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 46.830450 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 29683846 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 24186508 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 280818440 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 46.830451 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 29683847 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 24186512 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 280818433 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 440154299 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 440154292 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 119907695 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 220104176 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100457653 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 100457659 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 168700458 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 14475221 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 1561329 # Number of Branches Incorrectly Predicted As Not Taken). @@ -90,12 +248,12 @@ system.cpu.execution_unit.executions 205750873 # Nu system.cpu.mult_div_unit.multiplies 2124330 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 281927927 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 281928004 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 8028 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13487383 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 268874497 # Number of cycles cpu stages are processed. -system.cpu.activity 95.223370 # Percentage of cycles cpu is active +system.cpu.timesIdled 8014 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13423125 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 268874495 # Number of cycles cpu stages are processed. +system.cpu.activity 95.245045 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -107,78 +265,78 @@ system.cpu.committedInsts 398664595 # Nu system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) -system.cpu.cpi 0.708269 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.708108 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.708269 # CPI: Total CPI of All Threads -system.cpu.ipc 1.411892 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.708108 # CPI: Total CPI of All Threads +system.cpu.ipc 1.412214 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.411892 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 78547913 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 203813967 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 72.181828 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 108875170 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 173486710 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.441265 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 104652466 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 177709414 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.936758 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 183580459 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 98781421 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 34.983979 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 92669372 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 189692508 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.180636 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.412214 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 78483642 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 203813978 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 72.198263 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 108810922 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 173486698 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 61.455246 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 104588213 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 177709407 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 62.951082 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 183516209 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 98781411 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 34.991939 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 92605054 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 189692566 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 67.195949 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1974 # number of replacements -system.cpu.icache.tagsinuse 1829.872355 # Cycle average of tags in use -system.cpu.icache.total_refs 49107443 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1830.000422 # Cycle average of tags in use +system.cpu.icache.total_refs 49107453 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 3901 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12588.424250 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 12588.426814 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1829.872355 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.893492 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.893492 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 49107443 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 49107443 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 49107443 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 49107443 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 49107443 # number of overall hits -system.cpu.icache.overall_hits::total 49107443 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 1830.000422 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.893555 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.893555 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 49107453 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 49107453 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 49107453 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 49107453 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 49107453 # number of overall hits +system.cpu.icache.overall_hits::total 49107453 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 4389 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 4389 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 4389 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 4389 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4389 # number of overall misses system.cpu.icache.overall_misses::total 4389 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 215239500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 215239500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 215239500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 215239500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 215239500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 215239500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 49111832 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 49111832 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 49111832 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 49111832 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 49111832 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 49111832 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 191814500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 191814500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 191814500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 191814500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 191814500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 191814500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 49111842 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 49111842 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 49111842 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 49111842 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 49111842 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 49111842 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000089 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000089 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000089 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000089 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000089 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000089 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49040.669856 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49040.669856 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49040.669856 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49040.669856 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49040.669856 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49040.669856 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43703.463203 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 43703.463203 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 43703.463203 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 43703.463203 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 43703.463203 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 43703.463203 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 90 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 66 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 90 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 66 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 488 # number of ReadReq MSHR hits @@ -193,58 +351,58 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3901 system.cpu.icache.demand_mshr_misses::total 3901 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3901 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3901 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 190519000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 190519000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 190519000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 190519000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 190519000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 190519000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 169767000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 169767000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 169767000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 169767000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 169767000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 169767000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48838.502948 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48838.502948 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48838.502948 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48838.502948 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48838.502948 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48838.502948 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43518.841323 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43518.841323 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43518.841323 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 43518.841323 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43518.841323 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 43518.841323 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3284.744401 # Cycle average of tags in use -system.cpu.dcache.total_refs 168261808 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3285.037423 # Cycle average of tags in use +system.cpu.dcache.total_refs 168261838 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 40525.483622 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 40525.490848 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3284.744401 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.801940 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.801940 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 94753261 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94753261 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73508547 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73508547 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168261808 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168261808 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168261808 # number of overall hits -system.cpu.dcache.overall_hits::total 168261808 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1228 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1228 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 12182 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 12182 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 13410 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 13410 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 13410 # number of overall misses -system.cpu.dcache.overall_misses::total 13410 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 65498000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 65498000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 641953000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 641953000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 707451000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 707451000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 707451000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 707451000 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 3285.037423 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.802011 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.802011 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 94753259 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94753259 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73508579 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73508579 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168261838 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168261838 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168261838 # number of overall hits +system.cpu.dcache.overall_hits::total 168261838 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1230 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1230 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 12150 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 12150 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 13380 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 13380 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 13380 # number of overall misses +system.cpu.dcache.overall_misses::total 13380 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 62962000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 62962000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 525724500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 525724500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 588686500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 588686500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 588686500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 588686500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -255,38 +413,38 @@ system.cpu.dcache.overall_accesses::cpu.data 168275218 system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000013 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000013 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000166 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000166 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000165 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000165 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000080 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000080 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000080 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000080 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53337.133550 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53337.133550 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52696.847808 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 52696.847808 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52755.480984 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52755.480984 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52755.480984 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52755.480984 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51188.617886 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51188.617886 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43269.506173 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43269.506173 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 43997.496263 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 43997.496263 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 43997.496263 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 43997.496263 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 171928 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 132949 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1907 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1897 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 90.156266 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 70.083817 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 649 # number of writebacks system.cpu.dcache.writebacks::total 649 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 278 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 278 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8980 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 8980 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 9258 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 9258 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 9258 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 9258 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 280 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8948 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 8948 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 9228 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 9228 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 9228 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 9228 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses @@ -295,14 +453,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48495500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 48495500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 175965000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 175965000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 224460500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 224460500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 224460500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 224460500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47641000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 47641000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 148441000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 148441000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 196082000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 196082000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 196082000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 196082000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -311,28 +469,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51047.894737 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51047.894737 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54954.715803 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54954.715803 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54060.814066 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 54060.814066 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54060.814066 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 54060.814066 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50148.421053 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50148.421053 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46358.838226 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46358.838226 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 47225.915222 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 47225.915222 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47225.915222 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 47225.915222 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3900.293758 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3900.679461 # Cycle average of tags in use system.cpu.l2cache.total_refs 754 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 4711 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.160051 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 370.502388 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2902.254610 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 627.536760 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011307 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.088570 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019151 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.119028 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 370.560631 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2902.521753 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 627.597077 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011309 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.088578 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019153 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.119039 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 548 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 671 # number of ReadReq hits @@ -357,17 +515,17 @@ system.cpu.l2cache.demand_misses::total 7322 # nu system.cpu.l2cache.overall_misses::cpu.inst 3353 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7322 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 181079500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 46077000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 227156500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 172190500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 172190500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 181079500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 218267500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 399347000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 181079500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 218267500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 399347000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 160328500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45215500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 205544000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 144675500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 144675500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 160328500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 189891000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 350219500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 160328500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 189891000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 350219500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4848 # number of ReadReq accesses(hits+misses) @@ -392,17 +550,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.909226 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859523 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.909226 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54005.219207 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55918.689320 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 54382.690927 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54750.556439 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54750.556439 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54005.219207 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54993.071303 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54540.699262 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54005.219207 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54993.071303 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54540.699262 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47816.433045 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54873.179612 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 49208.522863 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46001.748808 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46001.748808 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47816.433045 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47843.537415 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 47831.125376 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47816.433045 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47843.537415 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 47831.125376 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,17 +580,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7322 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3353 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7322 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 140250000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 36053500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 176303500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133849000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133849000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140250000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 169902500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 310152500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140250000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 169902500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 310152500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117992891 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 34864220 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 152857111 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 105232120 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 105232120 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117992891 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 140096340 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 258089231 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117992891 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 140096340 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 258089231 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.861592 # mshr miss rate for ReadReq accesses @@ -444,17 +602,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.909226 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.909226 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41828.213540 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43754.247573 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42208.163754 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42559.300477 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42559.300477 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41828.213540 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42807.382212 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42358.986616 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41828.213540 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42807.382212 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42358.986616 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35190.244855 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42310.946602 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36594.951161 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33460.133545 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33460.133545 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35190.244855 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35297.641723 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35248.460940 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35190.244855 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35297.641723 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35248.460940 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |