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| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-10-19 06:20:04 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-10-19 06:20:04 -0400 |
| commit | 607c2772915628c2c67c1c5bfdefaa33ae66a06e (patch) | |
| tree | f8f23fd4012f9a0053d65ac91792a7dc61d6baff /tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt | |
| parent | 71c982ff708cc3adc7c0eccf536fea34c20cc5f0 (diff) | |
| download | gem5-607c2772915628c2c67c1c5bfdefaa33ae66a06e.tar.xz | |
stats: Update stats to reflect recent changes to floats
Mostly just splitting out the floats ops and corresponding
reads/writes.
Diffstat (limited to 'tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index e0c918d80..2ec97b33e 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.233641 # Nu sim_ticks 233641094500 # Number of ticks simulated final_tick 233641094500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 295188 # Simulator instruction rate (inst/s) -host_op_rate 295188 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 172997788 # Simulator tick rate (ticks/s) -host_mem_usage 258004 # Number of bytes of host memory used -host_seconds 1350.54 # Real time elapsed on the host +host_inst_rate 449379 # Simulator instruction rate (inst/s) +host_op_rate 449379 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 263362780 # Simulator tick rate (ticks/s) +host_mem_usage 260228 # Number of bytes of host memory used +host_seconds 887.15 # Real time elapsed on the host sim_insts 398664651 # Number of instructions simulated sim_ops 398664651 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -327,7 +327,9 @@ system.cpu.op_class_0::FloatAdd 35620060 8.93% 50.80% # Cl system.cpu.op_class_0::FloatCmp 7072549 1.77% 52.57% # Class of committed instruction system.cpu.op_class_0::FloatCvt 2735231 0.69% 53.26% # Class of committed instruction system.cpu.op_class_0::FloatMult 16498021 4.14% 57.40% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 57.40% # Class of committed instruction system.cpu.op_class_0::FloatDiv 1563283 0.39% 57.79% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 57.79% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 57.79% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 57.79% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 57.79% # Class of committed instruction @@ -349,8 +351,10 @@ system.cpu.op_class_0::SimdFloatMisc 0 0.00% 57.79% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 57.79% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 57.79% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::MemRead 94754510 23.77% 81.56% # Class of committed instruction -system.cpu.op_class_0::MemWrite 73520764 18.44% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 46072315 11.56% 69.35% # Class of committed instruction +system.cpu.op_class_0::MemWrite 30396984 7.62% 76.97% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 48682195 12.21% 89.18% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 43123780 10.82% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 398664651 # Class of committed instruction |