diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
| commit | a217eba078b17c51f6a74c9237584f066ef78bf1 (patch) | |
| tree | e566cbeb3520341dbdf6ecb0d3932a31d4e156fe /tests/long/se/30.eon/ref/alpha/tru64/minor-timing | |
| parent | db430698bfd4d77a49e11031bb65444552891f37 (diff) | |
| download | gem5-a217eba078b17c51f6a74c9237584f066ef78bf1.tar.xz | |
stats: Update stats for CPU and cache changes
This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
Diffstat (limited to 'tests/long/se/30.eon/ref/alpha/tru64/minor-timing')
| -rw-r--r-- | tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt | 468 |
1 files changed, 234 insertions, 234 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index 0b41505d8..2ad80aa5a 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.219644 # Number of seconds simulated -sim_ticks 219644167500 # Number of ticks simulated -final_tick 219644167500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.220941 # Number of seconds simulated +sim_ticks 220941341500 # Number of ticks simulated +final_tick 220941341500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 184210 # Simulator instruction rate (inst/s) -host_op_rate 184210 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 101490439 # Simulator tick rate (ticks/s) -host_mem_usage 247040 # Number of bytes of host memory used -host_seconds 2164.19 # Real time elapsed on the host +host_inst_rate 303038 # Simulator instruction rate (inst/s) +host_op_rate 303038 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 167944827 # Simulator tick rate (ticks/s) +host_mem_usage 273400 # Number of bytes of host memory used +host_seconds 1315.56 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -19,12 +19,12 @@ system.physmem.bytes_inst_read::cpu.inst 249408 # Nu system.physmem.bytes_inst_read::total 249408 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 7875 # Number of read requests responded to by this memory system.physmem.num_reads::total 7875 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2294620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2294620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1135509 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1135509 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2294620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2294620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 2281148 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2281148 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1128843 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1128843 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2281148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2281148 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7875 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7875 # Number of DRAM read bursts, including those serviced by the write queue @@ -71,7 +71,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 219644086000 # Total gap between requests +system.physmem.totGap 220941260000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -86,8 +86,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6822 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 970 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6820 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 972 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -182,29 +182,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1515 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 331.828383 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 199.155331 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.926802 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 511 33.73% 33.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 341 22.51% 56.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 189 12.48% 68.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 107 7.06% 75.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 50 3.30% 79.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 60 3.96% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 36 2.38% 85.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 30 1.98% 87.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 191 12.61% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1515 # Bytes accessed per row activation -system.physmem.totQLat 51832750 # Total ticks spent queuing -system.physmem.totMemAccLat 199489000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1518 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 330.160738 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 197.894458 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.998951 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 519 34.19% 34.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 336 22.13% 56.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 186 12.25% 68.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 110 7.25% 75.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 56 3.69% 79.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 56 3.69% 83.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 37 2.44% 85.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 28 1.84% 87.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 190 12.52% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1518 # Bytes accessed per row activation +system.physmem.totQLat 52730250 # Total ticks spent queuing +system.physmem.totMemAccLat 200386500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 39375000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6581.94 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6695.90 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25331.94 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25445.90 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.28 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.28 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage @@ -212,18 +212,18 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6354 # Number of row buffer hits during reads +system.physmem.readRowHits 6348 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.69 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 27891312.51 # Average gap between requests -system.physmem.pageHitRate 80.69 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 210595847500 # Time in different power states -system.physmem.memoryStateTime::REF 7334340000 # Time in different power states +system.physmem.avgGap 28056033.02 # Average gap between requests +system.physmem.pageHitRate 80.61 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 211835989750 # Time in different power states +system.physmem.memoryStateTime::REF 7377500000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1712418250 # Time in different power states +system.physmem.memoryStateTime::ACT 1721627750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 2294620 # Throughput (bytes/s) +system.membus.throughput 2281148 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 4737 # Transaction distribution system.membus.trans_dist::ReadResp 4737 # Transaction distribution system.membus.trans_dist::ReadExReq 3138 # Transaction distribution @@ -234,40 +234,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 504000 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 504000 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 9401500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9511500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 73916250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 74010500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 46223200 # Number of BP lookups -system.cpu.branchPred.condPredicted 26710359 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1014875 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25598344 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21333887 # Number of BTB hits +system.cpu.branchPred.lookups 46221231 # Number of BP lookups +system.cpu.branchPred.condPredicted 26710053 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1012987 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 25408308 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21330923 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.340887 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 8326899 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 83.952552 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 8326726 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 95595217 # DTB read hits -system.cpu.dtb.read_misses 114 # DTB read misses +system.cpu.dtb.read_hits 95595776 # DTB read hits +system.cpu.dtb.read_misses 118 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 95595331 # DTB read accesses -system.cpu.dtb.write_hits 73605959 # DTB write hits +system.cpu.dtb.read_accesses 95595894 # DTB read accesses +system.cpu.dtb.write_hits 73604420 # DTB write hits system.cpu.dtb.write_misses 858 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73606817 # DTB write accesses -system.cpu.dtb.data_hits 169201176 # DTB hits -system.cpu.dtb.data_misses 972 # DTB misses +system.cpu.dtb.write_accesses 73605278 # DTB write accesses +system.cpu.dtb.data_hits 169200196 # DTB hits +system.cpu.dtb.data_misses 976 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 169202148 # DTB accesses -system.cpu.itb.fetch_hits 98054052 # ITB hits -system.cpu.itb.fetch_misses 1240 # ITB misses +system.cpu.dtb.data_accesses 169201172 # DTB accesses +system.cpu.itb.fetch_hits 98242303 # ITB hits +system.cpu.itb.fetch_misses 1225 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 98055292 # ITB accesses +system.cpu.itb.fetch_accesses 98243528 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -281,70 +281,70 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 439288335 # number of cpu cycles simulated +system.cpu.numCycles 441882683 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664665 # Number of instructions committed system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4458110 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 4446127 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.101899 # CPI: cycles per instruction -system.cpu.ipc 0.907524 # IPC: instructions per cycle -system.cpu.tickCycles 435056382 # Number of cycles that the object actually ticked -system.cpu.idleCycles 4231953 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.108407 # CPI: cycles per instruction +system.cpu.ipc 0.902196 # IPC: instructions per cycle +system.cpu.tickCycles 437732113 # Number of cycles that the object actually ticked +system.cpu.idleCycles 4150570 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 3195 # number of replacements -system.cpu.icache.tags.tagsinuse 1919.689869 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 98048879 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1919.708567 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 98237130 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 5173 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18953.968490 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 18990.359559 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1919.689869 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.937349 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.937349 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1919.708567 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.937358 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.937358 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 200 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 198 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 398 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1282 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 196113277 # Number of tag accesses -system.cpu.icache.tags.data_accesses 196113277 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 98048879 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 98048879 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 98048879 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 98048879 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 98048879 # number of overall hits -system.cpu.icache.overall_hits::total 98048879 # number of overall hits +system.cpu.icache.tags.tag_accesses 196489779 # Number of tag accesses +system.cpu.icache.tags.data_accesses 196489779 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 98237130 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 98237130 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 98237130 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 98237130 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 98237130 # number of overall hits +system.cpu.icache.overall_hits::total 98237130 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 5173 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 5173 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 5173 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 5173 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5173 # number of overall misses system.cpu.icache.overall_misses::total 5173 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 293884750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 293884750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 293884750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 293884750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 293884750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 293884750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 98054052 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 98054052 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 98054052 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 98054052 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 98054052 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 98054052 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 293554750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 293554750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 293554750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 293554750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 293554750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 293554750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 98242303 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 98242303 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 98242303 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 98242303 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 98242303 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 98242303 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000053 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000053 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000053 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56811.279722 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56811.279722 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56811.279722 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56811.279722 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56811.279722 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56811.279722 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56747.486951 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56747.486951 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56747.486951 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56747.486951 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56747.486951 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56747.486951 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -359,26 +359,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 5173 system.cpu.icache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 5173 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 5173 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281914250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281914250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281914250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281914250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281914250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281914250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281585250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 281585250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281585250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 281585250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281585250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 281585250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54497.245312 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54497.245312 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54497.245312 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54497.245312 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54497.245312 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54497.245312 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54433.645853 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54433.645853 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54433.645853 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54433.645853 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54433.645853 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54433.645853 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 2911473 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 2894379 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 6139 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 6139 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution @@ -394,24 +394,24 @@ system.cpu.toL2Bus.data_through_bus 639488 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 5650000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8571750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 8571250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6975500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6974750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4427.544414 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4427.627395 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1491 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5274 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.282708 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 373.069820 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4054.474595 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011385 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123733 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.135118 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 373.083919 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4054.543476 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011386 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123735 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.135120 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 5274 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 612 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4444 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160950 # Percentage of cache occupancy per task id @@ -435,14 +435,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 7875 # system.cpu.l2cache.demand_misses::total 7875 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 7875 # number of overall misses system.cpu.l2cache.overall_misses::total 7875 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 325631750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 325631750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 212036500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 212036500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 537668250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 537668250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 537668250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 537668250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 325767500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 325767500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 212904500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 212904500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 538672000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 538672000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 538672000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 538672000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 6139 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 6139 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 654 # number of Writeback accesses(hits+misses) @@ -461,14 +461,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.843328 system.cpu.l2cache.demand_miss_rate::total 0.843328 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.843328 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.843328 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68742.189149 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68742.189149 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67570.586361 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67570.586361 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68275.333333 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68275.333333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68275.333333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68275.333333 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68770.846527 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68770.846527 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67847.195666 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67847.195666 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68402.793651 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68402.793651 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68402.793651 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68402.793651 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -485,14 +485,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 7875 system.cpu.l2cache.demand_mshr_misses::total 7875 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 7875 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7875 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266250750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266250750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 172336000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 172336000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 438586750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 438586750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 438586750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 438586750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266387000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266387000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 173110500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 173110500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 439497500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 439497500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 439497500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 439497500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.771624 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771624 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.980932 # mshr miss rate for ReadExReq accesses @@ -501,65 +501,65 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.843328 system.cpu.l2cache.demand_mshr_miss_rate::total 0.843328 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.843328 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.843328 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56206.618113 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56206.618113 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54919.056724 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54919.056724 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55693.555556 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55693.555556 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55693.555556 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55693.555556 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56235.381043 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56235.381043 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55165.869981 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55165.869981 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55809.206349 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55809.206349 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55809.206349 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55809.206349 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.682067 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168006905 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3291.748201 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168007181 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40337.792317 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40337.858583 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.682067 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.803633 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803633 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.748201 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.803649 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803649 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336032209 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336032209 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 94492115 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94492115 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 73514790 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73514790 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 168006905 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168006905 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 168006905 # number of overall hits -system.cpu.dcache.overall_hits::total 168006905 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 1177 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1177 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 5940 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5940 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 7117 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7117 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 7117 # number of overall misses -system.cpu.dcache.overall_misses::total 7117 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 80734750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 80734750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 392862000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 392862000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 473596750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 473596750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 473596750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 473596750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 94493292 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94493292 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 336032765 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336032765 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 94492394 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94492394 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 73514787 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73514787 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 168007181 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168007181 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 168007181 # number of overall hits +system.cpu.dcache.overall_hits::total 168007181 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 1176 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1176 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 5943 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5943 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 7119 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7119 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 7119 # number of overall misses +system.cpu.dcache.overall_misses::total 7119 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 81035500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 81035500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 393767750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 393767750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 474803250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 474803250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 474803250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 474803250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 94493570 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94493570 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 73520730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 168014022 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168014022 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 168014022 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168014022 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.inst 168014300 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168014300 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 168014300 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168014300 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000081 # miss rate for WriteReq accesses @@ -568,14 +568,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.000042 system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68593.670348 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68593.670348 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66138.383838 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66138.383838 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66544.435858 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66544.435858 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66544.435858 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66544.435858 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68907.738095 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68907.738095 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66257.403668 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66257.403668 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66695.217025 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66695.217025 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66695.217025 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66695.217025 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -588,28 +588,28 @@ system.cpu.dcache.writebacks::writebacks 654 # nu system.cpu.dcache.writebacks::total 654 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 208 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 208 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2744 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2744 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 2952 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2952 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 2952 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2952 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 969 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 3196 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3196 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2746 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2746 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 2954 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2954 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 2954 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2954 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 968 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 968 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 3197 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3197 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.inst 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 64078250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 64078250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 215682250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 215682250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 279760500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 279760500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 279760500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 279760500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 64480250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 64480250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 216613000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 216613000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 281093250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 281093250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 281093250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 281093250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for WriteReq accesses @@ -618,14 +618,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66128.224974 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66128.224974 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67485.059449 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67485.059449 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67169.387755 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67169.387755 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67169.387755 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67169.387755 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66611.828512 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66611.828512 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67755.082890 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67755.082890 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67489.375750 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67489.375750 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67489.375750 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67489.375750 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |