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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-07-19 19:04:58 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-07-19 19:04:58 -0700 |
| commit | 040fa23d01109c68d194d2517df777844e4e2f13 (patch) | |
| tree | 822b7da72458db435480c20c1a3448f6158c62aa /tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini | |
| parent | 06bb6a473157a204bb7e77ea28e618aa08d2d811 (diff) | |
| download | gem5-040fa23d01109c68d194d2517df777844e4e2f13.tar.xz | |
stats: update for syscall DPRINTF change
Only printing one rather than two args for the ignored syscall
warning means the count of register accesses has changed on
a few runs. Oddly only Alpha Tru64 seems to have any ignored
syscalls in the regression tests.
Diffstat (limited to 'tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini')
| -rw-r--r-- | tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini index f722ba576..536d6ad31 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 [system] type=System -children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain @@ -37,7 +37,9 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +domain_id=-1 eventq_index=0 +init_perf_level=0 voltage_domain=system.voltage_domain [system.cpu] @@ -615,9 +617,19 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +domain_id=-1 eventq_index=0 +init_perf_level=0 voltage_domain=system.voltage_domain +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + [system.membus] type=CoherentBus clk_domain=system.clk_domain |