stats: Update stats for unified cache configuration

This patch updates the stats to reflect the changes in the L2 MSHRs,
as the latter are now uniform across the regressions.

1 files changed, 7 insertions, 7 deletions

diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
index 10dc822fe..26c4b55f8 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.567335                       # Nu
 sim_ticks                                567335093000                       # Number of ticks simulated
 final_tick                               567335093000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1259990                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1259990                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1793077476                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 225476                       # Number of bytes of host memory used
-host_seconds                                   316.40                       # Real time elapsed on the host
+host_inst_rate                                1803555                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1803555                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2566617886                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 223016                       # Number of bytes of host memory used
+host_seconds                                   221.04                       # Real time elapsed on the host
 sim_insts                                   398664609                       # Number of instructions simulated
 sim_ops                                     398664609                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            205120                       # Number of bytes read from this memory
@@ -262,9 +262,9 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse              3772.485305                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                     674                       # Total number of references to valid blocks.
+system.cpu.l2cache.total_refs                     677                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                  4566                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.147613                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.148270                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.occ_blocks::writebacks   371.540221                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_blocks::cpu.inst   2770.469924                       # Average occupied blocks per requestor