alpha: Remove ALPHA tru64 support and associated tests

No one appears to be using it, and it is causing build issues
and increases the development and maintenance effort.

1 files changed, 0 insertions, 555 deletions

diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
deleted file mode 100644
index 6d86d3450..000000000
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
+++ /dev/null
@@ -1,555 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.567393                       # Number of seconds simulated
-sim_ticks                                567392530500                       # Number of ticks simulated
-final_tick                               567392530500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1833225                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1833225                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2609105944                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 258692                       # Number of bytes of host memory used
-host_seconds                                   217.47                       # Real time elapsed on the host
-sim_insts                                   398664609                       # Number of instructions simulated
-sim_ops                                     398664609                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 567392530500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst            205120                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            254016                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               459136                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       205120                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          205120                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3205                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               3969                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7174                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               361513                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               447690                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                  809203                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          361513                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             361513                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              361513                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              447690                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                 809203                       # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 567392530500                       # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     94754490                       # DTB read hits
-system.cpu.dtb.read_misses                         21                       # DTB read misses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 94754511                       # DTB read accesses
-system.cpu.dtb.write_hits                    73520730                       # DTB write hits
-system.cpu.dtb.write_misses                        35                       # DTB write misses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                73520765                       # DTB write accesses
-system.cpu.dtb.data_hits                    168275220                       # DTB hits
-system.cpu.dtb.data_misses                         56                       # DTB misses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                168275276                       # DTB accesses
-system.cpu.itb.fetch_hits                   398664666                       # ITB hits
-system.cpu.itb.fetch_misses                       173                       # ITB misses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               398664839                       # ITB accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.workload.num_syscalls                  215                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON    567392530500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                       1134785061                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   398664609                       # Number of instructions committed
-system.cpu.committedOps                     398664609                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             316365921                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses              155295119                       # Number of float alu accesses
-system.cpu.num_func_calls                    16015498                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     25997790                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    316365921                       # number of integer instructions
-system.cpu.num_fp_insts                     155295119                       # number of float instructions
-system.cpu.num_int_register_reads           372938779                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          159335870                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads            151776196                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes           100196481                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     168275276                       # number of memory refs
-system.cpu.num_load_insts                    94754511                       # Number of load instructions
-system.cpu.num_store_insts                   73520765                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 1134785061                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.Branches                          44587535                       # Number of branches fetched
-system.cpu.op_class::No_OpClass              23123356      5.80%      5.80% # Class of executed instruction
-system.cpu.op_class::IntAlu                 141652567     35.53%     41.33% # Class of executed instruction
-system.cpu.op_class::IntMult                  2124322      0.53%     41.86% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     41.86% # Class of executed instruction
-system.cpu.op_class::FloatAdd                35620060      8.93%     50.80% # Class of executed instruction
-system.cpu.op_class::FloatCmp                 7072549      1.77%     52.57% # Class of executed instruction
-system.cpu.op_class::FloatCvt                 2735231      0.69%     53.26% # Class of executed instruction
-system.cpu.op_class::FloatMult               16498021      4.14%     57.40% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc                   0      0.00%     57.40% # Class of executed instruction
-system.cpu.op_class::FloatDiv                 1563283      0.39%     57.79% # Class of executed instruction
-system.cpu.op_class::FloatMisc                      0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     57.79% # Class of executed instruction
-system.cpu.op_class::MemRead                 46072316     11.56%     69.35% # Class of executed instruction
-system.cpu.op_class::MemWrite                30396985      7.62%     76.97% # Class of executed instruction
-system.cpu.op_class::FloatMemRead            48682195     12.21%     89.18% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite           43123780     10.82%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  398664665                       # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements               764                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3288.789389                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           168271068                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              4152                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          40527.713873                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3288.789389                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.802927                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.802927                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         3388                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           21                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           39                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3          210                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         3112                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.827148                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         336554592                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        336554592                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 567392530500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data     94753540                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        94753540                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     73517528                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       73517528                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     168271068                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        168271068                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    168271068                       # number of overall hits
-system.cpu.dcache.overall_hits::total       168271068                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          950                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           950                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         3202                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         3202                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         4152                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           4152                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         4152                       # number of overall misses
-system.cpu.dcache.overall_misses::total          4152                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     53715500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     53715500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    198735000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    198735000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    252450500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    252450500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    252450500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    252450500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     94754490                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     94754490                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     73520730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     73520730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    168275220                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    168275220                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    168275220                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    168275220                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000010                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000010                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000044                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000044                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000025                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000025                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000025                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000025                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56542.631579                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 56542.631579                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62065.896315                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 62065.896315                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 60802.143545                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 60802.143545                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 60802.143545                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 60802.143545                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks          649                       # number of writebacks
-system.cpu.dcache.writebacks::total               649                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          950                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          950                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3202                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         3202                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         4152                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         4152                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         4152                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         4152                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     52765500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     52765500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    195533000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    195533000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    248298500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    248298500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    248298500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    248298500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000010                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000044                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55542.631579                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55542.631579                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61065.896315                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61065.896315                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59802.143545                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 59802.143545                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59802.143545                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 59802.143545                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements              1769                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1795.076643                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           398660993                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              3673                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          108538.250204                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1795.076643                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.876502                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.876502                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1904                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          138                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           91                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          251                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1375                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.929688                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         797333005                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        797333005                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 567392530500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    398660993                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       398660993                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     398660993                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        398660993                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    398660993                       # number of overall hits
-system.cpu.icache.overall_hits::total       398660993                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         3673                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          3673                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         3673                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           3673                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         3673                       # number of overall misses
-system.cpu.icache.overall_misses::total          3673                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    208020000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    208020000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    208020000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    208020000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    208020000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    208020000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    398664666                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    398664666                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    398664666                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    398664666                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    398664666                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    398664666                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000009                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000009                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000009                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000009                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000009                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000009                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56634.903349                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 56634.903349                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 56634.903349                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 56634.903349                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 56634.903349                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 56634.903349                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks         1769                       # number of writebacks
-system.cpu.icache.writebacks::total              1769                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         3673                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         3673                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         3673                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         3673                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         3673                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         3673                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    204347000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    204347000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    204347000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    204347000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    204347000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    204347000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000009                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000009                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000009                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000009                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000009                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000009                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55634.903349                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55634.903349                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55634.903349                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 55634.903349                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55634.903349                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 55634.903349                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         6481.659208                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               3184                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             7174                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.443825                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2770.348214                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  3711.310994                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.084544                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.113260                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.197805                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         7174                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          116                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2           75                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          392                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         6535                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.218933                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            90038                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses           90038                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 567392530500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks          649                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total          649                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks         1769                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total         1769                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data           60                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total           60                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst          468                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total          468                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data          123                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total          123                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst          468                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data          183                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total             651                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst          468                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data          183                       # number of overall hits
-system.cpu.l2cache.overall_hits::total            651                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data         3142                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         3142                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3205                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         3205                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          827                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          827                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3205                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         3969                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          7174                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3205                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         3969                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         7174                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    190095000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    190095000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    193914000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    193914000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     50040500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     50040500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    193914000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    240135500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    434049500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    193914000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    240135500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    434049500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks          649                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total          649                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks         1769                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total         1769                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         3202                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         3202                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         3673                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         3673                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          950                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total          950                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         3673                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         4152                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         7825                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         3673                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         4152                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         7825                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.981262                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.981262                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.872584                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.872584                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.870526                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.870526                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.872584                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.955925                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.916805                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.872584                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.955925                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.916805                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60501.273074                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60501.273074                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60503.588144                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60503.588144                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60508.464329                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60508.464329                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60503.588144                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60502.771479                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 60503.136326                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60503.588144                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60502.771479                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 60503.136326                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3142                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         3142                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3205                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3205                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          827                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          827                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3205                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         3969                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         7174                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3205                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         3969                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         7174                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    158675000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    158675000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    161864000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    161864000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     41770500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     41770500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    161864000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    200445500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    362309500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    161864000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    200445500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    362309500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.981262                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.981262                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.872584                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.872584                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.870526                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.870526                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.872584                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.955925                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.916805                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.872584                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.955925                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.916805                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50501.273074                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50501.273074                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.588144                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.588144                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50508.464329                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50508.464329                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.588144                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50502.771479                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50503.136326                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.588144                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50502.771479                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50503.136326                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests        10358                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests         2533                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 567392530500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp          4623                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty          649                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean         1769                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict          115                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         3202                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         3202                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         3673                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq          950                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         9115                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9068                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             18183                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       348288                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       307264                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             655552                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples         7825                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0               7825    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total           7825                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        7597000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       5509500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       6228000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.snoop_filter.tot_requests          7174                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 567392530500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp               4032                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              3142                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             3142                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          4032                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14348                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  14348                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       459136                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  459136                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples              7174                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    7174    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                7174                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             7196500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           35870000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
-
----------- End Simulation Statistics   ----------