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| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
| commit | a217eba078b17c51f6a74c9237584f066ef78bf1 (patch) | |
| tree | e566cbeb3520341dbdf6ecb0d3932a31d4e156fe /tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt | |
| parent | db430698bfd4d77a49e11031bb65444552891f37 (diff) | |
| download | gem5-a217eba078b17c51f6a74c9237584f066ef78bf1.tar.xz | |
stats: Update stats for CPU and cache changes
This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
Diffstat (limited to 'tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index c52832ea0..f8ab96a0a 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.567335 # Nu sim_ticks 567335093000 # Number of ticks simulated final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1080224 # Simulator instruction rate (inst/s) -host_op_rate 1080224 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1537254294 # Simulator tick rate (ticks/s) -host_mem_usage 271408 # Number of bytes of host memory used -host_seconds 369.06 # Real time elapsed on the host +host_inst_rate 1556013 # Simulator instruction rate (inst/s) +host_op_rate 1556013 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2214344764 # Simulator tick rate (ticks/s) +host_mem_usage 270340 # Number of bytes of host memory used +host_seconds 256.21 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -102,10 +102,10 @@ system.cpu.not_idle_fraction 1 # Pe system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 44587535 # Number of branches fetched system.cpu.op_class::No_OpClass 23123356 5.80% 5.80% # Class of executed instruction -system.cpu.op_class::IntAlu 145805208 36.57% 42.37% # Class of executed instruction -system.cpu.op_class::IntMult 2124322 0.53% 42.91% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 42.91% # Class of executed instruction -system.cpu.op_class::FloatAdd 31467419 7.89% 50.80% # Class of executed instruction +system.cpu.op_class::IntAlu 141652567 35.53% 41.33% # Class of executed instruction +system.cpu.op_class::IntMult 2124322 0.53% 41.86% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 41.86% # Class of executed instruction +system.cpu.op_class::FloatAdd 35620060 8.93% 50.80% # Class of executed instruction system.cpu.op_class::FloatCmp 7072549 1.77% 52.57% # Class of executed instruction system.cpu.op_class::FloatCvt 2735231 0.69% 53.26% # Class of executed instruction system.cpu.op_class::FloatMult 16498021 4.14% 57.40% # Class of executed instruction |