stats: Update the stats to reflect bus and memory changes

This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.

1 files changed, 40 insertions, 5 deletions

diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
index 39d4d27ed..ff5b38f2f 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.567335                       # Nu
 sim_ticks                                567335093000                       # Number of ticks simulated
 final_tick                               567335093000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 853902                       # Simulator instruction rate (inst/s)
-host_op_rate                                   853902                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1215178011                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 278532                       # Number of bytes of host memory used
-host_seconds                                   466.87                       # Real time elapsed on the host
+host_inst_rate                                1715092                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1715091                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2440727076                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 230984                       # Number of bytes of host memory used
+host_seconds                                   232.45                       # Real time elapsed on the host
 sim_insts                                   398664609                       # Number of instructions simulated
 sim_ops                                     398664609                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            205120                       # Number of bytes read from this memory
@@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total             361550                       # In
 system.physmem.bw_total::cpu.inst              361550                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data              447735                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total                 809285                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                       809285                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                4032                       # Transaction distribution
+system.membus.trans_dist::ReadResp               4032                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              3142                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             3142                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side        14348                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count                         14348                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side       459136                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size                     459136                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                 459136                       # Total data (bytes)
+system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy             7174000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy           64566000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -396,5 +411,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 51148.843931
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput                  955936                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq           4623                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp          4623                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback          649                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         3202                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         3202                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side         7346                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side         8953                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count                    16299                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side       235072                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side       307264                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size                542336                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus            542336                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy        4886000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       5509500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy       6228000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------