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authorCurtis Dunham <Curtis.Dunham@arm.com>2016-10-13 23:21:40 +0100
committerCurtis Dunham <Curtis.Dunham@arm.com>2016-10-13 23:21:40 +0100
commitc87b717dbdf36f4b0ebef1df4592f1ebabad15a5 (patch)
treee8dab9b58aef6394538af96fd1c7f1f2ffaf5775 /tests/long/se/30.eon/ref/alpha/tru64
parent78dd152a0d5e55e26cd6c501dbc4f73e316937d9 (diff)
downloadgem5-c87b717dbdf36f4b0ebef1df4592f1ebabad15a5.tar.xz
stats: update references
Diffstat (limited to 'tests/long/se/30.eon/ref/alpha/tru64')
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini41
-rwxr-xr-xtests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout8
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt662
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini41
-rwxr-xr-xtests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout8
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt1274
6 files changed, 1036 insertions, 998 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini
index 00cf13ff8..63271ea71 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini
@@ -149,7 +149,7 @@ useIndirect=true
[system.cpu.dcache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
@@ -583,7 +583,7 @@ opClass=InstPrefetch
[system.cpu.icache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
@@ -643,7 +643,7 @@ size=48
[system.cpu.l2cache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
@@ -760,6 +760,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -771,7 +772,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -779,29 +780,36 @@ width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
[system.physmem]
type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
@@ -821,6 +829,7 @@ devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
+kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
@@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
@@ -852,9 +861,9 @@ tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
-tXP=0
+tXP=6000
tXPDLL=0
-tXS=0
+tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout
index 33c16c36c..6a622d0db 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-tim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 21 2016 14:09:28
-gem5 executing on e108600-lin, pid 4300
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:45
+gem5 executing on e108600-lin, pid 28070
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/alpha/tru64/minor-timing
Global frequency set at 1000000000000 ticks per second
@@ -14,4 +14,4 @@ info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.233333
-Exiting @ tick 233525789500 because target called exit()
+Exiting @ tick 233641094500 because target called exit()
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
index 6b30c3cf1..e0c918d80 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,19 +1,19 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.233534 # Number of seconds simulated
-sim_ticks 233533887500 # Number of ticks simulated
-final_tick 233533887500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.233641 # Number of seconds simulated
+sim_ticks 233641094500 # Number of ticks simulated
+final_tick 233641094500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 225573 # Simulator instruction rate (inst/s)
-host_op_rate 225573 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 132138421 # Simulator tick rate (ticks/s)
-host_mem_usage 260868 # Number of bytes of host memory used
-host_seconds 1767.34 # Real time elapsed on the host
+host_inst_rate 295188 # Simulator instruction rate (inst/s)
+host_op_rate 295188 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 172997788 # Simulator tick rate (ticks/s)
+host_mem_usage 258004 # Number of bytes of host memory used
+host_seconds 1350.54 # Real time elapsed on the host
sim_insts 398664651 # Number of instructions simulated
sim_ops 398664651 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 249280 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory
system.physmem.bytes_read::total 503872 # Number of bytes read from this memory
@@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 249280 # Nu
system.physmem.num_reads::cpu.inst 3895 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1067425 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1090172 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2157597 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1067425 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1067425 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1067425 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1090172 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2157597 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1066936 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1089671 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2156607 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1066936 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1066936 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1066936 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1089671 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2156607 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 7873 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 7873 # Number of DRAM read bursts, including those serviced by the write queue
@@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 233533785500 # Total gap between requests
+system.physmem.totGap 233641000500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
@@ -91,9 +91,9 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 6853 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 951 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 69 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 6664 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 1130 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 79 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
@@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1544 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 326.051813 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 195.846863 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 329.937998 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 532 34.46% 34.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 344 22.28% 56.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 193 12.50% 69.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 103 6.67% 75.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 73 4.73% 80.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 45 2.91% 83.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 32 2.07% 85.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 36 2.33% 87.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 186 12.05% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1544 # Bytes accessed per row activation
-system.physmem.totQLat 53440000 # Total ticks spent queuing
-system.physmem.totMemAccLat 201058750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples 1527 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 328.298625 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 196.524272 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 332.958390 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 522 34.18% 34.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 350 22.92% 57.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 181 11.85% 68.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 105 6.88% 75.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 64 4.19% 80.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 46 3.01% 83.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 30 1.96% 85.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 42 2.75% 87.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 187 12.25% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1527 # Bytes accessed per row activation
+system.physmem.totQLat 179319500 # Total ticks spent queuing
+system.physmem.totMemAccLat 326938250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 6787.76 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 22776.51 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 25537.76 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 41526.51 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s
@@ -217,53 +217,63 @@ system.physmem.busUtilRead 0.02 # Da
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 6327 # Number of row buffer hits during reads
+system.physmem.readRowHits 6337 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 80.36 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 80.49 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 29662617.24 # Average gap between requests
-system.physmem.pageHitRate 80.36 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 6758640 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 3687750 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 34296600 # Energy for read commands per rank (pJ)
+system.physmem.avgGap 29676235.30 # Average gap between requests
+system.physmem.pageHitRate 80.49 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 6326040 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 3347190 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 31444560 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 15253240080 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 6038642700 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 134822908500 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 156159534270 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.682165 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 224288059000 # Time in different power states
-system.physmem_0.memoryStateTime::REF 7798180000 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 1447046250 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 4914000 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 2681250 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 27058200 # Energy for read commands per rank (pJ)
+system.physmem_0.refreshEnergy 242168160.000000 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 105016230 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 11391840 # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy 673376340 # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy 320465280 # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy 55494876360 # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy 56888412000 # Total energy per rank (pJ)
+system.physmem_0.averagePower 243.486327 # Core power per rank (mW)
+system.physmem_0.totalIdleTime 233381065000 # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE 19761500 # Time in different power states
+system.physmem_0.memoryStateTime::REF 102860000 # Time in different power states
+system.physmem_0.memoryStateTime::SREF 231069881000 # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 834517500 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 137354250 # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 1476720250 # Time in different power states
+system.physmem_1.actEnergy 4641000 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 2447775 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 24768660 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 15253240080 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 5739994620 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 135084870750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 156112758900 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.481917 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 224725904750 # Time in different power states
-system.physmem_1.memoryStateTime::REF 7798180000 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 1009185250 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 45912940 # Number of BP lookups
-system.cpu.branchPred.condPredicted 26702743 # Number of conditional branches predicted
+system.physmem_1.refreshEnergy 215124000.000000 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 84187860 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 12227040 # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy 535263060 # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy 280836480 # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy 55611059460 # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy 56770555335 # Total energy per rank (pJ)
+system.physmem_1.averagePower 242.981892 # Core power per rank (mW)
+system.physmem_1.totalIdleTime 233423818750 # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE 23567500 # Time in different power states
+system.physmem_1.memoryStateTime::REF 91510000 # Time in different power states
+system.physmem_1.memoryStateTime::SREF 231519465750 # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 731339000 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 101377500 # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 1173834750 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups 45912950 # Number of BP lookups
+system.cpu.branchPred.condPredicted 26702746 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 565787 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 25186733 # Number of BTB lookups
+system.cpu.branchPred.BTBLookups 25186743 # Number of BTB lookups
system.cpu.branchPred.BTBHits 18811780 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 74.689242 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 74.689212 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 8285572 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 2249880 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectLookups 2249876 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 2235903 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 13977 # Number of indirect misses.
+system.cpu.branchPred.indirectMisses 13973 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 111495 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
@@ -275,17 +285,17 @@ system.cpu.dtb.read_misses 116 # DT
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 95338572 # DTB read accesses
system.cpu.dtb.write_hits 73578378 # DTB write hits
-system.cpu.dtb.write_misses 849 # DTB write misses
+system.cpu.dtb.write_misses 847 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 73579227 # DTB write accesses
+system.cpu.dtb.write_accesses 73579225 # DTB write accesses
system.cpu.dtb.data_hits 168916834 # DTB hits
-system.cpu.dtb.data_misses 965 # DTB misses
+system.cpu.dtb.data_misses 963 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 168917799 # DTB accesses
-system.cpu.itb.fetch_hits 96959232 # ITB hits
+system.cpu.dtb.data_accesses 168917797 # DTB accesses
+system.cpu.itb.fetch_hits 96959253 # ITB hits
system.cpu.itb.fetch_misses 1239 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 96960471 # ITB accesses
+system.cpu.itb.fetch_accesses 96960492 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -299,16 +309,16 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 233533887500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 467067775 # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON 233641094500 # Cumulative time (in ticks) in various power states
+system.cpu.numCycles 467282189 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 398664651 # Number of instructions committed
system.cpu.committedOps 398664651 # Number of ops (including micro ops) committed
system.cpu.discardedOps 2289293 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.171581 # CPI: cycles per instruction
-system.cpu.ipc 0.853548 # IPC: instructions per cycle
+system.cpu.cpi 1.172118 # CPI: cycles per instruction
+system.cpu.ipc 0.853156 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction
system.cpu.op_class_0::IntAlu 141652555 35.53% 41.33% # Class of committed instruction
system.cpu.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction
@@ -344,18 +354,18 @@ system.cpu.op_class_0::MemWrite 73520764 18.44% 100.00% # Cl
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 398664651 # Class of committed instruction
-system.cpu.tickCycles 455740572 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 11327203 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states
+system.cpu.tickCycles 455741730 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 11540459 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 771 # number of replacements
-system.cpu.dcache.tags.tagsinuse 3291.924590 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 167817024 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 3291.586193 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 167817015 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 40292.202641 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 40292.200480 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 3291.924590 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.803693 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.803693 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 3291.586193 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.803610 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.803610 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
@@ -363,41 +373,41 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 216
system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 3113 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 335652191 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 335652191 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 94302223 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 94302223 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 73514801 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 73514801 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 167817024 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 167817024 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 167817024 # number of overall hits
-system.cpu.dcache.overall_hits::total 167817024 # number of overall hits
+system.cpu.dcache.tags.tag_accesses 335652183 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 335652183 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data 94302219 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 94302219 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 73514796 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 73514796 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 167817015 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 167817015 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 167817015 # number of overall hits
+system.cpu.dcache.overall_hits::total 167817015 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1061 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1061 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 5928 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 5928 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 6989 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 6989 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 6989 # number of overall misses
-system.cpu.dcache.overall_misses::total 6989 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 80682500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 80682500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 434084500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 434084500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 514767000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 514767000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 514767000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 514767000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 94303284 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 94303284 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_misses::cpu.data 5933 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 5933 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 6994 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 6994 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 6994 # number of overall misses
+system.cpu.dcache.overall_misses::total 6994 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 94695000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 94695000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 540363000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 540363000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 635058000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 635058000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 635058000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 635058000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 94303280 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 94303280 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 167824013 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 167824013 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 167824013 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 167824013 # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 167824009 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 167824009 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 167824009 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 167824009 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000011 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000011 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses
@@ -406,14 +416,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000042
system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76043.826579 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 76043.826579 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73226.130229 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 73226.130229 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 73653.884676 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 73653.884676 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 73653.884676 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 73653.884676 # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 89250.706880 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 89250.706880 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 91077.532446 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 91077.532446 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 90800.400343 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 90800.400343 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 90800.400343 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 90800.400343 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -424,12 +434,12 @@ system.cpu.dcache.writebacks::writebacks 654 # nu
system.cpu.dcache.writebacks::total 654 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 92 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2732 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2732 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 2824 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 2824 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 2824 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 2824 # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2737 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2737 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 2829 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 2829 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 2829 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 2829 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses
@@ -438,14 +448,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4165
system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 72936500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 72936500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 242391000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 242391000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 315327500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 315327500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 315327500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 315327500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86354000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 86354000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 303749000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 303749000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 390103000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 390103000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 390103000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 390103000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses
@@ -454,139 +464,139 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75269.865841 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75269.865841 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75841.989987 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75841.989987 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75708.883553 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 75708.883553 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75708.883553 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 75708.883553 # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements 3193 # number of replacements
-system.cpu.icache.tags.tagsinuse 1919.733373 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 96954061 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 5171 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 18749.576678 # Average number of references to valid blocks.
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89116.615067 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89116.615067 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95040.362954 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95040.362954 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 93662.184874 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 93662.184874 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 93662.184874 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 93662.184874 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements 3194 # number of replacements
+system.cpu.icache.tags.tagsinuse 1919.615846 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 96954081 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 5172 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 18745.955336 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1919.733373 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.937370 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.937370 # Average percentage of cache occupancy
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+system.cpu.icache.tags.occ_percent::total 0.937312 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1287 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 193923635 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 193923635 # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst 96954061 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 96954061 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 96954061 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 96954061 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 96954061 # number of overall hits
-system.cpu.icache.overall_hits::total 96954061 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 5171 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 5171 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 5171 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 5171 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 5171 # number of overall misses
-system.cpu.icache.overall_misses::total 5171 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 321948500 # number of ReadReq miss cycles
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+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89018.613607 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89018.613607 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99184.304400 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 99184.304400 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89018.613607 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95991.704374 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 92541.915407 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89018.613607 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95991.704374 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 92541.915407 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -669,79 +679,79 @@ system.cpu.l2cache.demand_mshr_misses::total 7873
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3895 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 3978 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 7873 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 205701000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 205701000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 256671500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 256671500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 61598000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 61598000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 256671500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 267299000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 523970500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 256671500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 267299000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 523970500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 267071000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 267071000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 307777500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 307777500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 75004000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 75004000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 307777500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 342075000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 649852500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 307777500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 342075000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 649852500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.753239 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.753239 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.753094 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.753094 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.869700 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.753239 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.753094 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.843295 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.753239 # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.843204 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.753094 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.843295 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65572.521517 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65572.521517 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65897.689345 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65897.689345 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73243.757432 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73243.757432 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65897.689345 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67194.318753 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66552.838816 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65897.689345 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67194.318753 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66552.838816 # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 13300 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 3964 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.843204 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85135.798534 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85135.798534 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79018.613607 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79018.613607 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89184.304400 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 89184.304400 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79018.613607 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85991.704374 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 82541.915407 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79018.613607 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85991.704374 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82541.915407 # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests 13302 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 3965 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 6138 # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp 6139 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 654 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 3193 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 3194 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 117 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 5171 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 5172 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 967 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13535 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13538 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9101 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 22636 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 535296 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 22639 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 535424 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 843712 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 843840 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 9336 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 9337 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 9336 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 9337 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 9336 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 10497000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 9337 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 10499000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 7756500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 7758000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 6247500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
@@ -751,7 +761,7 @@ system.membus.snoop_filter.hit_multi_requests 0
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 4736 # Transaction distribution
system.membus.trans_dist::ReadExReq 3137 # Transaction distribution
system.membus.trans_dist::ReadExResp 3137 # Transaction distribution
@@ -772,9 +782,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 7873 # Request fanout histogram
-system.membus.reqLayer0.occupancy 9223000 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 9215000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 41799750 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 41791500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
index e7c466732..c2a5884c8 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -173,7 +173,7 @@ useIndirect=true
[system.cpu.dcache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
@@ -531,7 +531,7 @@ pipelined=false
[system.cpu.icache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
@@ -591,7 +591,7 @@ size=48
[system.cpu.l2cache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
@@ -708,6 +708,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -719,7 +720,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -727,29 +728,36 @@ width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
[system.physmem]
type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
@@ -769,6 +777,7 @@ devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
+kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
@@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
@@ -800,9 +809,9 @@ tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
-tXP=0
+tXP=6000
tXPDLL=0
-tXS=0
+tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
index 02658fe82..ee5bfc401 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 21 2016 14:09:28
-gem5 executing on e108600-lin, pid 4299
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:44
+gem5 executing on e108600-lin, pid 28057
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
@@ -14,4 +14,4 @@ info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.050000
-Exiting @ tick 64188759000 because target called exit()
+Exiting @ tick 64255452000 because target called exit()
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index 71e9e3432..1a8043b05 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,35 +1,35 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.064159 # Number of seconds simulated
-sim_ticks 64159445000 # Number of ticks simulated
-final_tick 64159445000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.064255 # Number of seconds simulated
+sim_ticks 64255452000 # Number of ticks simulated
+final_tick 64255452000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 223776 # Simulator instruction rate (inst/s)
-host_op_rate 223776 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 38227708 # Simulator tick rate (ticks/s)
-host_mem_usage 261380 # Number of bytes of host memory used
-host_seconds 1678.35 # Real time elapsed on the host
+host_inst_rate 260947 # Simulator instruction rate (inst/s)
+host_op_rate 260947 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 44644346 # Simulator tick rate (ticks/s)
+host_mem_usage 259540 # Number of bytes of host memory used
+host_seconds 1439.27 # Real time elapsed on the host
sim_insts 375574794 # Number of instructions simulated
sim_ops 375574794 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 220736 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 255360 # Number of bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 255296 # Number of bytes read from this memory
system.physmem.bytes_read::total 476096 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 220736 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 220736 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 3449 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 3990 # Number of read requests responded to by this memory
+system.physmem.bytes_inst_read::cpu.inst 220800 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 220800 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 3450 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 3989 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7439 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 3440429 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3980084 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 7420513 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 3440429 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 3440429 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 3440429 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3980084 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 7420513 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 3436284 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3973141 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 7409426 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 3436284 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 3436284 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 3436284 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3973141 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 7409426 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 7439 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 7439 # Number of DRAM read bursts, including those serviced by the write queue
@@ -43,20 +43,20 @@ system.physmem.servicedByWrQ 0 # Nu
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 524 # Per bank write bursts
-system.physmem.perBankRdBursts::1 652 # Per bank write bursts
+system.physmem.perBankRdBursts::1 651 # Per bank write bursts
system.physmem.perBankRdBursts::2 450 # Per bank write bursts
system.physmem.perBankRdBursts::3 600 # Per bank write bursts
system.physmem.perBankRdBursts::4 446 # Per bank write bursts
system.physmem.perBankRdBursts::5 454 # Per bank write bursts
system.physmem.perBankRdBursts::6 513 # Per bank write bursts
-system.physmem.perBankRdBursts::7 523 # Per bank write bursts
+system.physmem.perBankRdBursts::7 524 # Per bank write bursts
system.physmem.perBankRdBursts::8 438 # Per bank write bursts
system.physmem.perBankRdBursts::9 408 # Per bank write bursts
system.physmem.perBankRdBursts::10 339 # Per bank write bursts
-system.physmem.perBankRdBursts::11 305 # Per bank write bursts
+system.physmem.perBankRdBursts::11 306 # Per bank write bursts
system.physmem.perBankRdBursts::12 414 # Per bank write bursts
system.physmem.perBankRdBursts::13 540 # Per bank write bursts
-system.physmem.perBankRdBursts::14 453 # Per bank write bursts
+system.physmem.perBankRdBursts::14 452 # Per bank write bursts
system.physmem.perBankRdBursts::15 380 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
@@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 64159334500 # Total gap between requests
+system.physmem.totGap 64255349500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
@@ -91,11 +91,11 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 4271 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 1861 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 920 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 327 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 3982 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 2008 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 898 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 438 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 111 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
@@ -188,28 +188,28 @@ system.physmem.wrQLenPdf::61 0 # Wh
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1349 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 352.640474 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 209.024877 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 349.175025 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 440 32.62% 32.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 302 22.39% 55.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 154 11.42% 66.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 83 6.15% 72.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 53 3.93% 76.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 50 3.71% 80.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 36 2.67% 82.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 35 2.59% 85.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 351.644181 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 209.715239 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 347.080632 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 429 31.80% 31.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 311 23.05% 54.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 151 11.19% 66.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 87 6.45% 72.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 68 5.04% 77.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 39 2.89% 80.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 38 2.82% 83.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 30 2.22% 85.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 196 14.53% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1349 # Bytes accessed per row activation
-system.physmem.totQLat 63577500 # Total ticks spent queuing
-system.physmem.totMemAccLat 203058750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 165053250 # Total ticks spent queuing
+system.physmem.totMemAccLat 304534500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 37195000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 8546.51 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 22187.56 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 27296.51 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 7.42 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 40937.56 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 7.41 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 7.42 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 7.41 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.06 # Data bus utilization in percentage
@@ -217,75 +217,85 @@ system.physmem.busUtilRead 0.06 # Da
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 6088 # Number of row buffer hits during reads
+system.physmem.readRowHits 6085 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.84 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 81.80 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 8624725.70 # Average gap between requests
-system.physmem.pageHitRate 81.84 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 5821200 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 3176250 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 32416800 # Energy for read commands per rank (pJ)
+system.physmem.avgGap 8637632.68 # Average gap between requests
+system.physmem.pageHitRate 81.80 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 5454960 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 2880405 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 29716680 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 4190534400 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1995176700 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 36745221000 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 42972346350 # Total energy per rank (pJ)
-system.physmem_0.averagePower 669.779347 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 61126318750 # Time in different power states
-system.physmem_0.memoryStateTime::REF 2142400000 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 890255000 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 4377240 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 2388375 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 25560600 # Energy for read commands per rank (pJ)
+system.physmem_0.refreshEnergy 128459760.000000 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 63558420 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 5463840 # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy 397888500 # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy 152192640 # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy 15095921460 # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy 15881536665 # Total energy per rank (pJ)
+system.physmem_0.averagePower 247.162475 # Core power per rank (mW)
+system.physmem_0.totalIdleTime 64101767750 # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE 8572500 # Time in different power states
+system.physmem_0.memoryStateTime::REF 54520000 # Time in different power states
+system.physmem_0.memoryStateTime::SREF 62832935750 # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 396328750 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 90536500 # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 872558500 # Time in different power states
+system.physmem_1.actEnergy 4212600 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 2239050 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 23397780 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 4190534400 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1859740425 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 36864024750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 42946625790 # Total energy per rank (pJ)
-system.physmem_1.averagePower 669.378459 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 61324552000 # Time in different power states
-system.physmem_1.memoryStateTime::REF 2142400000 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 692021750 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 47856205 # Number of BP lookups
-system.cpu.branchPred.condPredicted 27886274 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 572784 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 23348714 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 19574502 # Number of BTB hits
+system.physmem_1.refreshEnergy 172713840.000000 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 67790100 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 10409760 # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy 394655460 # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy 234464640 # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy 15065735460 # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy 15975618690 # Total energy per rank (pJ)
+system.physmem_1.averagePower 248.626662 # Core power per rank (mW)
+system.physmem_1.totalIdleTime 64079571000 # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE 20607500 # Time in different power states
+system.physmem_1.memoryStateTime::REF 73504000 # Time in different power states
+system.physmem_1.memoryStateTime::SREF 62603628000 # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 610590500 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 81643000 # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 865479000 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups 47858833 # Number of BP lookups
+system.cpu.branchPred.condPredicted 27887840 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 573531 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 23350857 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 19575248 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 83.835461 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 8687459 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 1418 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 2338624 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 2308001 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 30623 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 111239 # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct 83.830962 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 8687752 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1405 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 2338807 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 2307668 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 31139 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 111329 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 98829712 # DTB read hits
-system.cpu.dtb.read_misses 28367 # DTB read misses
-system.cpu.dtb.read_acv 845 # DTB read access violations
-system.cpu.dtb.read_accesses 98858079 # DTB read accesses
-system.cpu.dtb.write_hits 75499203 # DTB write hits
-system.cpu.dtb.write_misses 1454 # DTB write misses
+system.cpu.dtb.read_hits 98831063 # DTB read hits
+system.cpu.dtb.read_misses 28342 # DTB read misses
+system.cpu.dtb.read_acv 849 # DTB read access violations
+system.cpu.dtb.read_accesses 98859405 # DTB read accesses
+system.cpu.dtb.write_hits 75501441 # DTB write hits
+system.cpu.dtb.write_misses 1449 # DTB write misses
system.cpu.dtb.write_acv 3 # DTB write access violations
-system.cpu.dtb.write_accesses 75500657 # DTB write accesses
-system.cpu.dtb.data_hits 174328915 # DTB hits
-system.cpu.dtb.data_misses 29821 # DTB misses
-system.cpu.dtb.data_acv 848 # DTB access violations
-system.cpu.dtb.data_accesses 174358736 # DTB accesses
-system.cpu.itb.fetch_hits 46955913 # ITB hits
-system.cpu.itb.fetch_misses 420 # ITB misses
-system.cpu.itb.fetch_acv 7 # ITB acv
-system.cpu.itb.fetch_accesses 46956333 # ITB accesses
+system.cpu.dtb.write_accesses 75502890 # DTB write accesses
+system.cpu.dtb.data_hits 174332504 # DTB hits
+system.cpu.dtb.data_misses 29791 # DTB misses
+system.cpu.dtb.data_acv 852 # DTB access violations
+system.cpu.dtb.data_accesses 174362295 # DTB accesses
+system.cpu.itb.fetch_hits 46958874 # ITB hits
+system.cpu.itb.fetch_misses 432 # ITB misses
+system.cpu.itb.fetch_acv 5 # ITB acv
+system.cpu.itb.fetch_accesses 46959306 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -299,141 +309,141 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 64159445000 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 128318893 # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON 64255452000 # Cumulative time (in ticks) in various power states
+system.cpu.numCycles 128510907 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 47425719 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 424811206 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 47856205 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 30569962 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 79950349 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1246202 # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles 47429437 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 424837073 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 47858833 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 30570668 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 80085665 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1247776 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 13 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 270 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 13187 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 60 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 46955913 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 225768 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 128012699 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 3.318508 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.349839 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.MiscStallCycles 297 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 13295 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 79 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 46958874 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 226146 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 128152674 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 3.315086 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.349633 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 53041219 41.43% 41.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 4325218 3.38% 44.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 6711253 5.24% 50.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 5104898 3.99% 54.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 10968142 8.57% 62.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 7524114 5.88% 68.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 5300788 4.14% 72.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1845614 1.44% 74.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 33191453 25.93% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 53168247 41.49% 41.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 4330315 3.38% 44.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 6713619 5.24% 50.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 5107106 3.99% 54.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 10970093 8.56% 62.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 7524949 5.87% 68.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 5303300 4.14% 72.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1847075 1.44% 74.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 33187970 25.90% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 128012699 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.372947 # Number of branch fetches per cycle
-system.cpu.fetch.rate 3.310590 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 42125446 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 13481218 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 67948873 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3838220 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 618942 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 8882912 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 4201 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 421902807 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 13825 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 618942 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 43678343 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 3058028 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 517106 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 70134710 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 10005570 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 419884966 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 437260 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 2526892 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 2765017 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 3520699 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 273968908 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 552151473 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 393698766 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 158452706 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 128152674 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.372411 # Number of branch fetches per cycle
+system.cpu.fetch.rate 3.305844 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 42097840 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 13659925 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 67904561 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 3870622 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 619726 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 8883416 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 4205 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 421920314 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 13831 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 619726 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 43662514 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 3075430 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 529984 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 70109441 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 10155579 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 419899923 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 443686 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 2538434 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 2849903 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 3565226 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 273976095 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 552171720 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 393714640 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 158457079 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 259532319 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 14436589 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 37562 # count of serializing insts renamed
+system.cpu.rename.UndoneMaps 14443776 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 37564 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 298 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 15635470 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 99735139 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 76519296 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 11859955 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 9294086 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 392181792 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.skidInsts 15805009 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 99734698 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 76520876 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 11857010 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 9264279 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 392184083 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 290 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 389203558 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 195886 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 16607287 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 7664931 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 389210637 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 196187 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 16609578 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 7664570 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 75 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 128012699 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 3.040351 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.180919 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 128152674 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 3.037086 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.181467 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 17224377 13.46% 13.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 19358192 15.12% 28.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 22001472 17.19% 45.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 17955910 14.03% 59.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 19066405 14.89% 74.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 13282652 10.38% 85.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 8794829 6.87% 91.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 6104058 4.77% 96.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 4224804 3.30% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 17313559 13.51% 13.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 19411245 15.15% 28.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 22012922 17.18% 45.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 17948678 14.01% 59.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 19074074 14.88% 74.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 13271943 10.36% 85.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 8797733 6.87% 91.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 6095055 4.76% 96.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 4227465 3.30% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 128012699 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 128152674 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 256922 1.42% 1.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 2 0.00% 1.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 1.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 138470 0.76% 2.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 78848 0.44% 2.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 3339 0.02% 2.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 3443164 19.01% 21.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 1648895 9.10% 30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 30.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8039924 44.38% 75.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 4505956 24.87% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 253970 1.40% 1.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 2 0.00% 1.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 1.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 138834 0.77% 2.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 79013 0.44% 2.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 3594 0.02% 2.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 3443745 19.00% 21.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 1647907 9.09% 30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 30.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8047413 44.40% 75.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 4509145 24.88% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 146986421 37.77% 37.77% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 2128250 0.55% 38.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 146989472 37.77% 37.77% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 2128309 0.55% 38.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 36418938 9.36% 47.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 7355017 1.89% 49.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 2800646 0.72% 50.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 16556809 4.25% 54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 1584153 0.41% 54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 36418443 9.36% 47.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 7355119 1.89% 49.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 2800065 0.72% 50.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 16556449 4.25% 54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 1584163 0.41% 54.95% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.95% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.95% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.95% # Type of FU issued
@@ -455,82 +465,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.95% # Ty
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.95% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.95% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.95% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 99502900 25.57% 80.51% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 75836843 19.49% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 99502948 25.57% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 75842088 19.49% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 389203558 # Type of FU issued
-system.cpu.iq.rate 3.033096 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 18115520 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.046545 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 592493180 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 242176639 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 227925873 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 332238041 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 166682962 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 158291544 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 234723560 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 172561937 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 19352464 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 389210637 # Type of FU issued
+system.cpu.iq.rate 3.028619 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 18123623 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.046565 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 592644502 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 242185048 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 227933309 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 332249256 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 166679024 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 158288157 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 234729597 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 172571082 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 19364531 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 4980653 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 92349 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 70589 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 2998568 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 4980212 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 92962 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 70485 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 3000148 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 383293 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 3853 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 382479 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 3666 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 618942 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1854909 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 149633 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 415904338 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 108226 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 99735139 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 76519296 # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles 619726 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1854972 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 162334 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 415907776 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 109026 # Number of squashed instructions skipped by dispatch
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system.cpu.iew.iewDispNonSpecInsts 290 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 7462 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 141873 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 70589 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 411438 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 230495 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 641933 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 387616397 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 98858950 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1587161 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewIQFullEvents 8920 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 152322 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 70485 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 412161 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 230865 # Number of branches that were predicted not taken incorrectly
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system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 23722256 # number of nop insts executed
-system.cpu.iew.exec_refs 174359643 # number of memory reference insts executed
-system.cpu.iew.exec_branches 45862472 # Number of branches executed
-system.cpu.iew.exec_stores 75500693 # Number of stores executed
-system.cpu.iew.exec_rate 3.020727 # Inst execution rate
-system.cpu.iew.wb_sent 386480663 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 386217417 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 192328787 # num instructions producing a value
-system.cpu.iew.wb_consumers 273868663 # num instructions consuming a value
-system.cpu.iew.wb_rate 3.009825 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.702266 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 17240745 # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop 23723403 # number of nop insts executed
+system.cpu.iew.exec_refs 174363211 # number of memory reference insts executed
+system.cpu.iew.exec_branches 45864022 # Number of branches executed
+system.cpu.iew.exec_stores 75502928 # Number of stores executed
+system.cpu.iew.exec_rate 3.016276 # Inst execution rate
+system.cpu.iew.wb_sent 386484413 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 386221466 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 192314001 # num instructions producing a value
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+system.cpu.iew.wb_rate 3.005359 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.702255 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 17244606 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 568625 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 125549188 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 3.175366 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 3.248155 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 569369 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 125687681 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 3.171867 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 3.248348 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 42020703 33.47% 33.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 17522364 13.96% 47.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 8729636 6.95% 54.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 9062074 7.22% 61.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 6240745 4.97% 66.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 4112376 3.28% 69.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 4753795 3.79% 73.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 2410879 1.92% 75.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 30696616 24.45% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 42136978 33.53% 33.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 17569311 13.98% 47.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 8725420 6.94% 54.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 9050963 7.20% 61.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 6228783 4.96% 66.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 4113989 3.27% 69.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 4743327 3.77% 73.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 2404790 1.91% 75.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 30714120 24.44% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 125549188 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 125687681 # Number of insts commited each cycle
system.cpu.commit.committedInsts 398664569 # Number of instructions committed
system.cpu.commit.committedOps 398664569 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -576,33 +586,33 @@ system.cpu.commit.op_class_0::MemWrite 73520728 18.44% 100.00% # Cl
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 398664569 # Class of committed instruction
-system.cpu.commit.bw_lim_events 30696616 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 510754909 # The number of ROB reads
-system.cpu.rob.rob_writes 834280363 # The number of ROB writes
-system.cpu.timesIdled 3150 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 306194 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events 30714120 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 510879759 # The number of ROB reads
+system.cpu.rob.rob_writes 834289662 # The number of ROB writes
+system.cpu.timesIdled 3136 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 358233 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 375574794 # Number of Instructions Simulated
system.cpu.committedOps 375574794 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.341660 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.341660 # CPI: Total CPI of All Threads
-system.cpu.ipc 2.926886 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 2.926886 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 385442521 # number of integer regfile reads
-system.cpu.int_regfile_writes 165246956 # number of integer regfile writes
-system.cpu.fp_regfile_reads 154535424 # number of floating regfile reads
-system.cpu.fp_regfile_writes 102076666 # number of floating regfile writes
+system.cpu.cpi 0.342171 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.342171 # CPI: Total CPI of All Threads
+system.cpu.ipc 2.922513 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 2.922513 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 385452576 # number of integer regfile reads
+system.cpu.int_regfile_writes 165252743 # number of integer regfile writes
+system.cpu.fp_regfile_reads 154537274 # number of floating regfile reads
+system.cpu.fp_regfile_writes 102070951 # number of floating regfile writes
system.cpu.misc_regfile_reads 350572 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 779 # number of replacements
-system.cpu.dcache.tags.tagsinuse 3291.925722 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 152589979 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 4179 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 36513.514956 # Average number of references to valid blocks.
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements 774 # number of replacements
+system.cpu.dcache.tags.tagsinuse 3291.451205 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 152580730 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 4174 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 36555.038333 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 3291.925722 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.803693 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.803693 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 3291.451205 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.803577 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.803577 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 3400 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
@@ -610,304 +620,304 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 211
system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.830078 # Percentage of cache occupancy per task id
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-system.cpu.dcache.tags.data_accesses 305227185 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 79088959 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 79088959 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 73501014 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 73501014 # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses 305207642 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 305207642 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states
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system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data 152589973 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 152589973 # number of demand (read+write) hits
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system.cpu.dcache.ReadReq_misses::cpu.data 1810 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1810 # number of ReadReq misses
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-system.cpu.dcache.demand_misses::total 21524 # number of demand (read+write) misses
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-system.cpu.dcache.overall_misses::total 21524 # number of overall misses
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-system.cpu.dcache.ReadReq_miss_latency::total 128203000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_accesses::cpu.data 73520728 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 73520728 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses
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-system.cpu.dcache.overall_miss_rate::total 0.000141 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70830.386740 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 70830.386740 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60596.654915 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 60596.654915 # average WriteReq miss latency
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-system.cpu.dcache.demand_avg_miss_latency::total 61457.231695 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 61457.231695 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 61457.231695 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 49869 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 82 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 741 # number of cycles access was blocked
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000261 # miss rate for WriteReq accesses
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+system.cpu.dcache.demand_avg_miss_latency::total 69954.151733 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 69954.151733 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 69954.151733 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 57813 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 94 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 689 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 67.299595 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 82 # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks 658 # number of writebacks
-system.cpu.dcache.writebacks::total 658 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 821 # number of ReadReq MSHR hits
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+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 72017500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 276069500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 335209500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 611279000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 276069500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 335209500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 611279000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981179 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981179 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.849963 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.849963 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.873225 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.873225 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.849963 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955678 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.903559 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.849963 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955678 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.903559 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84140.664962 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84140.664962 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 80020.144928 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 80020.144928 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83644.018583 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 83644.018583 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 80020.144928 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84033.467034 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 82172.200565 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 80020.144928 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84033.467034 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82172.200565 # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests 11139 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 2906 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 5047 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 658 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 2131 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 121 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 3190 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 3190 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 4058 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 989 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10247 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9137 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 19384 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 396096 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309568 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 705664 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp 5045 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty 655 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 2132 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 119 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 3188 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 3188 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 4059 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 986 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10250 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9122 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 19372 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 396224 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309056 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 705280 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 8237 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 8233 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 8237 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 8233 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 8237 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 8362500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 8233 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 8356500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 6087499 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 6088500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 6268500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 6261000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 7439 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
@@ -1008,7 +1018,7 @@ system.membus.snoop_filter.hit_multi_requests 0
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 4311 # Transaction distribution
system.membus.trans_dist::ReadExReq 3128 # Transaction distribution
system.membus.trans_dist::ReadExResp 3128 # Transaction distribution
@@ -1029,9 +1039,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 7439 # Request fanout histogram
-system.membus.reqLayer0.occupancy 9245500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 9229500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 39234750 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 39165500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------