diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/long/se/30.eon/ref/alpha | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/long/se/30.eon/ref/alpha')
12 files changed, 834 insertions, 563 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini index 16e4d1756..2ad80ff6d 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -45,6 +52,7 @@ div32RepeatRate=1 div8Latency=1 div8RepeatRate=1 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 @@ -57,6 +65,7 @@ globalCtrBits=2 globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 +interrupts=system.cpu.interrupts itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -72,6 +81,7 @@ multRepeatRate=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 stageTracing=false stageWidth=4 @@ -93,20 +103,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -129,20 +132,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -150,6 +146,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -165,20 +164,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -202,7 +194,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing egid=100 env= errout=cerr diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout index 1c2a18294..b600ef537 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:24:12 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:10:43 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index a04efd18a..58ea20ddf 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.139995 # Nu sim_ticks 139995113500 # Number of ticks simulated final_tick 139995113500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 118986 # Simulator instruction rate (inst/s) -host_tick_rate 41783300 # Simulator tick rate (ticks/s) -host_mem_usage 214012 # Number of bytes of host memory used -host_seconds 3350.50 # Real time elapsed on the host +host_inst_rate 154307 # Simulator instruction rate (inst/s) +host_op_rate 154307 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54186341 # Simulator tick rate (ticks/s) +host_mem_usage 215920 # Number of bytes of host memory used +host_seconds 2583.59 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated +sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read 469184 # Number of bytes read from this memory system.physmem.bytes_inst_read 214784 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -68,9 +70,10 @@ system.cpu.comNops 23089775 # Nu system.cpu.comNonSpec 215 # Number of Non-Speculative instructions committed system.cpu.comInts 112239074 # Number of Integer instructions committed system.cpu.comFloats 50439198 # Number of Floating Point instructions committed -system.cpu.committedInsts 398664595 # Number of Instructions Simulated (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 398664595 # Number of Instructions Simulated (Total) +system.cpu.committedInsts 398664595 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) +system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) system.cpu.cpi 0.702320 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.cpi_total 0.702320 # CPI: Total CPI of All Threads @@ -124,26 +127,39 @@ system.cpu.icache.total_refs 48855472 # To system.cpu.icache.sampled_refs 3897 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 12536.687708 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1829.847469 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.893480 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 48855472 # number of ReadReq hits -system.cpu.icache.demand_hits 48855472 # number of demand (read+write) hits -system.cpu.icache.overall_hits 48855472 # number of overall hits -system.cpu.icache.ReadReq_misses 4376 # number of ReadReq misses -system.cpu.icache.demand_misses 4376 # number of demand (read+write) misses -system.cpu.icache.overall_misses 4376 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 214318500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 214318500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 214318500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 48859848 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 48859848 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 48859848 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000090 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000090 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000090 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 48975.891225 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 48975.891225 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 48975.891225 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1829.847469 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.893480 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.893480 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 48855472 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 48855472 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 48855472 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 48855472 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 48855472 # number of overall hits +system.cpu.icache.overall_hits::total 48855472 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4376 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4376 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4376 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4376 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4376 # number of overall misses +system.cpu.icache.overall_misses::total 4376 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 214318500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 214318500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 214318500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 214318500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 214318500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 214318500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 48859848 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 48859848 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 48859848 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 48859848 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 48859848 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 48859848 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000090 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000090 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000090 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48975.891225 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48975.891225 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48975.891225 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 45000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -152,27 +168,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets 45000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 479 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 479 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 479 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 3897 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 3897 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 3897 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 185285000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 185285000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 185285000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000080 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000080 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 47545.547857 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 47545.547857 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 47545.547857 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 479 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 479 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 479 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 479 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 479 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 479 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3897 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 3897 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 3897 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 3897 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 3897 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 3897 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 185285000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 185285000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 185285000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 185285000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 185285000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 185285000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47545.547857 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47545.547857 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47545.547857 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.tagsinuse 3284.892021 # Cycle average of tags in use @@ -180,32 +199,49 @@ system.cpu.dcache.total_refs 168261959 # To system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 40525.519990 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3284.892021 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.801976 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 94753265 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 73508694 # number of WriteReq hits -system.cpu.dcache.demand_hits 168261959 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 168261959 # number of overall hits -system.cpu.dcache.ReadReq_misses 1224 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 12035 # number of WriteReq misses -system.cpu.dcache.demand_misses 13259 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 13259 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 63830500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 626731500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 690562000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 690562000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 94754489 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 168275218 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 168275218 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000164 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000079 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000079 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 52149.101307 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 52075.737432 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 52082.509993 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 52082.509993 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 3284.892021 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.801976 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.801976 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 94753265 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94753265 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73508694 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73508694 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168261959 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168261959 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168261959 # number of overall hits +system.cpu.dcache.overall_hits::total 168261959 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1224 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1224 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 12035 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 12035 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 13259 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 13259 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 13259 # number of overall misses +system.cpu.dcache.overall_misses::total 13259 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 63830500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 63830500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 626731500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 626731500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 690562000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 690562000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 690562000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 690562000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 168275218 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168275218 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168275218 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000013 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000164 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000079 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000079 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52149.101307 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52075.737432 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52082.509993 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52082.509993 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 82468500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -214,32 +250,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 44625.811688 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 649 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 274 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 8833 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 9107 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 9107 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 46185000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 169537500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 215722500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 215722500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48615.789474 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52947.376640 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 51956.286127 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 51956.286127 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 649 # number of writebacks +system.cpu.dcache.writebacks::total 649 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 274 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 274 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8833 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 8833 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 9107 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 9107 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 9107 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 9107 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 46185000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 46185000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 169537500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 169537500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215722500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 215722500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215722500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 215722500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48615.789474 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52947.376640 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51956.286127 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51956.286127 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 13 # number of replacements system.cpu.l2cache.tagsinuse 3900.004949 # Cycle average of tags in use @@ -247,36 +291,75 @@ system.cpu.l2cache.total_refs 729 # To system.cpu.l2cache.sampled_refs 4720 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.154449 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3529.472340 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 370.532609 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.107711 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.011308 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 658 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 649 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 60 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 718 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 718 # number of overall hits -system.cpu.l2cache.ReadReq_misses 4186 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 3145 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 7331 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 7331 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 219209500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 164966000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 384175500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 384175500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 4844 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 649 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 3205 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 8049 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 8049 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.864162 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.981279 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.910796 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.910796 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52367.295748 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52453.418124 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52404.242259 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52404.242259 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 370.532609 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2905.642885 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 623.829454 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.088673 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019038 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.119019 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 541 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 117 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 658 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 541 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 177 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 718 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 541 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 177 # number of overall hits +system.cpu.l2cache.overall_hits::total 718 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3356 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 830 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4186 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 3145 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 3145 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3356 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3975 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7331 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3356 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3975 # number of overall misses +system.cpu.l2cache.overall_misses::total 7331 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 175581500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43628000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 219209500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 164966000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 164966000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 175581500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 208594000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 384175500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 175581500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 208594000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 384175500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 3897 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 4844 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 3205 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 3205 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 3897 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8049 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 3897 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 8049 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.861175 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.876452 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981279 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.861175 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.957370 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.861175 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.957370 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.682956 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52563.855422 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52453.418124 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.682956 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52476.477987 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.682956 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52476.477987 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -285,30 +368,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 4186 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 3145 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 7331 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 7331 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 168226500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 126764000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 294990500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 294990500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.864162 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.981279 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.910796 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.910796 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40187.888199 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40306.518283 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40238.780521 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40238.780521 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3356 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 830 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4186 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3145 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3145 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3356 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3975 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7331 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3356 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3975 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7331 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134709500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33517000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 168226500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126764000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126764000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134709500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160281000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 294990500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134709500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160281000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 294990500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.861175 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876452 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.861175 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.861175 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40139.898689 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40381.927711 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40306.518283 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40139.898689 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40322.264151 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40139.898689 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40322.264151 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini index 0fce2844b..c359a496a 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -80,6 +89,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -88,6 +98,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -125,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -424,20 +428,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -445,6 +442,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -460,20 +460,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -497,7 +490,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout index 137fd0ee8..d3938f090 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:24:12 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:10:45 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 28785f469..e5ff3033e 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.089480 # Nu sim_ticks 89480174500 # Number of ticks simulated final_tick 89480174500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 190161 # Simulator instruction rate (inst/s) -host_tick_rate 45305657 # Simulator tick rate (ticks/s) -host_mem_usage 214676 # Number of bytes of host memory used -host_seconds 1975.03 # Real time elapsed on the host +host_inst_rate 246728 # Simulator instruction rate (inst/s) +host_op_rate 246728 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58782597 # Simulator tick rate (ticks/s) +host_mem_usage 216860 # Number of bytes of host memory used +host_seconds 1522.22 # Real time elapsed on the host sim_insts 375574794 # Number of instructions simulated +sim_ops 375574794 # Number of ops (including micro ops) simulated system.physmem.bytes_read 475840 # Number of bytes read from this memory system.physmem.bytes_inst_read 219968 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -271,6 +273,7 @@ system.cpu.iew.wb_rate 2.269707 # in system.cpu.iew.wb_fanout 0.713332 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 398664569 # The number of committed instructions +system.cpu.commit.commitCommittedOps 398664569 # The number of committed instructions system.cpu.commit.commitSquashedInsts 60016815 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 3547729 # The number of times a branch was mispredicted @@ -291,7 +294,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 169731918 # Number of insts commited each cycle -system.cpu.commit.count 398664569 # Number of instructions committed +system.cpu.commit.committedInsts 398664569 # Number of instructions committed +system.cpu.commit.committedOps 398664569 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 168275214 # Number of memory references committed system.cpu.commit.loads 94754486 # Number of loads committed @@ -307,6 +311,7 @@ system.cpu.rob.rob_writes 926487800 # Th system.cpu.timesIdled 2712 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 121803 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574794 # Number of Instructions Simulated +system.cpu.committedOps 375574794 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574794 # Number of Instructions Simulated system.cpu.cpi 0.476497 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.476497 # CPI: Total CPI of All Threads @@ -324,26 +329,39 @@ system.cpu.icache.total_refs 57898804 # To system.cpu.icache.sampled_refs 4037 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 14342.037156 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1834.326922 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.895667 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 57898804 # number of ReadReq hits -system.cpu.icache.demand_hits 57898804 # number of demand (read+write) hits -system.cpu.icache.overall_hits 57898804 # number of overall hits -system.cpu.icache.ReadReq_misses 5282 # number of ReadReq misses -system.cpu.icache.demand_misses 5282 # number of demand (read+write) misses -system.cpu.icache.overall_misses 5282 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 167914000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 167914000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 167914000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 57904086 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 57904086 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 57904086 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000091 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000091 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000091 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 31789.852329 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 31789.852329 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 31789.852329 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1834.326922 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.895667 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.895667 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 57898804 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 57898804 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 57898804 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 57898804 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 57898804 # number of overall hits +system.cpu.icache.overall_hits::total 57898804 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5282 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5282 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5282 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5282 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5282 # number of overall misses +system.cpu.icache.overall_misses::total 5282 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 167914000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 167914000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 167914000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 167914000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 167914000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 167914000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 57904086 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 57904086 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 57904086 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 57904086 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 57904086 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 57904086 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000091 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000091 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000091 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31789.852329 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 31789.852329 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 31789.852329 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -352,27 +370,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1245 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1245 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1245 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 4037 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 4037 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 4037 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 123459000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 123459000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 123459000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000070 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000070 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000070 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 30581.867724 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 30581.867724 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 30581.867724 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1245 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1245 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1245 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1245 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1245 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1245 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4037 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4037 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4037 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4037 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4037 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4037 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 123459000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 123459000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 123459000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 123459000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 123459000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 123459000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000070 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000070 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000070 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30581.867724 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30581.867724 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30581.867724 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 793 # number of replacements system.cpu.dcache.tagsinuse 3296.196945 # Cycle average of tags in use @@ -380,34 +401,53 @@ system.cpu.dcache.total_refs 164730953 # To system.cpu.dcache.sampled_refs 4193 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 39287.134033 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3296.196945 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.804736 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 91229707 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 73501239 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 164730946 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 164730946 # number of overall hits -system.cpu.dcache.ReadReq_misses 1678 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 19489 # number of WriteReq misses -system.cpu.dcache.demand_misses 21167 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 21167 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 55919500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 568883000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 624802500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 624802500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 91231385 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 73520728 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 164752113 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 164752113 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000265 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000128 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000128 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 33325.089392 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 29189.953307 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 29517.763500 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 29517.763500 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 3296.196945 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.804736 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.804736 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 91229707 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 91229707 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501239 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501239 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 7 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 7 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 164730946 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 164730946 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 164730946 # number of overall hits +system.cpu.dcache.overall_hits::total 164730946 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1678 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1678 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19489 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19489 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21167 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21167 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21167 # number of overall misses +system.cpu.dcache.overall_misses::total 21167 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 55919500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 55919500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 568883000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 568883000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 624802500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 624802500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 624802500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 624802500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 91231385 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 91231385 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 73520728 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 73520728 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 7 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 7 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 164752113 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 164752113 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 164752113 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 164752113 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000018 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000265 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000128 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000128 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33325.089392 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29189.953307 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29517.763500 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29517.763500 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 13000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -416,32 +456,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 2600 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 671 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 680 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 16294 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 16974 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 16974 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 998 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 3195 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 4193 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 4193 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 31703500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 113133500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 144837000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 144837000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000011 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31767.034068 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35409.546166 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34542.570952 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34542.570952 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 671 # number of writebacks +system.cpu.dcache.writebacks::total 671 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 680 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 680 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16294 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16294 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16974 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16974 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16974 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16974 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 998 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 998 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3195 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3195 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4193 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4193 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4193 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4193 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31703500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 31703500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 113133500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 113133500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 144837000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 144837000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 144837000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 144837000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31767.034068 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35409.546166 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34542.570952 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34542.570952 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 10 # number of replacements system.cpu.l2cache.tagsinuse 4007.455925 # Cycle average of tags in use @@ -449,36 +497,75 @@ system.cpu.l2cache.total_refs 810 # To system.cpu.l2cache.sampled_refs 4847 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.167114 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3629.785283 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 377.670641 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.110772 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.011526 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 730 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 671 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 65 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 795 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 795 # number of overall hits -system.cpu.l2cache.ReadReq_misses 4305 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 3130 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 7435 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 7435 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 148163500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 108392000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 256555500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 256555500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 5035 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 671 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 3195 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 8230 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 8230 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.855015 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.979656 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.903402 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.903402 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34416.608595 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34630.031949 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34506.455952 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34506.455952 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 377.670641 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2971.084033 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 658.701251 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011526 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.090670 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.020102 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.122298 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 600 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 130 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 730 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 671 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 671 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 65 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 65 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 600 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 195 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 795 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 600 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 195 # number of overall hits +system.cpu.l2cache.overall_hits::total 795 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3437 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 868 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4305 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 3130 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 3130 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3437 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3998 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7435 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3437 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3998 # number of overall misses +system.cpu.l2cache.overall_misses::total 7435 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 118151500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30012000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 148163500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 108392000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 108392000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 118151500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 138404000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 256555500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 118151500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 138404000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 256555500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4037 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 998 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5035 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 671 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 671 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 3195 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 3195 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4037 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4193 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8230 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4037 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4193 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 8230 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.851375 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.869739 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.979656 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.851375 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.953494 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.851375 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.953494 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34376.345650 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34576.036866 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34630.031949 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34376.345650 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34618.309155 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34376.345650 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34618.309155 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -487,30 +574,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 4305 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 3130 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 7435 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 7435 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 134314000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 98534000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 232848000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 232848000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.855015 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.979656 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.903402 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.903402 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31199.535424 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31480.511182 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31317.821116 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31317.821116 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3437 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 868 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4305 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3130 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3130 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3437 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3998 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7435 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3437 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3998 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7435 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 107040000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27274000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 134314000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98534000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98534000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 107040000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 125808000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 232848000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 107040000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 125808000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 232848000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.851375 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869739 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.979656 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.851375 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.953494 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.851375 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.953494 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31143.439046 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31421.658986 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31480.511182 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31143.439046 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31467.733867 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31143.439046 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31467.733867 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini index 8310ba9e4..ce995453a 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -54,6 +64,9 @@ icache_port=system.membus.port[2] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -64,7 +77,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-atomic +cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout index 3a628f576..3f05b7dba 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:24:12 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:11:11 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-atomic +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt index 3ed2b47f1..cdec8f7fd 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.199332 # Nu sim_ticks 199332411500 # Number of ticks simulated final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3927016 # Simulator instruction rate (inst/s) -host_tick_rate 1963508553 # Simulator tick rate (ticks/s) -host_mem_usage 204908 # Number of bytes of host memory used -host_seconds 101.52 # Real time elapsed on the host +host_inst_rate 4966970 # Simulator instruction rate (inst/s) +host_op_rate 4966969 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2483485434 # Simulator tick rate (ticks/s) +host_mem_usage 206672 # Number of bytes of host memory used +host_seconds 80.26 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated +sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read 2257107875 # Number of bytes read from this memory system.physmem.bytes_inst_read 1594658604 # Number of instructions bytes read from this memory system.physmem.bytes_written 492356798 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 215 # Nu system.cpu.numCycles 398664824 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 398664595 # Number of instructions executed +system.cpu.committedInsts 398664595 # Number of instructions committed +system.cpu.committedOps 398664595 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 316365907 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses system.cpu.num_func_calls 16015498 # number of times a function call or return occured diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini index 63aac5a1a..c8010ddb2 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -167,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout index 06075d86e..fe28e85e0 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:24:12 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:12:03 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index af7a7f90d..0281e5820 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.567343 # Nu sim_ticks 567343170000 # Number of ticks simulated final_tick 567343170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1814376 # Simulator instruction rate (inst/s) -host_tick_rate 2582053806 # Simulator tick rate (ticks/s) -host_mem_usage 213620 # Number of bytes of host memory used -host_seconds 219.73 # Real time elapsed on the host +host_inst_rate 2193403 # Simulator instruction rate (inst/s) +host_op_rate 2193403 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3121451222 # Simulator tick rate (ticks/s) +host_mem_usage 215564 # Number of bytes of host memory used +host_seconds 181.76 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated +sim_ops 398664609 # Number of ops (including micro ops) simulated system.physmem.bytes_read 459520 # Number of bytes read from this memory system.physmem.bytes_inst_read 205120 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -54,7 +56,8 @@ system.cpu.workload.num_syscalls 215 # Nu system.cpu.numCycles 1134686340 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 398664609 # Number of instructions executed +system.cpu.committedInsts 398664609 # Number of instructions committed +system.cpu.committedOps 398664609 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 316365921 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses system.cpu.num_func_calls 16015498 # number of times a function call or return occured @@ -78,26 +81,39 @@ system.cpu.icache.total_refs 398660993 # To system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1795.131074 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.876529 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 398660993 # number of ReadReq hits -system.cpu.icache.demand_hits 398660993 # number of demand (read+write) hits -system.cpu.icache.overall_hits 398660993 # number of overall hits -system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses -system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses -system.cpu.icache.overall_misses 3673 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 186032000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 186032000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 186032000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 398664666 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 398664666 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 398664666 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 50648.516199 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 50648.516199 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 50648.516199 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1795.131074 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.876529 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.876529 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 398660993 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 398660993 # number of overall hits +system.cpu.icache.overall_hits::total 398660993 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 3673 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 3673 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 3673 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses +system.cpu.icache.overall_misses::total 3673 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 186032000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 186032000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 186032000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 186032000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 186032000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 186032000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 398664666 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 398664666 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 398664666 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000009 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50648.516199 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 50648.516199 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 50648.516199 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -106,26 +122,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 3673 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 3673 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 175013000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 175013000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 175013000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 47648.516199 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3673 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 3673 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 3673 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175013000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 175013000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175013000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 175013000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175013000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 175013000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47648.516199 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.tagsinuse 3288.912598 # Cycle average of tags in use @@ -133,32 +147,49 @@ system.cpu.dcache.total_refs 168271068 # To system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3288.912598 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.802957 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 94753540 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 73517528 # number of WriteReq hits -system.cpu.dcache.demand_hits 168271068 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 168271068 # number of overall hits -system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 3202 # number of WriteReq misses -system.cpu.dcache.demand_misses 4152 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 4152 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 48286000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 176792000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 225078000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 225078000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 168275220 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 50827.368421 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 55212.991880 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 54209.537572 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 54209.537572 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 3288.912598 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.802957 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.802957 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73517528 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168271068 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168271068 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168271068 # number of overall hits +system.cpu.dcache.overall_hits::total 168271068 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 950 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 950 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3202 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3202 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 4152 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses +system.cpu.dcache.overall_misses::total 4152 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 48286000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 48286000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 176792000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 176792000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 225078000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 225078000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 225078000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 225078000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 168275220 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168275220 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168275220 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168275220 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000010 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000044 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50827.368421 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55212.991880 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54209.537572 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54209.537572 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -167,30 +198,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 649 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 45436000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 167186000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 212622000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 212622000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 47827.368421 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52212.991880 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 51209.537572 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 51209.537572 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 649 # number of writebacks +system.cpu.dcache.writebacks::total 649 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45436000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 45436000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167186000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 167186000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212622000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 212622000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212622000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 212622000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47827.368421 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52212.991880 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51209.537572 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51209.537572 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 13 # number of replacements system.cpu.l2cache.tagsinuse 3768.712262 # Cycle average of tags in use @@ -198,36 +231,75 @@ system.cpu.l2cache.total_refs 656 # To system.cpu.l2cache.sampled_refs 4572 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.143482 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3397.175455 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 371.536808 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.103674 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.011338 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 585 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 649 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 60 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 645 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 645 # number of overall hits -system.cpu.l2cache.ReadReq_misses 4038 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 3142 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 7180 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 7180 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 209976000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 163384000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 373360000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 373360000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 4623 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 649 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 3202 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.873459 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.981262 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.917572 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.917572 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 371.536808 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2770.454482 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 626.720973 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011338 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019126 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.115012 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 468 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 117 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 585 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 468 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 177 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 645 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 468 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 177 # number of overall hits +system.cpu.l2cache.overall_hits::total 645 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3205 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 833 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4038 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 3142 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 3142 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3205 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3975 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7180 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3975 # number of overall misses +system.cpu.l2cache.overall_misses::total 7180 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 166660000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43316000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 209976000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163384000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 163384000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 166660000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 206700000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 373360000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 166660000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 206700000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 373360000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 3673 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 950 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 4623 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 3202 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 3202 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 3673 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 7825 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 3673 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 7825 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.872584 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.876842 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981262 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.872584 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.957370 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.957370 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -236,30 +308,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 4038 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 3142 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 7180 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 7180 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 161520000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 125680000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 287200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 287200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.873459 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.981262 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.917572 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.917572 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3205 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 833 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4038 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3142 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3142 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3205 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3975 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7180 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3975 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7180 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 128200000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33320000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 161520000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 125680000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 125680000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 128200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 159000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 287200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 128200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 159000000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 287200000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876842 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |