diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
| commit | 25e1b1c1f5f4e0ad3976c88998161700135f4aae (patch) | |
| tree | 36e668b99a36c3dfcfefc157d7bd6b102b8f8af6 /tests/long/se/30.eon/ref/alpha | |
| parent | 7e711c98f8fcd949b9430bbf243d60348d0ef28b (diff) | |
| download | gem5-25e1b1c1f5f4e0ad3976c88998161700135f4aae.tar.xz | |
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
Diffstat (limited to 'tests/long/se/30.eon/ref/alpha')
3 files changed, 1084 insertions, 1048 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index 5e6582f7a..1a7177e69 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.226051 # Number of seconds simulated -sim_ticks 226051212500 # Number of ticks simulated -final_tick 226051212500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.226045 # Number of seconds simulated +sim_ticks 226044973500 # Number of ticks simulated +final_tick 226044973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 313509 # Simulator instruction rate (inst/s) -host_op_rate 313509 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 177766322 # Simulator tick rate (ticks/s) -host_mem_usage 302576 # Number of bytes of host memory used -host_seconds 1271.62 # Real time elapsed on the host +host_inst_rate 304016 # Simulator instruction rate (inst/s) +host_op_rate 304016 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 172378586 # Simulator tick rate (ticks/s) +host_mem_usage 302856 # Number of bytes of host memory used +host_seconds 1311.33 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 249344 # Nu system.physmem.num_reads::cpu.inst 3896 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory system.physmem.num_reads::total 7874 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1103042 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1126258 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2229300 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1103042 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1103042 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1103042 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1126258 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2229300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1103073 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1126289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2229362 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1103073 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1103073 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1103073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1126289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2229362 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7874 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7874 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 226051111000 # Total gap between requests +system.physmem.totGap 226044886000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6818 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 82 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6812 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 977 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1564 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 321.964194 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 193.457187 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.645688 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 541 34.59% 34.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 357 22.83% 57.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 194 12.40% 69.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 101 6.46% 76.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 65 4.16% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 55 3.52% 83.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 35 2.24% 86.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 34 2.17% 88.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 182 11.64% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1564 # Bytes accessed per row activation -system.physmem.totQLat 54215500 # Total ticks spent queuing -system.physmem.totMemAccLat 201853000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1551 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 323.878788 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 193.961760 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.450478 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 540 34.82% 34.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 341 21.99% 56.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 198 12.77% 69.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 105 6.77% 76.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 68 4.38% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 43 2.77% 83.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 33 2.13% 85.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 36 2.32% 87.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 187 12.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1551 # Bytes accessed per row activation +system.physmem.totQLat 53691750 # Total ticks spent queuing +system.physmem.totMemAccLat 201329250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 39370000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6885.38 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6818.87 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25635.38 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25568.87 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.23 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.23 # Average system read bandwidth in MiByte/s @@ -216,70 +216,70 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6308 # Number of row buffer hits during reads +system.physmem.readRowHits 6316 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.11 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.21 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28708548.51 # Average gap between requests -system.physmem.pageHitRate 80.11 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6872040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3749625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 34327800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 28707757.94 # Average gap between requests +system.physmem.pageHitRate 80.21 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6811560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3716625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 34210800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14764513920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5850636750 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 130498264500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 151158364635 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.692398 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 217093450250 # Time in different power states -system.physmem_0.memoryStateTime::REF 7548320000 # Time in different power states +system.physmem_0.refreshEnergy 14764005360 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5854324365 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 130490358000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 151153426710 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.693587 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 217080502500 # Time in different power states +system.physmem_0.memoryStateTime::REF 7548060000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1408913500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1414335000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4951800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2701875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 27042600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 4914000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2681250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 27011400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14764513920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5592917520 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 130724334000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 151116461715 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.507029 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 217471574500 # Time in different power states -system.physmem_1.memoryStateTime::REF 7548320000 # Time in different power states +system.physmem_1.refreshEnergy 14764005360 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5569701705 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 130740027000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 151108340715 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.494129 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 217498306250 # Time in different power states +system.physmem_1.memoryStateTime::REF 7548060000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1030789250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 997097750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 46270925 # Number of BP lookups -system.cpu.branchPred.condPredicted 26727379 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1017826 # Number of conditional branches incorrect +system.cpu.branchPred.lookups 46270920 # Number of BP lookups +system.cpu.branchPred.condPredicted 26727376 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1017825 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 25620092 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21360644 # Number of BTB hits +system.cpu.branchPred.BTBHits 21360645 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.374580 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 8341960 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 83.374584 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 8341957 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 95612151 # DTB read hits +system.cpu.dtb.read_hits 95612152 # DTB read hits system.cpu.dtb.read_misses 116 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 95612267 # DTB read accesses -system.cpu.dtb.write_hits 73605971 # DTB write hits +system.cpu.dtb.read_accesses 95612268 # DTB read accesses +system.cpu.dtb.write_hits 73605970 # DTB write hits system.cpu.dtb.write_misses 858 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73606829 # DTB write accesses +system.cpu.dtb.write_accesses 73606828 # DTB write accesses system.cpu.dtb.data_hits 169218122 # DTB hits system.cpu.dtb.data_misses 974 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 169219096 # DTB accesses -system.cpu.itb.fetch_hits 98739643 # ITB hits +system.cpu.itb.fetch_hits 98739640 # ITB hits system.cpu.itb.fetch_misses 1232 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 98740875 # ITB accesses +system.cpu.itb.fetch_accesses 98740872 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,67 +293,67 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 452102425 # number of cpu cycles simulated +system.cpu.numCycles 452089947 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664665 # Number of instructions committed system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4488157 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 4488161 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.134042 # CPI: cycles per instruction -system.cpu.ipc 0.881802 # IPC: instructions per cycle -system.cpu.tickCycles 448265843 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3836582 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.134011 # CPI: cycles per instruction +system.cpu.ipc 0.881826 # IPC: instructions per cycle +system.cpu.tickCycles 448265885 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3824062 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.681680 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168032891 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3291.715048 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168032888 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40344.031453 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40344.030732 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3291.681680 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803633 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803633 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3291.715048 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803641 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803641 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336084169 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336084169 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 94518092 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94518092 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73514799 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73514799 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168032891 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168032891 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168032891 # number of overall hits -system.cpu.dcache.overall_hits::total 168032891 # number of overall hits +system.cpu.dcache.tags.tag_accesses 336084171 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336084171 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 94518093 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94518093 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73514795 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73514795 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168032888 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168032888 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168032888 # number of overall hits +system.cpu.dcache.overall_hits::total 168032888 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1180 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1180 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5931 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5931 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 7111 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7111 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7111 # number of overall misses -system.cpu.dcache.overall_misses::total 7111 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88098000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88098000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 432683750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 432683750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 520781750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 520781750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 520781750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 520781750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 94519272 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94519272 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 5935 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5935 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 7115 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7115 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7115 # number of overall misses +system.cpu.dcache.overall_misses::total 7115 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 87916000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 87916000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 428863500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 428863500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 516779500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 516779500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 516779500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 516779500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 94519273 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94519273 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168040002 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168040002 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168040002 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168040002 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168040003 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168040003 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168040003 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168040003 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000012 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses @@ -362,14 +362,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74659.322034 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 74659.322034 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72952.916877 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72952.916877 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73236.077907 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73236.077907 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73236.077907 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73236.077907 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74505.084746 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 74505.084746 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72260.067397 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 72260.067397 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72632.396346 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72632.396346 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72632.396346 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72632.396346 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,12 +382,12 @@ system.cpu.dcache.writebacks::writebacks 654 # nu system.cpu.dcache.writebacks::total 654 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 211 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2735 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2735 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2946 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2946 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2946 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2946 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2739 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2739 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2950 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2950 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2950 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2950 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses @@ -396,14 +396,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4165 system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 69978250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 69978250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 238524000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 238524000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 308502250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 308502250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 308502250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 308502250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 71088500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 71088500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 239432500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 239432500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 310521000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 310521000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 310521000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 310521000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -412,68 +412,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72216.976264 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72216.976264 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74632.040050 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74632.040050 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74070.168067 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74070.168067 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74070.168067 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74070.168067 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73362.745098 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73362.745098 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74916.301627 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74916.301627 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74554.861945 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74554.861945 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74554.861945 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74554.861945 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3197 # number of replacements -system.cpu.icache.tags.tagsinuse 1918.668517 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 98734468 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1918.682192 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 98734465 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 5175 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19079.124251 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 19079.123671 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1918.668517 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.936850 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.936850 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1918.682192 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.936857 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.936857 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 397 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1281 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 197484461 # Number of tag accesses -system.cpu.icache.tags.data_accesses 197484461 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 98734468 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 98734468 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 98734468 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 98734468 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 98734468 # number of overall hits -system.cpu.icache.overall_hits::total 98734468 # number of overall hits +system.cpu.icache.tags.tag_accesses 197484455 # Number of tag accesses +system.cpu.icache.tags.data_accesses 197484455 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 98734465 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 98734465 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 98734465 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 98734465 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 98734465 # number of overall hits +system.cpu.icache.overall_hits::total 98734465 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 5175 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 5175 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 5175 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 5175 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5175 # number of overall misses system.cpu.icache.overall_misses::total 5175 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 322926000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 322926000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 322926000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 322926000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 322926000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 322926000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 98739643 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 98739643 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 98739643 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 98739643 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 98739643 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 98739643 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 319209000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 319209000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 319209000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 319209000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 319209000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 319209000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 98739640 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 98739640 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 98739640 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 98739640 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 98739640 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 98739640 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62401.159420 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62401.159420 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62401.159420 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62401.159420 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62401.159420 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62401.159420 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61682.898551 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61682.898551 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61682.898551 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61682.898551 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61682.898551 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61682.898551 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -488,116 +488,122 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 5175 system.cpu.icache.demand_mshr_misses::total 5175 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 5175 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 5175 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 313513500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 313513500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 313513500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 313513500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 313513500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 313513500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 314034000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 314034000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 314034000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 314034000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 314034000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 314034000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60582.318841 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60582.318841 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60582.318841 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60582.318841 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60582.318841 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60582.318841 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60682.898551 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60682.898551 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60682.898551 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60682.898551 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60682.898551 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60682.898551 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4426.539250 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1494 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 4426.586364 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4808 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5274 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.283276 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.911642 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 373.086855 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.473471 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 641.978924 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 373.093241 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.507533 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 641.985590 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011386 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104110 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104111 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.019592 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.135087 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.135089 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 5274 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 612 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4443 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160950 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 88424 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 88424 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1279 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 126 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1405 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 114936 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 114936 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 654 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 654 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 61 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 61 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1279 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1279 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 126 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 126 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 1279 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 187 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1466 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1279 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 187 # number of overall hits system.cpu.l2cache.overall_hits::total 1466 # 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number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 302340250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 597248750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 5175 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 967 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 6142 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 234115500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 234115500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 292841000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 292841000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 68160500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 68160500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 292841000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 302276000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 595117000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 292841000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 302276000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 595117000 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 654 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 654 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 3198 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 3198 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5175 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 5175 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 967 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 967 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 5175 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4165 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 9340 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 5175 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4165 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9340 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.752850 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.869700 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.771247 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.980926 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.980926 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.752850 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.752850 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.869700 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.869700 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.752850 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.955102 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.843041 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.752850 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955102 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.843041 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75695.200205 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80302.318668 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 76513.141229 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74850.494103 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74850.494103 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75695.200205 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76003.079437 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75850.742951 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75695.200205 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76003.079437 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75850.742951 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74630.379343 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74630.379343 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75164.527721 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75164.527721 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81046.967895 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81046.967895 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75164.527721 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75986.928105 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75580.010160 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75164.527721 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75986.928105 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75580.010160 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -606,84 +612,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3896 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 841 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4737 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3137 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 3137 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3896 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3896 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 841 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 841 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 3896 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 3978 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 7874 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3896 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3978 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7874 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 246135500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56978250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 303113750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 195592000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 195592000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 246135500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 252570250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 498705750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 246135500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 252570250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 498705750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.752850 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771247 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 202745500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 202745500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 253881000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 253881000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59750500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59750500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 253881000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 262496000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 516377000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 253881000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 262496000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 516377000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.752850 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.752850 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.869700 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.752850 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.843041 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.752850 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.843041 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63176.463039 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67750.594530 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63988.547604 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62350.015939 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62350.015939 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63176.463039 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63491.767220 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63335.756922 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63176.463039 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63491.767220 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63335.756922 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64630.379343 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64630.379343 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65164.527721 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65164.527721 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71046.967895 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71046.967895 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65164.527721 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65986.928105 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65580.010160 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65164.527721 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65986.928105 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65580.010160 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 6142 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 6142 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 3314 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10350 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8984 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 19334 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 5175 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 967 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13547 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9101 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22648 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 331200 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 639616 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 9994 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 13308 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 9994 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 13308 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 9994 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5651000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 13308 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7308000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8587500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7762500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7035750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6247999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 4737 # Transaction distribution system.membus.trans_dist::ReadResp 4737 # Transaction distribution system.membus.trans_dist::ReadExReq 3137 # Transaction distribution system.membus.trans_dist::ReadExResp 3137 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4737 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15748 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 15748 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 503936 # Cumulative packet size per connected master and slave (bytes) @@ -699,9 +711,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7874 # Request fanout histogram -system.membus.reqLayer0.occupancy 9179500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9183500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 41811750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 41813250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 1cb945d89..be9d713b1 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.069793 # Number of seconds simulated -sim_ticks 69793219500 # Number of ticks simulated -final_tick 69793219500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.069809 # Number of seconds simulated +sim_ticks 69809049000 # Number of ticks simulated +final_tick 69809049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 237836 # Simulator instruction rate (inst/s) -host_op_rate 237836 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44197170 # Simulator tick rate (ticks/s) -host_mem_usage 232228 # Number of bytes of host memory used -host_seconds 1579.13 # Real time elapsed on the host +host_inst_rate 246384 # Simulator instruction rate (inst/s) +host_op_rate 246384 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45796096 # Simulator tick rate (ticks/s) +host_mem_usage 304152 # Number of bytes of host memory used +host_seconds 1524.35 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 221440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255808 # Number of bytes read from this memory -system.physmem.bytes_read::total 477248 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221440 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3460 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3997 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7457 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3172801 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3665227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6838028 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3172801 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3172801 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3172801 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3665227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6838028 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7457 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 221504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255680 # Number of bytes read from this memory +system.physmem.bytes_read::total 477184 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221504 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3461 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3995 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7456 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 3172998 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3662562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6835561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3172998 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3172998 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3172998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3662562 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6835561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7456 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7457 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7456 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 477248 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 477184 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 477248 # Total read bytes from the system interface side +system.physmem.bytesReadSys 477184 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 527 # Per bank write bursts -system.physmem.perBankRdBursts::1 657 # Per bank write bursts -system.physmem.perBankRdBursts::2 455 # Per bank write bursts -system.physmem.perBankRdBursts::3 602 # Per bank write bursts +system.physmem.perBankRdBursts::1 655 # Per bank write bursts +system.physmem.perBankRdBursts::2 454 # Per bank write bursts +system.physmem.perBankRdBursts::3 600 # Per bank write bursts system.physmem.perBankRdBursts::4 446 # Per bank write bursts -system.physmem.perBankRdBursts::5 454 # Per bank write bursts +system.physmem.perBankRdBursts::5 455 # Per bank write bursts system.physmem.perBankRdBursts::6 515 # Per bank write bursts -system.physmem.perBankRdBursts::7 522 # Per bank write bursts -system.physmem.perBankRdBursts::8 438 # Per bank write bursts +system.physmem.perBankRdBursts::7 525 # Per bank write bursts +system.physmem.perBankRdBursts::8 439 # Per bank write bursts system.physmem.perBankRdBursts::9 407 # Per bank write bursts -system.physmem.perBankRdBursts::10 339 # Per bank write bursts +system.physmem.perBankRdBursts::10 338 # Per bank write bursts system.physmem.perBankRdBursts::11 305 # Per bank write bursts system.physmem.perBankRdBursts::12 414 # Per bank write bursts system.physmem.perBankRdBursts::13 542 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 69793123000 # Total gap between requests +system.physmem.totGap 69808953500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7457 # Read request sizes (log2) +system.physmem.readPktSize::6 7456 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4245 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 898 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4273 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1892 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 323 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1360 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 348.047059 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 208.039838 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 346.646558 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 428 31.47% 31.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 327 24.04% 55.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 157 11.54% 67.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 92 6.76% 73.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 56 4.12% 77.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 39 2.87% 80.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 33 2.43% 83.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 25 1.84% 85.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 203 14.93% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1360 # Bytes accessed per row activation -system.physmem.totQLat 67335750 # Total ticks spent queuing -system.physmem.totMemAccLat 207154500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37285000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9029.87 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1355 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 349.142435 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 207.457712 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 347.186854 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 436 32.18% 32.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 321 23.69% 55.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 135 9.96% 65.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 103 7.60% 73.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 56 4.13% 77.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 42 3.10% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 37 2.73% 83.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 28 2.07% 85.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 197 14.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1355 # Bytes accessed per row activation +system.physmem.totQLat 63176250 # Total ticks spent queuing +system.physmem.totMemAccLat 202976250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37280000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8473.21 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27779.87 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27223.21 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.84 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.84 # Average system read bandwidth in MiByte/s @@ -214,72 +214,72 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6086 # Number of row buffer hits during reads +system.physmem.readRowHits 6090 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.68 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9359410.35 # Average gap between requests -system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined +system.physmem.avgGap 9362788.83 # Average gap between requests +system.physmem.pageHitRate 81.68 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 5828760 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 3180375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 32377800 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 32370000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4558223280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2111779035 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 40020613500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 46732002750 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.624038 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 66577889000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2330380000 # Time in different power states +system.physmem_0.refreshEnergy 4559240400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2097349200 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 40042614750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 46740583485 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.597578 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 66614495250 # Time in different power states +system.physmem_0.memoryStateTime::REF 2330900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 882777000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 861488750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4430160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2417250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 25272000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 4399920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2400750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 25256400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4558223280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2013356565 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 40106949000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 46710648255 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.318049 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 66719394750 # Time in different power states -system.physmem_1.memoryStateTime::REF 2330380000 # Time in different power states +system.physmem_1.refreshEnergy 4559240400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1988059680 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 40138482750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 46717839900 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.271757 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 66771998750 # Time in different power states +system.physmem_1.memoryStateTime::REF 2330900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 738657750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 701106250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 51259743 # Number of BP lookups -system.cpu.branchPred.condPredicted 29683169 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1233682 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26552604 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23664767 # Number of BTB hits +system.cpu.branchPred.lookups 51296431 # Number of BP lookups +system.cpu.branchPred.condPredicted 29722668 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1234399 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 27069453 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23684308 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.124091 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9366329 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 317 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 87.494594 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9353372 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 312 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 103795078 # DTB read hits -system.cpu.dtb.read_misses 91880 # DTB read misses -system.cpu.dtb.read_acv 49322 # DTB read access violations -system.cpu.dtb.read_accesses 103886958 # DTB read accesses -system.cpu.dtb.write_hits 79431295 # DTB write hits -system.cpu.dtb.write_misses 1540 # DTB write misses +system.cpu.dtb.read_hits 103786850 # DTB read hits +system.cpu.dtb.read_misses 91978 # DTB read misses +system.cpu.dtb.read_acv 49358 # DTB read access violations +system.cpu.dtb.read_accesses 103878828 # DTB read accesses +system.cpu.dtb.write_hits 79421845 # DTB write hits +system.cpu.dtb.write_misses 1562 # DTB write misses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 79432835 # DTB write accesses -system.cpu.dtb.data_hits 183226373 # DTB hits -system.cpu.dtb.data_misses 93420 # DTB misses -system.cpu.dtb.data_acv 49324 # DTB access violations -system.cpu.dtb.data_accesses 183319793 # DTB accesses -system.cpu.itb.fetch_hits 51424924 # ITB hits -system.cpu.itb.fetch_misses 367 # ITB misses +system.cpu.dtb.write_accesses 79423407 # DTB write accesses +system.cpu.dtb.data_hits 183208695 # DTB hits +system.cpu.dtb.data_misses 93540 # DTB misses +system.cpu.dtb.data_acv 49360 # DTB access violations +system.cpu.dtb.data_accesses 183302235 # DTB accesses +system.cpu.itb.fetch_hits 51432488 # ITB hits +system.cpu.itb.fetch_misses 372 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 51425291 # ITB accesses +system.cpu.itb.fetch_accesses 51432860 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,106 +293,106 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 139586442 # number of cpu cycles simulated +system.cpu.numCycles 139618100 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 52218190 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 457878359 # Number of instructions fetch has processed -system.cpu.fetch.Branches 51259743 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33031096 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 85762697 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2573496 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 52215637 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 458041697 # Number of instructions fetch has processed +system.cpu.fetch.Branches 51296431 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33037680 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 85803922 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2575582 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 172 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 13442 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 10 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 51424924 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 558112 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 139281263 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.287437 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.344389 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.MiscStallCycles 177 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 13927 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 49 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 51432488 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 569689 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 139321507 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.287660 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.344182 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 58400466 41.93% 41.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4519538 3.24% 45.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 7300185 5.24% 50.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5568881 4.00% 54.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11993718 8.61% 63.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 8035210 5.77% 68.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5954127 4.27% 73.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1896980 1.36% 74.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35612158 25.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58400173 41.92% 41.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4522566 3.25% 45.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 7306043 5.24% 50.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5576459 4.00% 54.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 12017776 8.63% 63.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 8032548 5.77% 68.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5948759 4.27% 73.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1886194 1.35% 74.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35630989 25.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 139281263 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.367226 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.280250 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45296559 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16238717 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 71951122 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4512320 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1282545 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9579038 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4257 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 452073358 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 14179 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1282545 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 47196926 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5664651 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 519192 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 74460720 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10157229 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 448418638 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 439172 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2532304 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2861217 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 3565763 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 292805975 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 590541853 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 420605547 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 169936305 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 139321507 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.367405 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.280676 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45279858 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16277373 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 71952167 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4528520 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1283589 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9590263 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4245 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 452242919 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 14142 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1283589 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 47190225 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5719256 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 519758 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 74463142 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 10145537 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 448534058 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 439648 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2541243 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2902301 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 3500431 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 292850852 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 590664412 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 420646005 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 170018406 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33273646 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 37923 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 33318523 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 37911 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 320 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 15988914 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 106425467 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 81691000 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12462225 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9670397 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 415046688 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 308 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 407272286 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 487219 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 39472187 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 18379010 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 93 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 139281263 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.924100 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.223091 # Number of insts issued each cycle +system.cpu.rename.skidInsts 16086321 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 106433302 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 81699514 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12490023 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9782021 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 415154479 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 307 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 407277518 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 483889 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 39579977 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 18549388 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 92 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 139321507 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.923293 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.222373 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24058662 17.27% 17.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19633951 14.10% 31.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22674806 16.28% 47.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18925755 13.59% 61.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 19544360 14.03% 75.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14234748 10.22% 85.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9653364 6.93% 92.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6204842 4.45% 96.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4350775 3.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24043039 17.26% 17.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19688824 14.13% 31.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22672553 16.27% 47.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18939258 13.59% 61.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 19545668 14.03% 75.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14219061 10.21% 85.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9684319 6.95% 92.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6188357 4.44% 96.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4340428 3.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 139281263 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 139321507 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 264805 1.33% 1.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 265122 1.33% 1.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.00% 1.33% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 1.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 148480 0.74% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 91560 0.46% 2.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 2226 0.01% 2.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 3500111 17.53% 20.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1672568 8.38% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 151057 0.76% 2.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 93335 0.47% 2.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 3062 0.02% 2.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 3506383 17.53% 20.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1668666 8.34% 28.44% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.44% # attempts to use FU when none available @@ -414,118 +414,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.44% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9323721 46.69% 75.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4965817 24.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9341831 46.71% 75.16% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4968318 24.84% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 153389569 37.66% 37.67% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2128191 0.52% 38.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 153385991 37.66% 37.67% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2128232 0.52% 38.19% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 37431648 9.19% 47.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7537641 1.85% 49.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2804878 0.69% 49.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16758896 4.11% 54.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1606846 0.39% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 105464958 25.90% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 80116078 19.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 37448194 9.19% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7543709 1.85% 49.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2805732 0.69% 49.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16759263 4.11% 54.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1610357 0.40% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 105461195 25.89% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 80101264 19.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 407272286 # Type of FU issued -system.cpu.iq.rate 2.917707 # Inst issue rate -system.cpu.iq.fu_busy_cnt 19969288 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.049032 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 626696170 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 266819247 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237458259 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 347586172 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 187775636 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 163387975 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 246426590 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 180781403 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19964423 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 407277518 # Type of FU issued +system.cpu.iq.rate 2.917083 # Inst issue rate +system.cpu.iq.fu_busy_cnt 19997775 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.049101 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 626671270 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 266840013 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237433052 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 347686937 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 187970906 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 163426789 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 246404368 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 180837344 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19931279 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 11670980 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 165408 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 76048 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8170271 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 11678815 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 164981 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 76480 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8178785 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 382447 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3767 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 381276 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3827 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1282545 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4525606 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 90420 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 440059104 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 152527 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 106425467 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 81691000 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 308 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7009 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 82356 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 76048 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1000879 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 421168 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1422047 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 403473304 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 103936308 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3798982 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1283589 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4537578 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 127300 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 440164979 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 164208 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 106433302 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 81699514 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 307 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6586 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 117247 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 76480 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1004792 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 416739 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1421531 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 403496390 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 103928218 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3781128 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 25012108 # number of nop insts executed -system.cpu.iew.exec_refs 183369178 # number of memory reference insts executed -system.cpu.iew.exec_branches 46997600 # Number of branches executed -system.cpu.iew.exec_stores 79432870 # Number of stores executed -system.cpu.iew.exec_rate 2.890491 # Inst execution rate -system.cpu.iew.wb_sent 401684713 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 400846234 # cumulative count of insts written-back -system.cpu.iew.wb_producers 198095133 # num instructions producing a value -system.cpu.iew.wb_consumers 284050882 # num instructions consuming a value +system.cpu.iew.exec_nop 25010193 # number of nop insts executed +system.cpu.iew.exec_refs 183351660 # number of memory reference insts executed +system.cpu.iew.exec_branches 47000418 # Number of branches executed +system.cpu.iew.exec_stores 79423442 # Number of stores executed +system.cpu.iew.exec_rate 2.890001 # Inst execution rate +system.cpu.iew.wb_sent 401708524 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 400859841 # cumulative count of insts written-back +system.cpu.iew.wb_producers 198115569 # num instructions producing a value +system.cpu.iew.wb_consumers 284128842 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.871670 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.697393 # average fanout of values written-back +system.cpu.iew.wb_rate 2.871117 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.697274 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 41395670 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 41501718 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1229479 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 133482933 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.986633 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.212859 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1230197 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 133512631 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.985969 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.212275 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 48683097 36.47% 36.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18109981 13.57% 50.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 9618460 7.21% 57.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8715508 6.53% 63.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6449297 4.83% 68.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4412968 3.31% 71.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5003390 3.75% 75.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2633066 1.97% 77.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29857166 22.37% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 48674660 36.46% 36.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18127731 13.58% 50.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 9648746 7.23% 57.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8719124 6.53% 63.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6443109 4.83% 68.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4416607 3.31% 71.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5004547 3.75% 75.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2625621 1.97% 77.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29852486 22.36% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 133482933 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 133512631 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -571,127 +571,127 @@ system.cpu.commit.op_class_0::MemWrite 73520729 18.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 398664583 # Class of committed instruction -system.cpu.commit.bw_lim_events 29857166 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 543683043 # The number of ROB reads -system.cpu.rob.rob_writes 885930772 # The number of ROB writes -system.cpu.timesIdled 3165 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 305179 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 29852486 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 543823469 # The number of ROB reads +system.cpu.rob.rob_writes 886153369 # The number of ROB writes +system.cpu.timesIdled 3159 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 296593 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.371661 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.371661 # CPI: Total CPI of All Threads -system.cpu.ipc 2.690625 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.690625 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 403591803 # number of integer regfile reads -system.cpu.int_regfile_writes 172078772 # number of integer regfile writes -system.cpu.fp_regfile_reads 157997982 # number of floating regfile reads -system.cpu.fp_regfile_writes 105636085 # number of floating regfile writes +system.cpu.cpi 0.371745 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.371745 # CPI: Total CPI of All Threads +system.cpu.ipc 2.690015 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.690015 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 403553331 # number of integer regfile reads +system.cpu.int_regfile_writes 172072539 # number of integer regfile writes +system.cpu.fp_regfile_reads 158043337 # number of floating regfile reads +system.cpu.fp_regfile_writes 105673333 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 806 # number of replacements -system.cpu.dcache.tags.tagsinuse 3297.136243 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 156944357 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4209 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37287.801616 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 795 # number of replacements +system.cpu.dcache.tags.tagsinuse 3296.035456 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 156970312 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4197 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37400.598523 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3297.136243 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.804965 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.804965 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3403 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 3296.035456 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.804696 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.804696 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3402 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 3119 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.830811 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 313935887 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 313935887 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 83443297 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 83443297 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501051 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501051 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 156944348 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 156944348 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 156944348 # number of overall hits -system.cpu.dcache.overall_hits::total 156944348 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1804 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1804 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19678 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19678 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21482 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21482 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21482 # number of overall misses -system.cpu.dcache.overall_misses::total 21482 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 122640500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 122640500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1228413709 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1228413709 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1351054209 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1351054209 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1351054209 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1351054209 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 83445101 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 83445101 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.830566 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 313987939 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 313987939 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 83469338 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 83469338 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73500964 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73500964 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 156970302 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 156970302 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 156970302 # number of overall hits +system.cpu.dcache.overall_hits::total 156970302 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1794 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1794 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19765 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19765 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21559 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21559 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21559 # number of overall misses +system.cpu.dcache.overall_misses::total 21559 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 128871000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 128871000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1185279954 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1185279954 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1314150954 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1314150954 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1314150954 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1314150954 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 83471132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 83471132 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 9 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 9 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 156965830 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 156965830 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 156965830 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 156965830 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000268 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000268 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 156991861 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 156991861 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 156991861 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 156991861 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000137 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000137 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000137 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000137 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67982.538803 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67982.538803 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62425.739862 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62425.739862 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62892.384741 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62892.384741 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62892.384741 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62892.384741 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 51314 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 108 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 737 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71834.448161 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71834.448161 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59968.629092 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59968.629092 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60956.025511 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60956.025511 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60956.025511 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60956.025511 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 49421 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 88 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 747 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.625509 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 108 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 66.159304 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 88 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 682 # number of writebacks -system.cpu.dcache.writebacks::total 682 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 803 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 803 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16470 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16470 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17273 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17273 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17273 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17273 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1001 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1001 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3208 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3208 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4209 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4209 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4209 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4209 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 72824500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 72824500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 253362750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 253362750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 326187250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 326187250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 326187250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 326187250 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 671 # number of writebacks +system.cpu.dcache.writebacks::total 671 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 799 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 799 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16563 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16563 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17362 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17362 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17362 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17362 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 995 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 995 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4197 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4197 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4197 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4197 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76593500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 76593500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 246844000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 246844000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 323437500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 323437500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 323437500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 323437500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -700,198 +700,204 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72751.748252 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72751.748252 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78978.413342 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78978.413342 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77497.564742 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77497.564742 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77497.564742 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77497.564742 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76978.391960 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76978.391960 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77090.568395 # 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Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2157 # number of replacements +system.cpu.icache.tags.tagsinuse 1832.216020 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 51426803 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4084 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12592.263222 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1831.206745 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.894144 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.894144 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1832.216020 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894637 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894637 # 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miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.847453 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.868342 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.868342 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.847453 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.951870 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.900374 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.847453 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.951870 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.900374 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77036.889173 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77036.889173 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75867.090436 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75867.090436 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85225.115741 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85225.115741 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75867.090436 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78807.759700 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77442.730687 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75867.090436 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78807.759700 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77442.730687 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -900,102 +906,108 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3460 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 867 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4327 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3130 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3130 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3460 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3997 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7457 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3460 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3997 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7457 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 220205500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 59518000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 279723500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 210540750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 210540750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 220205500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 270058750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 490264250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 220205500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 270058750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 490264250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.846587 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.866134 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.850432 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.975686 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.975686 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.846587 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.949632 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.898867 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.846587 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.949632 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.898867 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63643.208092 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68648.212226 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64646.059626 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67265.415335 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67265.415335 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63643.208092 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67565.361521 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65745.507577 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63643.208092 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67565.361521 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65745.507577 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3131 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3131 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3461 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3461 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 864 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 864 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3461 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3995 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7456 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3461 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3995 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7456 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 209892500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 209892500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 227966000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 227966000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 64994500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 64994500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 227966000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 274887000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 502853000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 227966000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 274887000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 502853000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.977826 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.977826 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.847453 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.847453 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.868342 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.868342 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.847453 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.951870 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.900374 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.847453 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.951870 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.900374 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67036.889173 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67036.889173 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65867.090436 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65867.090436 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75225.115741 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75225.115741 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65867.090436 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68807.759700 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67442.730687 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65867.090436 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68807.759700 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67442.730687 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 5088 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5088 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 682 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3208 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3208 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8174 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9100 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 17274 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 313024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 574592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadResp 5079 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 671 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2281 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3202 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3202 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4084 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 995 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10325 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9189 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 19514 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 572928 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 8978 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 11233 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 8978 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11233 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8978 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5171000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11233 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 6287500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6830250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6126000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6882750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6295500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 4327 # Transaction distribution -system.membus.trans_dist::ReadResp 4327 # Transaction distribution -system.membus.trans_dist::ReadExReq 3130 # Transaction distribution -system.membus.trans_dist::ReadExResp 3130 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14914 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14914 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477248 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 477248 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 4325 # Transaction distribution +system.membus.trans_dist::ReadExReq 3131 # Transaction distribution +system.membus.trans_dist::ReadExResp 3131 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4325 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14912 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477184 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 477184 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7457 # Request fanout histogram +system.membus.snoop_fanout::samples 7456 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7457 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7456 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7457 # Request fanout histogram -system.membus.reqLayer0.occupancy 9341500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7456 # Request fanout histogram +system.membus.reqLayer0.occupancy 9215500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 39310250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 39331250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 97440304f..8c86953a0 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.567335 # Number of seconds simulated -sim_ticks 567335093500 # Number of ticks simulated -final_tick 567335093500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 567335097500 # Number of ticks simulated +final_tick 567335097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1360508 # Simulator instruction rate (inst/s) -host_op_rate 1360508 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1936123010 # Simulator tick rate (ticks/s) -host_mem_usage 299124 # Number of bytes of host memory used -host_seconds 293.03 # Real time elapsed on the host +host_inst_rate 1293186 # Simulator instruction rate (inst/s) +host_op_rate 1293186 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1840317995 # Simulator tick rate (ticks/s) +host_mem_usage 300812 # Number of bytes of host memory used +host_seconds 308.28 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -63,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 1134670187 # number of cpu cycles simulated +system.cpu.numCycles 1134670195 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664609 # Number of instructions committed @@ -82,7 +82,7 @@ system.cpu.num_mem_refs 168275276 # nu system.cpu.num_load_insts 94754511 # Number of load instructions system.cpu.num_store_insts 73520765 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1134670187 # Number of busy cycles +system.cpu.num_busy_cycles 1134670195 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 44587535 # Number of branches fetched @@ -122,12 +122,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 398664665 # Class of executed instruction system.cpu.dcache.tags.replacements 764 # number of replacements -system.cpu.dcache.tags.tagsinuse 3288.930570 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3288.930558 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3288.930570 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 3288.930558 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.802962 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id @@ -205,14 +205,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45659000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 45659000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 168787000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 168787000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 214446000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 214446000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 214446000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 214446000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 46134000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 46134000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 170388000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 170388000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 216522000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 216522000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 216522000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 216522000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -221,22 +221,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48062.105263 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48062.105263 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52712.991880 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52712.991880 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51648.843931 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51648.843931 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51648.843931 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51648.843931 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48562.105263 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48562.105263 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53212.991880 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53212.991880 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52148.843931 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52148.843931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52148.843931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52148.843931 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1769 # number of replacements -system.cpu.icache.tags.tagsinuse 1795.138960 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1795.138955 # Cycle average of tags in use system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1795.138960 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1795.138955 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.876533 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1904 # Occupied blocks per task id @@ -260,12 +260,12 @@ system.cpu.icache.demand_misses::cpu.inst 3673 # n system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses system.cpu.icache.overall_misses::total 3673 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 182359500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 182359500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 182359500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 182359500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 182359500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 182359500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 182363500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 182363500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 182363500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 182363500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 182363500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 182363500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses @@ -278,12 +278,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49648.652328 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49648.652328 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49648.652328 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49648.652328 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49648.652328 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49648.652328 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49649.741356 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49649.741356 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49649.741356 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49649.741356 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49649.741356 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49649.741356 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -298,34 +298,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3673 system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 176850000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 176850000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 176850000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 176850000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 176850000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 176850000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 178690500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 178690500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 178690500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 178690500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 178690500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 178690500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48148.652328 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48148.652328 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48148.652328 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48148.652328 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48148.652328 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48148.652328 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48649.741356 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48649.741356 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48649.741356 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48649.741356 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48649.741356 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48649.741356 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3772.485298 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 677 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3772.485272 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2561 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4566 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.148270 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.560885 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 371.540220 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.469918 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 630.475159 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 371.540218 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.469899 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 630.475155 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011339 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.019241 # Average percentage of cache occupancy @@ -337,78 +337,84 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 75 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 497 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3787 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.139343 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 75560 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 75560 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 468 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 591 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 90632 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 90632 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 468 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 468 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 123 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 123 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 468 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 651 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 468 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits system.cpu.l2cache.overall_hits::total 651 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3205 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 827 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4032 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 3142 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 3142 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3205 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3205 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 827 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 827 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 3205 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 3969 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 7174 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7174 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 168263000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43417500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 211680500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 164955000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 164955000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 168263000 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 168265000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 168265000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 43417500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 43417500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 168265000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 208372500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 376635500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 168263000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 376637500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 168265000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 208372500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 376635500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 3673 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 950 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 4623 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_miss_latency::total 376637500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 3202 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 3202 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 3673 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 3673 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 950 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 950 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 3673 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 7825 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 3673 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 7825 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.872584 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870526 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.872161 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981262 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.981262 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.872584 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.872584 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.870526 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.870526 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.872584 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.916805 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916805 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.156006 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.124008 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.156006 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52500.780031 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52500.780031 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.780031 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52500.069696 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.156006 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.348481 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.780031 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52500.069696 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.348481 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -417,84 +423,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3205 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 827 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4032 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3142 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 3142 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3205 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3205 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 827 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 827 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 3205 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 3969 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 7174 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7174 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 129802500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33493500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 163296000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 127251000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 127251000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129802500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160744500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 290547000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129802500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160744500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 290547000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870526 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.872161 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133535000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133535000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 136215000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 136215000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 35147500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 35147500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 136215000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168682500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 304897500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 136215000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168682500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 304897500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981262 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.872584 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.870526 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.870526 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.916805 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.916805 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42500.780031 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42500.780031 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42500.780031 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.348481 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42500.780031 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.348481 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 4623 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1884 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 3202 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 3202 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7346 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8953 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16299 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 3673 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 950 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9115 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9068 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 18183 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 235072 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 542336 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 8474 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 10358 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 8474 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 10358 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8474 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4886000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 10358 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5828000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 5509500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6228000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 4032 # Transaction distribution system.membus.trans_dist::ReadResp 4032 # Transaction distribution system.membus.trans_dist::ReadExReq 3142 # Transaction distribution system.membus.trans_dist::ReadExResp 3142 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4032 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14348 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 14348 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes) @@ -510,9 +522,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7174 # Request fanout histogram -system.membus.reqLayer0.occupancy 7174500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 7176500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 35870500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 35872500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |