diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
| commit | 55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch) | |
| tree | 6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/long/se/30.eon/ref/alpha | |
| parent | ee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff) | |
| download | gem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz | |
stats: Update to match classic memory changes
Diffstat (limited to 'tests/long/se/30.eon/ref/alpha')
3 files changed, 1073 insertions, 1059 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index b65c3962a..6b30c3cf1 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.233526 # Number of seconds simulated -sim_ticks 233525789500 # Number of ticks simulated -final_tick 233525789500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.233534 # Number of seconds simulated +sim_ticks 233533887500 # Number of ticks simulated +final_tick 233533887500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 279317 # Simulator instruction rate (inst/s) -host_op_rate 279317 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 163615265 # Simulator tick rate (ticks/s) -host_mem_usage 255720 # Number of bytes of host memory used -host_seconds 1427.29 # Real time elapsed on the host +host_inst_rate 225573 # Simulator instruction rate (inst/s) +host_op_rate 225573 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 132138421 # Simulator tick rate (ticks/s) +host_mem_usage 260868 # Number of bytes of host memory used +host_seconds 1767.34 # Real time elapsed on the host sim_insts 398664651 # Number of instructions simulated sim_ops 398664651 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 249280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory system.physmem.bytes_read::total 503872 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 249280 # Nu system.physmem.num_reads::cpu.inst 3895 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1067462 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1090209 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2157672 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1067462 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1067462 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1067462 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1090209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2157672 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1067425 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1090172 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2157597 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1067425 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1067425 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1067425 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1090172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2157597 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7873 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7873 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 233525688500 # Total gap between requests +system.physmem.totGap 233533785500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6857 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 948 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6853 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 951 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 69 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1541 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 326.852693 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 195.480715 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 331.694198 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 535 34.72% 34.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 344 22.32% 57.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 186 12.07% 69.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 104 6.75% 75.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 66 4.28% 80.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 53 3.44% 83.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 28 1.82% 85.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 39 2.53% 87.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 186 12.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1541 # Bytes accessed per row activation -system.physmem.totQLat 52273750 # Total ticks spent queuing -system.physmem.totMemAccLat 199892500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1544 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 326.051813 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 195.846863 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.937998 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 532 34.46% 34.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 344 22.28% 56.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 193 12.50% 69.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 103 6.67% 75.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 73 4.73% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 45 2.91% 83.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 32 2.07% 85.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 36 2.33% 87.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 186 12.05% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1544 # Bytes accessed per row activation +system.physmem.totQLat 53440000 # Total ticks spent queuing +system.physmem.totMemAccLat 201058750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6639.62 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6787.76 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25389.62 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25537.76 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s @@ -217,75 +217,75 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6330 # Number of row buffer hits during reads +system.physmem.readRowHits 6327 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.40 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.36 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 29661588.78 # Average gap between requests -system.physmem.pageHitRate 80.40 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6804000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3712500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 34327800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 29662617.24 # Average gap between requests +system.physmem.pageHitRate 80.36 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6758640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3687750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 34296600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15252731520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5982776145 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 134867232750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 156147584715 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.653337 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 224361889750 # Time in different power states -system.physmem_0.memoryStateTime::REF 7797920000 # Time in different power states +system.physmem_0.refreshEnergy 15253240080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6038642700 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 134822908500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 156159534270 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.682165 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 224288059000 # Time in different power states +system.physmem_0.memoryStateTime::REF 7798180000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1365674000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1447046250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4845960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2644125 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 4914000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2681250 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 27058200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15252731520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5743132470 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 135077446500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 156107858775 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.483223 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 224713608000 # Time in different power states -system.physmem_1.memoryStateTime::REF 7797920000 # Time in different power states +system.physmem_1.refreshEnergy 15253240080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5739994620 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 135084870750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 156112758900 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.481917 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 224725904750 # Time in different power states +system.physmem_1.memoryStateTime::REF 7798180000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1013955750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1009185250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 45912937 # Number of BP lookups -system.cpu.branchPred.condPredicted 26702744 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 45912940 # Number of BP lookups +system.cpu.branchPred.condPredicted 26702743 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 565787 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25186730 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 25186733 # Number of BTB lookups system.cpu.branchPred.BTBHits 18811780 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 74.689251 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 74.689242 # BTB Hit Percentage system.cpu.branchPred.usedRAS 8285572 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2249877 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 2249880 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 2235903 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 13974 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 13977 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 111495 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 95338457 # DTB read hits +system.cpu.dtb.read_hits 95338456 # DTB read hits system.cpu.dtb.read_misses 116 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 95338573 # DTB read accesses +system.cpu.dtb.read_accesses 95338572 # DTB read accesses system.cpu.dtb.write_hits 73578378 # DTB write hits system.cpu.dtb.write_misses 849 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 73579227 # DTB write accesses -system.cpu.dtb.data_hits 168916835 # DTB hits +system.cpu.dtb.data_hits 168916834 # DTB hits system.cpu.dtb.data_misses 965 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168917800 # DTB accesses -system.cpu.itb.fetch_hits 96959231 # ITB hits +system.cpu.dtb.data_accesses 168917799 # DTB accesses +system.cpu.itb.fetch_hits 96959232 # ITB hits system.cpu.itb.fetch_misses 1239 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 96960470 # ITB accesses +system.cpu.itb.fetch_accesses 96960471 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,16 +299,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 233525789500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 467051579 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 233533887500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 467067775 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664651 # Number of instructions committed system.cpu.committedOps 398664651 # Number of ops (including micro ops) committed system.cpu.discardedOps 2289293 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.171540 # CPI: cycles per instruction -system.cpu.ipc 0.853577 # IPC: instructions per cycle +system.cpu.cpi 1.171581 # CPI: cycles per instruction +system.cpu.ipc 0.853548 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction system.cpu.op_class_0::IntAlu 141652555 35.53% 41.33% # Class of committed instruction system.cpu.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction @@ -344,18 +344,18 @@ system.cpu.op_class_0::MemWrite 73520764 18.44% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 398664651 # Class of committed instruction -system.cpu.tickCycles 455740556 # Number of cycles that the object actually ticked -system.cpu.idleCycles 11311023 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 455740572 # Number of cycles that the object actually ticked +system.cpu.idleCycles 11327203 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.966637 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 167817023 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3291.924590 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 167817024 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40292.202401 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40292.202641 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3291.966637 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803703 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803703 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3291.924590 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803693 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803693 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id @@ -365,31 +365,31 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 3113 system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 335652191 # Number of tag accesses system.cpu.dcache.tags.data_accesses 335652191 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 94302223 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94302223 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73514800 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73514800 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 167817023 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 167817023 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 167817023 # number of overall hits -system.cpu.dcache.overall_hits::total 167817023 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 73514801 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73514801 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 167817024 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 167817024 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 167817024 # number of overall hits +system.cpu.dcache.overall_hits::total 167817024 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1061 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1061 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5929 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5929 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 6990 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6990 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 6990 # number of overall misses -system.cpu.dcache.overall_misses::total 6990 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 77930500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 77930500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 429190000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 429190000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 507120500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 507120500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 507120500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 507120500 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 5928 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5928 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 6989 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6989 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6989 # number of overall misses +system.cpu.dcache.overall_misses::total 6989 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 80682500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 80682500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 434084500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 434084500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 514767000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 514767000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 514767000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 514767000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94303284 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94303284 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -406,14 +406,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73450.047125 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73450.047125 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72388.261090 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72388.261090 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72549.427754 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72549.427754 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72549.427754 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72549.427754 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76043.826579 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 76043.826579 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73226.130229 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73226.130229 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73653.884676 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73653.884676 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73653.884676 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73653.884676 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -424,12 +424,12 @@ system.cpu.dcache.writebacks::writebacks 654 # nu system.cpu.dcache.writebacks::total 654 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 92 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2733 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2733 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2825 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2825 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2825 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2825 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2732 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2732 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2824 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2824 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2824 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2824 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses @@ -438,14 +438,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4165 system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70280500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 70280500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 239912500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 239912500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 310193000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 310193000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 310193000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 310193000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 72936500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 72936500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 242391000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 242391000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 315327500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 315327500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 315327500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 315327500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -454,69 +454,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72528.895769 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72528.895769 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75066.489362 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75066.489362 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74476.110444 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74476.110444 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74476.110444 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74476.110444 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75269.865841 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75269.865841 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75841.989987 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75841.989987 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75708.883553 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75708.883553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75708.883553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75708.883553 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 3193 # number of replacements -system.cpu.icache.tags.tagsinuse 1919.750364 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 96954060 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1919.733373 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 96954061 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 5171 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18749.576484 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 18749.576678 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1919.750364 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.937378 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.937378 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1919.733373 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.937370 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.937370 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1287 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 193923633 # Number of tag accesses -system.cpu.icache.tags.data_accesses 193923633 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 96954060 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 96954060 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 96954060 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 96954060 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 96954060 # number of overall hits -system.cpu.icache.overall_hits::total 96954060 # number of overall hits +system.cpu.icache.tags.tag_accesses 193923635 # Number of tag accesses +system.cpu.icache.tags.data_accesses 193923635 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 96954061 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 96954061 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 96954061 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 96954061 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 96954061 # number of overall hits +system.cpu.icache.overall_hits::total 96954061 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 5171 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 5171 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 5171 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 5171 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5171 # number of overall misses system.cpu.icache.overall_misses::total 5171 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 318040500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 318040500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 318040500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 318040500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 318040500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 318040500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 96959231 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 96959231 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 96959231 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 96959231 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 96959231 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 96959231 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 321948500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 321948500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 321948500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 321948500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 321948500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 321948500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 96959232 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 96959232 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 96959232 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 96959232 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 96959232 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 96959232 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000053 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000053 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000053 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61504.641269 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61504.641269 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61504.641269 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61504.641269 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61504.641269 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61504.641269 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62260.394508 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62260.394508 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62260.394508 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62260.394508 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62260.394508 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62260.394508 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -531,47 +531,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 5171 system.cpu.icache.demand_mshr_misses::total 5171 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 5171 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 5171 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312869500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 312869500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312869500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 312869500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312869500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 312869500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 316777500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 316777500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 316777500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 316777500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 316777500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 316777500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60504.641269 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60504.641269 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60504.641269 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60504.641269 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60504.641269 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60504.641269 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61260.394508 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61260.394508 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61260.394508 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61260.394508 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61260.394508 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61260.394508 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4425.384656 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4801 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5273 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.910487 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 7128.160045 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5427 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 7873 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.689318 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 372.164909 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.179805 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 642.039942 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011358 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104101 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.019594 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.135052 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5273 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 613 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4442 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160919 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 114871 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 114871 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.137560 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3717.022485 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104100 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.113435 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.217534 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 7873 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 503 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7185 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.240265 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 114273 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 114273 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 654 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 654 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 3193 # number of WritebackClean hits @@ -600,18 +599,18 @@ system.cpu.l2cache.demand_misses::total 7873 # nu system.cpu.l2cache.overall_misses::cpu.inst 3895 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3978 # number of overall misses system.cpu.l2cache.overall_misses::total 7873 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 234589500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 234589500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 291713500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 291713500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 67354500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 67354500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 291713500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 301944000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 593657500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 291713500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 301944000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 593657500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 237071000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 237071000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 295621500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 295621500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 70008000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 70008000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 295621500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 307079000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 602700500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 295621500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 307079000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 602700500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 654 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 654 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 3193 # number of WritebackClean accesses(hits+misses) @@ -640,18 +639,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.843295 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.753239 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955102 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.843295 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74781.479120 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74781.479120 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74894.351733 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74894.351733 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80088.585018 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80088.585018 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74894.351733 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75903.469080 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75404.229646 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74894.351733 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75903.469080 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75404.229646 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75572.521517 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75572.521517 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75897.689345 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75897.689345 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83243.757432 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83243.757432 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75897.689345 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77194.318753 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76552.838816 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75897.689345 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77194.318753 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76552.838816 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -670,18 +669,18 @@ system.cpu.l2cache.demand_mshr_misses::total 7873 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3895 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3978 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7873 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 203219500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 203219500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 252763500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 252763500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 58944500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 58944500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 252763500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 262164000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 514927500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 252763500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 262164000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 514927500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 205701000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 205701000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 256671500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 256671500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 61598000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 61598000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 256671500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 267299000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 523970500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 256671500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 267299000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 523970500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.753239 # mshr miss rate for ReadCleanReq accesses @@ -694,25 +693,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.843295 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.753239 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.843295 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64781.479120 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64781.479120 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64894.351733 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64894.351733 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70088.585018 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70088.585018 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64894.351733 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65903.469080 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65404.229646 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64894.351733 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65903.469080 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65404.229646 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65572.521517 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65572.521517 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65897.689345 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65897.689345 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73243.757432 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73243.757432 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65897.689345 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67194.318753 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66552.838816 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65897.689345 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67194.318753 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66552.838816 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 13300 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 3964 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 6138 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 654 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 3193 # Transaction distribution @@ -744,9 +743,15 @@ system.cpu.toL2Bus.reqLayer0.occupancy 10497000 # La system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 7756500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6247999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6247500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 7873 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4736 # Transaction distribution system.membus.trans_dist::ReadExReq 3137 # Transaction distribution system.membus.trans_dist::ReadExResp 3137 # Transaction distribution @@ -767,9 +772,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7873 # Request fanout histogram -system.membus.reqLayer0.occupancy 9219000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9223000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 41801750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 41799750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 81cd1b880..71e9e3432 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.064189 # Number of seconds simulated -sim_ticks 64188759000 # Number of ticks simulated -final_tick 64188759000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.064159 # Number of seconds simulated +sim_ticks 64159445000 # Number of ticks simulated +final_tick 64159445000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 260398 # Simulator instruction rate (inst/s) -host_op_rate 260398 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44504184 # Simulator tick rate (ticks/s) -host_mem_usage 257256 # Number of bytes of host memory used -host_seconds 1442.31 # Real time elapsed on the host +host_inst_rate 223776 # Simulator instruction rate (inst/s) +host_op_rate 223776 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38227708 # Simulator tick rate (ticks/s) +host_mem_usage 261380 # Number of bytes of host memory used +host_seconds 1678.35 # Real time elapsed on the host sim_insts 375574794 # Number of instructions simulated sim_ops 375574794 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 220736 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 255360 # Number of bytes read from this memory -system.physmem.bytes_read::total 476160 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 220800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 220800 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3450 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 476096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 220736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220736 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3449 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3990 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7440 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3439855 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3978267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7418121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3439855 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3439855 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3439855 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3978267 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7418121 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7440 # Number of read requests accepted +system.physmem.num_reads::total 7439 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 3440429 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3980084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7420513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3440429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3440429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3440429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3980084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7420513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7439 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7440 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7439 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 476160 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 476096 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 476160 # Total read bytes from the system interface side +system.physmem.bytesReadSys 476096 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -56,7 +56,7 @@ system.physmem.perBankRdBursts::10 339 # Pe system.physmem.perBankRdBursts::11 305 # Per bank write bursts system.physmem.perBankRdBursts::12 414 # Per bank write bursts system.physmem.perBankRdBursts::13 540 # Per bank write bursts -system.physmem.perBankRdBursts::14 454 # Per bank write bursts +system.physmem.perBankRdBursts::14 453 # Per bank write bursts system.physmem.perBankRdBursts::15 380 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 64188663500 # Total gap between requests +system.physmem.totGap 64159334500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7440 # Read request sizes (log2) +system.physmem.readPktSize::6 7439 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,11 +91,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1868 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 921 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1861 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 920 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1358 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 347.287187 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 206.380841 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 346.777138 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 443 32.62% 32.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 304 22.39% 55.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 160 11.78% 66.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 96 7.07% 73.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 54 3.98% 77.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 38 2.80% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 38 2.80% 83.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 25 1.84% 85.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 200 14.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1358 # Bytes accessed per row activation -system.physmem.totQLat 65294500 # Total ticks spent queuing -system.physmem.totMemAccLat 204794500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37200000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8776.14 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1349 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 352.640474 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 209.024877 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 349.175025 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 440 32.62% 32.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 302 22.39% 55.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 154 11.42% 66.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 83 6.15% 72.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 53 3.93% 76.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 50 3.71% 80.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 36 2.67% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 35 2.59% 85.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 196 14.53% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1349 # Bytes accessed per row activation +system.physmem.totQLat 63577500 # Total ticks spent queuing +system.physmem.totMemAccLat 203058750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37195000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8546.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27526.14 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27296.51 # Average memory access latency per DRAM burst system.physmem.avgRdBW 7.42 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 7.42 # Average system read bandwidth in MiByte/s @@ -217,75 +217,75 @@ system.physmem.busUtilRead 0.06 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6069 # Number of row buffer hits during reads +system.physmem.readRowHits 6088 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.84 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8627508.53 # Average gap between requests -system.physmem.pageHitRate 81.57 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5843880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3188625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 32221800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 8624725.70 # Average gap between requests +system.physmem.pageHitRate 81.84 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5821200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3176250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 32416800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4192060080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1996054785 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 36758466000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 42987835170 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.776911 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 61149211250 # Time in different power states -system.physmem_0.memoryStateTime::REF 2143180000 # Time in different power states +system.physmem_0.refreshEnergy 4190534400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1995176700 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 36745221000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 42972346350 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.779347 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 61126318750 # Time in different power states +system.physmem_0.memoryStateTime::REF 2142400000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 890802750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 890255000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4399920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2400750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 25217400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 4377240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2388375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 25560600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4192060080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1854861795 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 36882319500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 42961259445 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.362844 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 61355238000 # Time in different power states -system.physmem_1.memoryStateTime::REF 2143180000 # Time in different power states +system.physmem_1.refreshEnergy 4190534400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1859740425 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 36864024750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 42946625790 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.378459 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 61324552000 # Time in different power states +system.physmem_1.memoryStateTime::REF 2142400000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 684265000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 692021750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 47858697 # Number of BP lookups -system.cpu.branchPred.condPredicted 27887013 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 573168 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 23334340 # Number of BTB lookups -system.cpu.branchPred.BTBHits 19575055 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 47856205 # Number of BP lookups +system.cpu.branchPred.condPredicted 27886274 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 572784 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 23348714 # Number of BTB lookups +system.cpu.branchPred.BTBHits 19574502 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.889474 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 8688210 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1446 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2339152 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2308305 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 30847 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 111425 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 83.835461 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 8687459 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1418 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 2338624 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2308001 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 30623 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 111239 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 98833092 # DTB read hits -system.cpu.dtb.read_misses 28443 # DTB read misses -system.cpu.dtb.read_acv 867 # DTB read access violations -system.cpu.dtb.read_accesses 98861535 # DTB read accesses -system.cpu.dtb.write_hits 75500788 # DTB write hits +system.cpu.dtb.read_hits 98829712 # DTB read hits +system.cpu.dtb.read_misses 28367 # DTB read misses +system.cpu.dtb.read_acv 845 # DTB read access violations +system.cpu.dtb.read_accesses 98858079 # DTB read accesses +system.cpu.dtb.write_hits 75499203 # DTB write hits system.cpu.dtb.write_misses 1454 # DTB write misses system.cpu.dtb.write_acv 3 # DTB write access violations -system.cpu.dtb.write_accesses 75502242 # DTB write accesses -system.cpu.dtb.data_hits 174333880 # DTB hits -system.cpu.dtb.data_misses 29897 # DTB misses -system.cpu.dtb.data_acv 870 # DTB access violations -system.cpu.dtb.data_accesses 174363777 # DTB accesses -system.cpu.itb.fetch_hits 46960311 # ITB hits -system.cpu.itb.fetch_misses 430 # ITB misses -system.cpu.itb.fetch_acv 5 # ITB acv -system.cpu.itb.fetch_accesses 46960741 # ITB accesses +system.cpu.dtb.write_accesses 75500657 # DTB write accesses +system.cpu.dtb.data_hits 174328915 # DTB hits +system.cpu.dtb.data_misses 29821 # DTB misses +system.cpu.dtb.data_acv 848 # DTB access violations +system.cpu.dtb.data_accesses 174358736 # DTB accesses +system.cpu.itb.fetch_hits 46955913 # ITB hits +system.cpu.itb.fetch_misses 420 # ITB misses +system.cpu.itb.fetch_acv 7 # ITB acv +system.cpu.itb.fetch_accesses 46956333 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,141 +299,141 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 128377521 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 128318893 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 47431154 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 424848239 # Number of instructions fetch has processed -system.cpu.fetch.Branches 47858697 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 30571570 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80009353 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1247564 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 47425719 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 424811206 # Number of instructions fetch has processed +system.cpu.fetch.Branches 47856205 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 30569962 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 79950349 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1246202 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 13 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 284 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 13513 # Number of stall cycles due to pending traps +system.cpu.fetch.MiscStallCycles 270 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 13187 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 60 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 46960311 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 225671 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 128078159 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.317101 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.349648 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 46955913 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 225768 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 128012699 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.318508 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.349839 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 53091522 41.45% 41.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4331488 3.38% 44.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6713646 5.24% 50.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5106781 3.99% 54.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 10967794 8.56% 62.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 7526071 5.88% 68.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5305239 4.14% 72.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1848793 1.44% 74.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 33186825 25.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 53041219 41.43% 41.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4325218 3.38% 44.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6711253 5.24% 50.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5104898 3.99% 54.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 10968142 8.57% 62.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 7524114 5.88% 68.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5300788 4.14% 72.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1845614 1.44% 74.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 33191453 25.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 128078159 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.372797 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.309366 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 42083889 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 13603478 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 67893810 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3877357 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 619625 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 8883159 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4198 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 421926458 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 13804 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 619625 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 43653235 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3048927 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 516546 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70101215 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10138611 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 419911173 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 439346 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2543427 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2848893 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 3543199 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 273983157 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 552185759 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 393726185 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 158459573 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 128012699 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.372947 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.310590 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 42125446 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 13481218 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 67948873 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3838220 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 618942 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 8882912 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4201 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 421902807 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 13825 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 618942 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 43678343 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3058028 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 517106 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70134710 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 10005570 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 419884966 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 437260 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2526892 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2765017 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 3520699 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 273968908 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 552151473 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 393698766 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 158452706 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532319 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14450838 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 14436589 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 37562 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 298 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 15867681 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 99739292 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 76524203 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 11895065 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9302116 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 392194254 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 15635470 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 99735139 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 76519296 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 11859955 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9294086 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 392181792 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 290 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 389210938 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 196221 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 16619749 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7681566 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 389203558 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 195886 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 16607287 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7664931 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 75 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 128078159 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.038855 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.181056 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 128012699 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.040351 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.180919 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17247166 13.47% 13.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19402738 15.15% 28.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22008781 17.18% 45.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17964276 14.03% 59.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 19060613 14.88% 74.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 13269746 10.36% 85.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8793023 6.87% 91.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6106038 4.77% 96.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4225778 3.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17224377 13.46% 13.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19358192 15.12% 28.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22001472 17.19% 45.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17955910 14.03% 59.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 19066405 14.89% 74.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 13282652 10.38% 85.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8794829 6.87% 91.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6104058 4.77% 96.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4224804 3.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 128078159 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 128012699 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 255592 1.41% 1.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 138975 0.77% 2.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 79489 0.44% 2.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 3727 0.02% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 3445589 19.00% 21.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1648341 9.09% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8051616 44.40% 75.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4508979 24.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 256922 1.42% 1.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 1.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 138470 0.76% 2.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 78848 0.44% 2.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 3339 0.02% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 3443164 19.01% 21.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1648895 9.10% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8039924 44.38% 75.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4505956 24.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 146987981 37.77% 37.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2128295 0.55% 38.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 146986421 37.77% 37.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2128250 0.55% 38.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 36418632 9.36% 47.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7354909 1.89% 49.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2800462 0.72% 50.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16556521 4.25% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1584140 0.41% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 36418938 9.36% 47.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7355017 1.89% 49.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2800646 0.72% 50.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16556809 4.25% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1584153 0.41% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.95% # Type of FU issued @@ -455,82 +455,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.95% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 99505104 25.57% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 75841313 19.49% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 99502900 25.57% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 75836843 19.49% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 389210938 # Type of FU issued -system.cpu.iq.rate 3.031769 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18132308 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.046587 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 592570653 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 242193331 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 227932630 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 332257911 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 166691582 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 158290719 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 234731368 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 172578297 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19373689 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 389203558 # Type of FU issued +system.cpu.iq.rate 3.033096 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18115520 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.046545 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 592493180 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 242176639 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 227925873 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 332238041 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 166682962 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 158291544 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 234723560 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172561937 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19352464 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4984806 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 93159 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 70985 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3003475 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4980653 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 92349 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 70589 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2998568 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 382536 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3859 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 383293 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3853 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 619625 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1856570 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 132026 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 415917767 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 108843 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 99739292 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 76524203 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 618942 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1854909 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 149633 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 415904338 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 108226 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 99735139 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 76519296 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 290 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 8227 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 123512 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 70985 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 411741 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 230567 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 642308 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 387626106 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 98862428 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1584832 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 7462 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 141873 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 70589 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 411438 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 230495 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 641933 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 387616397 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 98858950 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1587161 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 23723223 # number of nop insts executed -system.cpu.iew.exec_refs 174364706 # number of memory reference insts executed -system.cpu.iew.exec_branches 45864043 # Number of branches executed -system.cpu.iew.exec_stores 75502278 # Number of stores executed -system.cpu.iew.exec_rate 3.019424 # Inst execution rate -system.cpu.iew.wb_sent 386487511 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 386223349 # cumulative count of insts written-back -system.cpu.iew.wb_producers 192322376 # num instructions producing a value -system.cpu.iew.wb_consumers 273878502 # num instructions consuming a value -system.cpu.iew.wb_rate 3.008497 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.702218 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 17254297 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 23722256 # number of nop insts executed +system.cpu.iew.exec_refs 174359643 # number of memory reference insts executed +system.cpu.iew.exec_branches 45862472 # Number of branches executed +system.cpu.iew.exec_stores 75500693 # Number of stores executed +system.cpu.iew.exec_rate 3.020727 # Inst execution rate +system.cpu.iew.wb_sent 386480663 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 386217417 # cumulative count of insts written-back +system.cpu.iew.wb_producers 192328787 # num instructions producing a value +system.cpu.iew.wb_consumers 273868663 # num instructions consuming a value +system.cpu.iew.wb_rate 3.009825 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.702266 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 17240745 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 569011 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 125612042 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.173777 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.248518 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 568625 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 125549188 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.175366 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.248155 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 42074654 33.50% 33.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 17552788 13.97% 47.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 8725383 6.95% 54.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9055727 7.21% 61.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6223211 4.95% 66.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4119483 3.28% 69.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4738198 3.77% 73.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2406397 1.92% 75.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 30716201 24.45% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 42020703 33.47% 33.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 17522364 13.96% 47.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 8729636 6.95% 54.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9062074 7.22% 61.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6240745 4.97% 66.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4112376 3.28% 69.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 4753795 3.79% 73.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2410879 1.92% 75.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 30696616 24.45% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 125612042 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 125549188 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664569 # Number of instructions committed system.cpu.commit.committedOps 398664569 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -576,33 +576,33 @@ system.cpu.commit.op_class_0::MemWrite 73520728 18.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 398664569 # Class of committed instruction -system.cpu.commit.bw_lim_events 30716201 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 510811730 # The number of ROB reads -system.cpu.rob.rob_writes 834310252 # The number of ROB writes -system.cpu.timesIdled 3164 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 299362 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 30696616 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 510754909 # The number of ROB reads +system.cpu.rob.rob_writes 834280363 # The number of ROB writes +system.cpu.timesIdled 3150 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 306194 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574794 # Number of Instructions Simulated system.cpu.committedOps 375574794 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.341816 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.341816 # CPI: Total CPI of All Threads -system.cpu.ipc 2.925550 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.925550 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 385452871 # number of integer regfile reads -system.cpu.int_regfile_writes 165252221 # number of integer regfile writes -system.cpu.fp_regfile_reads 154536644 # number of floating regfile reads -system.cpu.fp_regfile_writes 102074619 # number of floating regfile writes +system.cpu.cpi 0.341660 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.341660 # CPI: Total CPI of All Threads +system.cpu.ipc 2.926886 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.926886 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 385442521 # number of integer regfile reads +system.cpu.int_regfile_writes 165246956 # number of integer regfile writes +system.cpu.fp_regfile_reads 154535424 # number of floating regfile reads +system.cpu.fp_regfile_writes 102076666 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 776 # number of replacements -system.cpu.dcache.tags.tagsinuse 3292.009184 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 152572889 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4176 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 36535.653496 # Average number of references to valid blocks. +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 779 # number of replacements +system.cpu.dcache.tags.tagsinuse 3291.925722 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 152589979 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4179 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 36513.514956 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3292.009184 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803713 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803713 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3291.925722 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803693 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803693 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3400 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id @@ -610,45 +610,45 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 211 system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.830078 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 305192990 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 305192990 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 79071847 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 79071847 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501036 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501036 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 305227185 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 305227185 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 79088959 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 79088959 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501014 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501014 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 152572883 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 152572883 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 152572883 # number of overall hits -system.cpu.dcache.overall_hits::total 152572883 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1826 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1826 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19692 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19692 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21518 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21518 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21518 # number of overall misses -system.cpu.dcache.overall_misses::total 21518 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 128481000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 128481000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1201737956 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1201737956 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1330218956 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1330218956 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1330218956 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1330218956 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 79073673 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 79073673 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 152589973 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 152589973 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 152589973 # number of overall hits +system.cpu.dcache.overall_hits::total 152589973 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1810 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1810 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19714 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19714 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21524 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21524 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21524 # number of overall misses +system.cpu.dcache.overall_misses::total 21524 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 128203000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 128203000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1194602455 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1194602455 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1322805455 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1322805455 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1322805455 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1322805455 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 79090769 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 79090769 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520728 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520728 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 152594401 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 152594401 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 152594401 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 152594401 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 152611497 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 152611497 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 152611497 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 152611497 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000268 # miss rate for WriteReq accesses @@ -657,258 +657,257 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000141 system.cpu.dcache.demand_miss_rate::total 0.000141 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000141 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000141 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70361.993428 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70361.993428 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61026.709120 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61026.709120 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61818.893763 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61818.893763 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61818.893763 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61818.893763 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 50592 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 80 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 740 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70830.386740 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70830.386740 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60596.654915 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60596.654915 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61457.231695 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61457.231695 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61457.231695 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61457.231695 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 49869 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 82 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 741 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 68.367568 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 80 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 655 # number of writebacks -system.cpu.dcache.writebacks::total 655 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 838 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 838 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16504 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16504 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17342 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17342 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17342 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17342 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 988 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 988 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3188 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3188 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4176 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4176 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4176 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4176 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 74762500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 74762500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 249321500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 249321500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 324084000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 324084000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 324084000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 324084000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 67.299595 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 82 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 658 # number of writebacks +system.cpu.dcache.writebacks::total 658 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 821 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 821 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16524 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16524 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17345 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17345 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17345 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17345 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 989 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 989 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3190 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3190 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4179 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4179 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4179 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4179 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76039500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 76039500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 251163000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 251163000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 327202500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 327202500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 327202500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 327202500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000013 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000013 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75670.546559 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75670.546559 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78206.242158 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78206.242158 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77606.321839 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77606.321839 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77606.321839 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77606.321839 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 2132 # number of replacements -system.cpu.icache.tags.tagsinuse 1831.246133 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 46954666 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4060 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11565.188670 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76885.237614 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76885.237614 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78734.482759 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78734.482759 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78296.841350 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78296.841350 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78296.841350 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78296.841350 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 2131 # number of replacements +system.cpu.icache.tags.tagsinuse 1829.791655 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 46950265 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4058 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11569.804091 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1831.246133 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.894163 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.894163 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1928 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1346 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 93924682 # Number of tag accesses -system.cpu.icache.tags.data_accesses 93924682 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 46954666 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 46954666 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 46954666 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 46954666 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 46954666 # number of overall hits -system.cpu.icache.overall_hits::total 46954666 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5645 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5645 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5645 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5645 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5645 # number of overall misses -system.cpu.icache.overall_misses::total 5645 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 370489499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 370489499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 370489499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 370489499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 370489499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 370489499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 46960311 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 46960311 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 46960311 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 46960311 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 46960311 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 46960311 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1829.791655 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.893453 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.893453 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1927 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 297 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1343 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.940918 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 93915884 # Number of tag accesses +system.cpu.icache.tags.data_accesses 93915884 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 46950265 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 46950265 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 46950265 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 46950265 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 46950265 # number of overall hits +system.cpu.icache.overall_hits::total 46950265 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5648 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5648 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5648 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5648 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5648 # number of overall misses +system.cpu.icache.overall_misses::total 5648 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 373323999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 373323999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 373323999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 373323999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 373323999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 373323999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 46955913 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 46955913 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 46955913 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 46955913 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 46955913 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 46955913 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000120 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000120 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000120 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000120 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000120 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000120 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65631.443578 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 65631.443578 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 65631.443578 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 65631.443578 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 65631.443578 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 65631.443578 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 496 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66098.441749 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 66098.441749 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 66098.441749 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 66098.441749 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 66098.441749 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 66098.441749 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 575 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 62 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 63.888889 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 2132 # number of writebacks -system.cpu.icache.writebacks::total 2132 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1585 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1585 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1585 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1585 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1585 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1585 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4060 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4060 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4060 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4060 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4060 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4060 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 275403500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 275403500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 275403500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 275403500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 275403500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 275403500 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 2131 # number of writebacks +system.cpu.icache.writebacks::total 2131 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1590 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1590 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1590 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1590 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1590 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1590 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4058 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4058 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4058 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4058 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4058 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4058 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 277954000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 277954000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 277954000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 277954000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 277954000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 277954000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67833.374384 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67833.374384 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67833.374384 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67833.374384 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67833.374384 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67833.374384 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68495.317891 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68495.317891 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68495.317891 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68495.317891 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68495.317891 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68495.317891 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4001.708243 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3078 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4847 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.635032 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 6688.615033 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3708 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 7439 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.498454 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 370.790492 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2968.908882 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 662.008869 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011316 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.090604 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.020203 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.122122 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 4847 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 137 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 533 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4032 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.147919 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 97187 # 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average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73368.329466 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73368.329466 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66175.942029 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69116.290727 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67752.822581 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66175.942029 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69116.290727 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67752.822581 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 11144 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2908 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_misses::total 7439 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 214348000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 214348000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 230879000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 230879000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 64512500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 64512500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 230879000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 278860500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 509739500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 230879000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 278860500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 509739500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980564 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980564 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.849926 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.849926 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.871587 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.871587 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.849926 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.954774 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.903120 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.849926 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.954774 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.903120 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68525.575448 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68525.575448 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66940.852421 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66940.852421 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74840.487239 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74840.487239 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66940.852421 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69889.849624 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68522.583681 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66940.852421 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69889.849624 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68522.583681 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 11147 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2910 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 5048 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 655 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2132 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 5047 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 658 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2131 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 121 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3188 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3188 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 4060 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 988 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10252 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9128 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 19380 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 396288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309184 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 705472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 3190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4058 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 989 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10247 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9137 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 19384 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 396096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 705664 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 8236 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 8237 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 8236 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 8237 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8236 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 8359000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 8237 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 8362500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6090499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6087499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6264000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6268500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4312 # Transaction distribution +system.membus.snoop_filter.tot_requests 7439 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 4311 # Transaction distribution system.membus.trans_dist::ReadExReq 3128 # Transaction distribution system.membus.trans_dist::ReadExResp 3128 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4312 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14880 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14880 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476160 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 476160 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 4311 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14878 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14878 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 476096 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 7440 # Request fanout histogram +system.membus.snoop_fanout::samples 7439 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7440 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7439 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7440 # Request fanout histogram -system.membus.reqLayer0.occupancy 9246500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7439 # Request fanout histogram +system.membus.reqLayer0.occupancy 9245500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 39238750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 39234750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 9532c68be..33645e09f 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.567385 # Number of seconds simulated -sim_ticks 567385356500 # Number of ticks simulated -final_tick 567385356500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.567393 # Number of seconds simulated +sim_ticks 567392530500 # Number of ticks simulated +final_tick 567392530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1154582 # Simulator instruction rate (inst/s) -host_op_rate 1154582 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1643217424 # Simulator tick rate (ticks/s) -host_mem_usage 254440 # Number of bytes of host memory used -host_seconds 345.29 # Real time elapsed on the host +host_inst_rate 646502 # Simulator instruction rate (inst/s) +host_op_rate 646502 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 920122456 # Simulator tick rate (ticks/s) +host_mem_usage 259072 # Number of bytes of host memory used +host_seconds 616.65 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory system.physmem.bytes_read::total 459136 # Number of bytes read from this memory @@ -22,15 +22,15 @@ system.physmem.bytes_inst_read::total 205120 # Nu system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7174 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 361518 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 447696 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 809214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 361518 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 361518 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 361518 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 447696 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 809214 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 361513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 447690 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 809203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 361513 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 361513 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 361513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 447690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 809203 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -65,8 +65,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 567385356500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1134770713 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 567392530500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1134785061 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664609 # Number of instructions committed @@ -85,7 +85,7 @@ system.cpu.num_mem_refs 168275276 # nu system.cpu.num_load_insts 94754511 # Number of load instructions system.cpu.num_store_insts 73520765 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1134770713 # Number of busy cycles +system.cpu.num_busy_cycles 1134785061 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 44587535 # Number of branches fetched @@ -124,16 +124,16 @@ system.cpu.op_class::MemWrite 73520765 18.44% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 398664665 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 764 # number of replacements -system.cpu.dcache.tags.tagsinuse 3288.807028 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3288.789389 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3288.807028 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.802931 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.802931 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3288.789389 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.802927 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.802927 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id @@ -143,7 +143,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 3112 system.cpu.dcache.tags.occ_task_id_percent::1024 0.827148 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 336554592 # Number of tag accesses system.cpu.dcache.tags.data_accesses 336554592 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 4152 # n system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses system.cpu.dcache.overall_misses::total 4152 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 52888500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 52888500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 195593000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 195593000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 248481500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 248481500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 248481500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 248481500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 53715500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 53715500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 198735000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 198735000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 252450500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 252450500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 252450500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 252450500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55672.105263 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55672.105263 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61084.634603 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61084.634603 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59846.218690 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59846.218690 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59846.218690 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59846.218690 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56542.631579 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56542.631579 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62065.896315 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62065.896315 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60802.143545 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60802.143545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60802.143545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60802.143545 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -208,14 +208,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51938500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 51938500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 192391000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 192391000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 244329500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 244329500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 244329500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 244329500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52765500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 52765500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 195533000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 195533000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 248298500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 248298500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 248298500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 248298500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -224,34 +224,34 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54672.105263 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54672.105263 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60084.634603 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60084.634603 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58846.218690 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58846.218690 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55542.631579 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55542.631579 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61065.896315 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61065.896315 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59802.143545 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 59802.143545 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59802.143545 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 59802.143545 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1769 # number of replacements -system.cpu.icache.tags.tagsinuse 1795.084430 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1795.076643 # Cycle average of tags in use system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1795.084430 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.876506 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.876506 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1795.076643 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.876502 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.876502 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1904 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 251 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1375 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.929688 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 797333005 # Number of tag accesses system.cpu.icache.tags.data_accesses 797333005 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits @@ -264,12 +264,12 @@ system.cpu.icache.demand_misses::cpu.inst 3673 # n system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses system.cpu.icache.overall_misses::total 3673 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 204815000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 204815000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 204815000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 204815000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 204815000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 204815000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 208020000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 208020000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 208020000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 208020000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 208020000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 208020000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses @@ -282,12 +282,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55762.319630 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55762.319630 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55762.319630 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55762.319630 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55762.319630 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55762.319630 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56634.903349 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56634.903349 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56634.903349 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56634.903349 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56634.903349 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56634.903349 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -302,48 +302,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3673 system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 201142000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 201142000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 201142000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 201142000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 201142000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 201142000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 204347000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 204347000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 204347000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 204347000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 204347000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 204347000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54762.319630 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54762.319630 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54762.319630 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54762.319630 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55634.903349 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55634.903349 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55634.903349 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 55634.903349 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55634.903349 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 55634.903349 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3772.330397 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2561 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4566 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.560885 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 6481.659208 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3184 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 7174 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.443825 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 371.516873 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.363420 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 630.450105 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011338 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084545 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.019240 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.115122 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 4566 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 77 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 497 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3787 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.139343 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 90632 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 90632 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.348214 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3711.310994 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084544 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.113260 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.197805 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 7174 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 392 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6535 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.218933 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 90038 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 90038 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 649 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 649 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1769 # number of WritebackClean hits @@ -372,18 +370,18 @@ system.cpu.l2cache.demand_misses::total 7174 # nu system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7174 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 186953000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 186953000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 190709000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 190709000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49213500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 49213500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 190709000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 236166500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 426875500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 190709000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 236166500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 426875500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 190095000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 190095000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 193914000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 193914000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50040500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 50040500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 193914000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 240135500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 434049500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 193914000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 240135500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 434049500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 649 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 649 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 1769 # number of WritebackClean accesses(hits+misses) @@ -412,18 +410,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.916805 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916805 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59501.273074 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59501.273074 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.588144 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.588144 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59508.464329 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59508.464329 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.588144 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59502.771479 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59503.136326 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.588144 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59502.771479 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59503.136326 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60501.273074 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60501.273074 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60503.588144 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60503.588144 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60508.464329 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60508.464329 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60503.588144 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60502.771479 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60503.136326 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60503.588144 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60502.771479 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60503.136326 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -442,18 +440,18 @@ system.cpu.l2cache.demand_mshr_misses::total 7174 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7174 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 155533000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 155533000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 158659000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 158659000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 40943500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 40943500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 158659000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 196476500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 355135500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 158659000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 196476500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 355135500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 158675000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158675000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 161864000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 161864000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 41770500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 41770500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 161864000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 200445500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 362309500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 161864000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 200445500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 362309500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981262 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadCleanReq accesses @@ -466,25 +464,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.916805 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.916805 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49501.273074 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49501.273074 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.588144 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.588144 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49508.464329 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49508.464329 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.588144 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49502.771479 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.136326 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.588144 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49502.771479 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.136326 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50501.273074 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50501.273074 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.588144 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.588144 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50508.464329 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50508.464329 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.588144 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50502.771479 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50503.136326 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.588144 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50502.771479 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50503.136326 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 10358 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2533 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 649 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1769 # Transaction distribution @@ -518,7 +516,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 5509500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6228000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 7174 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4032 # Transaction distribution system.membus.trans_dist::ReadExReq 3142 # Transaction distribution system.membus.trans_dist::ReadExResp 3142 # Transaction distribution |