summaryrefslogtreecommitdiff
path: root/tests/long/se/30.eon/ref/alpha
diff options
context:
space:
mode:
authorNilay Vaish <nilay@cs.wisc.edu>2013-01-24 12:29:00 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2013-01-24 12:29:00 -0600
commit9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b (patch)
tree64b85031cb791a21af6059778384d358d992b817 /tests/long/se/30.eon/ref/alpha
parentdbeabedaf0f8d9ec0ea3331db2e44b1add53f79f (diff)
downloadgem5-9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b.tar.xz
regressions: update stats due to branch predictor changes
The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
Diffstat (limited to 'tests/long/se/30.eon/ref/alpha')
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini57
-rwxr-xr-xtests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout8
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt27
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini57
-rwxr-xr-xtests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout8
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt27
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini21
-rwxr-xr-xtests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout8
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt10
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini68
-rwxr-xr-xtests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout12
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt210
12 files changed, 255 insertions, 258 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
index d18ed7c2f..9ca2ce67b 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,18 +31,13 @@ system_port=system.membus.slave[0]
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
+children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
activity=0
+branchPred=system.cpu.branchPred
cachePorts=2
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
cpu_id=0
-defer_registration=false
div16Latency=1
div16RepeatRate=1
div24Latency=1
@@ -57,17 +53,9 @@ dtb=system.cpu.dtb
fetchBuffSize=4
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -76,11 +64,11 @@ memBlockSize=64
multLatency=1
multRepeatRate=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
stageTracing=false
stageWidth=4
+switched_out=false
system=system
threadModel=SMT
tracer=system.cpu.tracer
@@ -88,6 +76,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -95,21 +101,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -126,21 +127,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -163,21 +159,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -204,7 +195,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
index 063caa36a..21846ca98 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 11:24:52
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:33:34
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
index 1ee5829a5..7980de17a 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.139847 # Nu
sim_ticks 139846906500 # Number of ticks simulated
final_tick 139846906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 122154 # Simulator instruction rate (inst/s)
-host_op_rate 122154 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 42850332 # Simulator tick rate (ticks/s)
-host_mem_usage 220236 # Number of bytes of host memory used
-host_seconds 3263.61 # Real time elapsed on the host
+host_inst_rate 94955 # Simulator instruction rate (inst/s)
+host_op_rate 94955 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 33309069 # Simulator tick rate (ticks/s)
+host_mem_usage 278532 # Number of bytes of host memory used
+host_seconds 4198.46 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
sim_ops 398664595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory
@@ -185,6 +185,15 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate 87.94 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 19083904.82 # Average gap between requests
+system.cpu.branchPred.lookups 53489670 # Number of BP lookups
+system.cpu.branchPred.condPredicted 30685393 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 15149659 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 32882351 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 15212538 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 46.263535 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 8007516 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 20 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@@ -221,14 +230,6 @@ system.cpu.workload.num_syscalls 215 # Nu
system.cpu.numCycles 279693814 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 53489670 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 30685393 # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 15149659 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 32882351 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 15212538 # Number of BTB hits
-system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target.
-system.cpu.branch_predictor.RASInCorrect 20 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 46.263535 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 29230505 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 24259165 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 280386588 # Number of Reads from Int. Register File
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
index 8e356eaf5..123a4827a 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -56,7 +53,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -116,6 +103,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -125,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -132,21 +138,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -426,21 +427,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -463,21 +459,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -504,7 +495,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
index c6043774f..a1122f6bc 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 11:29:31
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:48:30
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index d6188dabe..078219244 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.077336 # Nu
sim_ticks 77336466500 # Number of ticks simulated
final_tick 77336466500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 195499 # Simulator instruction rate (inst/s)
-host_op_rate 195499 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 40256068 # Simulator tick rate (ticks/s)
-host_mem_usage 221208 # Number of bytes of host memory used
-host_seconds 1921.11 # Real time elapsed on the host
+host_inst_rate 141610 # Simulator instruction rate (inst/s)
+host_op_rate 141610 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 29159685 # Simulator tick rate (ticks/s)
+host_mem_usage 279556 # Number of bytes of host memory used
+host_seconds 2652.17 # Real time elapsed on the host
sim_insts 375574808 # Number of instructions simulated
sim_ops 375574808 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory
@@ -185,6 +185,15 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate 87.37 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 10391883.63 # Average gap between requests
+system.cpu.branchPred.lookups 50254079 # Number of BP lookups
+system.cpu.branchPred.condPredicted 29238788 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1202354 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 26185724 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 23237791 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 88.742213 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 9009650 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1041 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@@ -221,14 +230,6 @@ system.cpu.workload.num_syscalls 215 # Nu
system.cpu.numCycles 154672935 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 50254079 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 29238788 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 1202354 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 26185724 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 23237791 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 9009650 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 1041 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 51121474 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 448760218 # Number of instructions fetch has processed
system.cpu.fetch.Branches 50254079 # Number of branches that fetch encountered
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
index 4442b5ed2..e04d3a419 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
@@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -29,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -42,17 +44,18 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -67,6 +70,9 @@ size=64
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
@@ -82,7 +88,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864
@@ -99,14 +105,15 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout
index ba8d40ed9..1bc520ee3 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 11:50:11
-gem5 started Jun 4 2012 14:23:04
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:04:20
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
index 695830448..a976b0a99 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.199332 # Nu
sim_ticks 199332411500 # Number of ticks simulated
final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3372014 # Simulator instruction rate (inst/s)
-host_op_rate 3372014 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1686007461 # Simulator tick rate (ticks/s)
-host_mem_usage 211928 # Number of bytes of host memory used
-host_seconds 118.23 # Real time elapsed on the host
+host_inst_rate 2294613 # Simulator instruction rate (inst/s)
+host_op_rate 2294613 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1147307033 # Simulator tick rate (ticks/s)
+host_mem_usage 269948 # Number of bytes of host memory used
+host_seconds 173.74 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
sim_ops 398664595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 1594658604 # Number of bytes read from this memory
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
index d4c58b08d..a2dc77128 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
@@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -29,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -41,15 +43,16 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -61,21 +64,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -90,21 +90,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -113,6 +110,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
@@ -120,23 +120,20 @@ size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -145,10 +142,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@@ -158,12 +155,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864
@@ -181,13 +178,14 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
-master=system.physmem.port[0]
+master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
index d468809f0..b077bccfc 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
@@ -1,14 +1,16 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 2 2012 08:30:56
-gem5 started Jul 2 2012 09:39:35
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:49:24
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.566667
-Exiting @ tick 567365869000 because target called exit()
+Exiting @ tick 567335093000 because target called exit()
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
index 26c4b55f8..39d4d27ed 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.567335 # Nu
sim_ticks 567335093000 # Number of ticks simulated
final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1803555 # Simulator instruction rate (inst/s)
-host_op_rate 1803555 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2566617886 # Simulator tick rate (ticks/s)
-host_mem_usage 223016 # Number of bytes of host memory used
-host_seconds 221.04 # Real time elapsed on the host
+host_inst_rate 853902 # Simulator instruction rate (inst/s)
+host_op_rate 853902 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1215178011 # Simulator tick rate (ticks/s)
+host_mem_usage 278532 # Number of bytes of host memory used
+host_seconds 466.87 # Real time elapsed on the host
sim_insts 398664609 # Number of instructions simulated
sim_ops 398664609 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory
@@ -160,106 +160,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 47648.516199
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 764 # number of replacements
-system.cpu.dcache.tagsinuse 3288.930576 # Cycle average of tags in use
-system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 3288.930576 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.802962 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 73517528 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 168271068 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 168271068 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 168271068 # number of overall hits
-system.cpu.dcache.overall_hits::total 168271068 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 950 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 950 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 3202 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 3202 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 4152 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses
-system.cpu.dcache.overall_misses::total 4152 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 47084000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 47084000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 173590000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 173590000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 220674000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 220674000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 220674000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 220674000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 168275220 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 168275220 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 168275220 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 168275220 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000010 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000010 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000044 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000044 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49562.105263 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 49562.105263 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54212.991880 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54212.991880 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 53148.843931 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 53148.843931 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
-system.cpu.dcache.writebacks::total 649 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45184000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 45184000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167186000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 167186000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212370000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 212370000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212370000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 212370000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47562.105263 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47562.105263 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52212.991880 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52212.991880 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 3772.485305 # Cycle average of tags in use
system.cpu.l2cache.total_refs 677 # Total number of references to valid blocks.
@@ -396,5 +296,105 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 764 # number of replacements
+system.cpu.dcache.tagsinuse 3288.930576 # Cycle average of tags in use
+system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 3288.930576 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.802962 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 73517528 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 168271068 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 168271068 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 168271068 # number of overall hits
+system.cpu.dcache.overall_hits::total 168271068 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 950 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 950 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 3202 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 3202 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 4152 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses
+system.cpu.dcache.overall_misses::total 4152 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 47084000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 47084000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 173590000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 173590000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 220674000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 220674000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 220674000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 220674000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 168275220 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 168275220 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 168275220 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 168275220 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000010 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000010 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000044 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000044 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49562.105263 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 49562.105263 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54212.991880 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 54212.991880 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 53148.843931 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 53148.843931 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
+system.cpu.dcache.writebacks::total 649 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45184000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 45184000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167186000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 167186000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212370000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 212370000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212370000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 212370000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47562.105263 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47562.105263 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52212.991880 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52212.991880 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------