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authorNilay Vaish <nilay@cs.wisc.edu>2015-01-04 13:02:12 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2015-01-04 13:02:12 -0600
commite979e8d75e12caee2b4b1ab3512d7f2fdba4fcdb (patch)
tree553bace58f742b4c98ac52d600a1103901011b8b /tests/long/se/30.eon/ref/alpha
parent0d8d6e44419e2c5464012b66abc62aaad433026b (diff)
downloadgem5-e979e8d75e12caee2b4b1ab3512d7f2fdba4fcdb.tar.xz
stats: changes due to recent changesets.
Diffstat (limited to 'tests/long/se/30.eon/ref/alpha')
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt230
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini6
2 files changed, 139 insertions, 97 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
index fd544a1a5..688c5f811 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
@@ -4,26 +4,30 @@ sim_seconds 0.226819 # Nu
sim_ticks 226818771000 # Number of ticks simulated
final_tick 226818771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 333141 # Simulator instruction rate (inst/s)
-host_op_rate 333141 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 189539219 # Simulator tick rate (ticks/s)
-host_mem_usage 300760 # Number of bytes of host memory used
-host_seconds 1196.69 # Real time elapsed on the host
+host_inst_rate 207340 # Simulator instruction rate (inst/s)
+host_op_rate 207340 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 117965343 # Simulator tick rate (ticks/s)
+host_mem_usage 287544 # Number of bytes of host memory used
+host_seconds 1922.76 # Real time elapsed on the host
sim_insts 398664665 # Number of instructions simulated
sim_ops 398664665 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 503872 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 249280 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory
system.physmem.bytes_read::total 503872 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 249280 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 249280 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 7873 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 3895 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 2221474 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1099027 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1122447 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2221474 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1099027 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1099027 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 2221474 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1099027 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1122447 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2221474 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 7873 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
@@ -306,8 +310,8 @@ system.cpu.dcache.tags.total_refs 168028615 # To
system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 40343.004802 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.955330 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst 0.803700 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 3291.955330 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.803700 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.803700 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
@@ -318,53 +322,53 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114
system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 336075633 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 336075633 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst 94513823 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data 94513823 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 94513823 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst 73514792 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 73514792 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 73514792 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.inst 168028615 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::cpu.data 168028615 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168028615 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst 168028615 # number of overall hits
+system.cpu.dcache.overall_hits::cpu.data 168028615 # number of overall hits
system.cpu.dcache.overall_hits::total 168028615 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst 1181 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data 1181 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1181 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst 5938 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 5938 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5938 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst 7119 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::cpu.data 7119 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 7119 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst 7119 # number of overall misses
+system.cpu.dcache.overall_misses::cpu.data 7119 # number of overall misses
system.cpu.dcache.overall_misses::total 7119 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst 81009750 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 81009750 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 81009750 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst 391587500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 391587500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 391587500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst 472597250 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 472597250 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 472597250 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst 472597250 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 472597250 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 472597250 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst 94515004 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data 94515004 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 94515004 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.inst 73520730 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst 168035734 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 168035734 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 168035734 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst 168035734 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 168035734 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 168035734 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000012 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000081 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000081 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68594.199831 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68594.199831 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 68594.199831 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65946.025598 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65946.025598 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 65946.025598 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66385.342042 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 66385.342042 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 66385.342042 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66385.342042 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 66385.342042 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 66385.342042 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
@@ -376,45 +380,45 @@ system.cpu.dcache.fast_writes 0 # nu
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 654 # number of writebacks
system.cpu.dcache.writebacks::total 654 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 211 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 211 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2743 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2743 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2743 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst 2954 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 2954 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2954 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst 2954 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 2954 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2954 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 970 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 970 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 970 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 3195 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3195 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 3195 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst 4165 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 4165 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst 4165 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 64296000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 64296000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 64296000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 214342750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 214342750 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 214342750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 278638750 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 278638750 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 278638750 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 278638750 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 278638750 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 278638750 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66284.536082 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66284.536082 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66284.536082 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67086.932707 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67086.932707 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67086.932707 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66900.060024 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66900.060024 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66900.060024 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66900.060024 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66900.060024 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66900.060024 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 3196 # number of replacements
@@ -510,9 +514,11 @@ system.cpu.l2cache.tags.sampled_refs 5273 # Sa
system.cpu.l2cache.tags.avg_refs 0.283330 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 373.138335 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 4053.786392 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.752394 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 642.033998 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.011387 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123712 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104118 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.019593 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.135099 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 5273 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id
@@ -522,57 +528,75 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4443
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160919 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 88415 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 88415 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst 1405 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst 1279 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 126 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1405 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 654 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 654 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.inst 61 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 61 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 61 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 1466 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst 1279 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 187 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1466 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 1466 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst 1279 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 187 # number of overall hits
system.cpu.l2cache.overall_hits::total 1466 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 4736 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst 3895 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 841 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 4736 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst 3137 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 3137 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 3137 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 7873 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst 3895 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 3978 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 7873 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 7873 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst 3895 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 3978 # number of overall misses
system.cpu.l2cache.overall_misses::total 7873 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 324955500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 263088750 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61866750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 324955500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 210698500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 210698500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 210698500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 535654000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 263088750 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 272565250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 535654000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 535654000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 263088750 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 272565250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 535654000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 6141 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 5174 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 967 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 6141 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 654 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 654 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst 3198 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 3198 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 3198 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 9339 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst 5174 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 4165 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9339 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 9339 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 5174 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 4165 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9339 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.771210 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.752802 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.869700 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.771210 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.980926 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.980926 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.980926 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.843024 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.752802 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.955102 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.843024 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.843024 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.752802 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.955102 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.843024 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68613.914696 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67545.250321 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73563.317479 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68613.914696 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67165.604080 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67165.604080 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67165.604080 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68036.834752 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67545.250321 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68518.162393 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 68036.834752 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68036.834752 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67545.250321 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68518.162393 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 68036.834752 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
@@ -582,37 +606,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4736 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3895 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 841 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 4736 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 3137 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3137 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 3137 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 7873 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3895 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 3978 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 7873 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 7873 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3895 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 3978 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 7873 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 265602000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 214177750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 51424250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 265602000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 171025500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 171025500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 171025500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 436627500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 214177750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 222449750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 436627500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 436627500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 214177750 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 222449750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 436627500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.771210 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.752802 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771210 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.980926 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.843024 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.752802 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.843024 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.843024 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.752802 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.843024 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56081.503378 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54987.869063 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61146.551724 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56081.503378 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54518.807778 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54518.807778 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54518.807778 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55458.846691 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54987.869063 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55919.997486 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55458.846691 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55458.846691 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54987.869063 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55919.997486 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55458.846691 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 6141 # Transaction distribution
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
index c0739097e..de709e95a 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -155,6 +155,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -502,6 +503,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -551,6 +553,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
@@ -600,6 +603,7 @@ eventq_index=0
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
+drivers=
egid=100
env=
errout=cerr
@@ -608,6 +612,7 @@ eventq_index=0
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
@@ -681,6 +686,7 @@ clk_domain=system.clk_domain
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0