diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
| commit | a217eba078b17c51f6a74c9237584f066ef78bf1 (patch) | |
| tree | e566cbeb3520341dbdf6ecb0d3932a31d4e156fe /tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt | |
| parent | db430698bfd4d77a49e11031bb65444552891f37 (diff) | |
| download | gem5-a217eba078b17c51f6a74c9237584f066ef78bf1.tar.xz | |
stats: Update stats for CPU and cache changes
This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
Diffstat (limited to 'tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt | 1152 |
1 files changed, 576 insertions, 576 deletions
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 0a05ac469..73979cce4 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,560 +1,58 @@ ---------- Begin Simulation Statistics ---------- -final_tick 227445516000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -host_inst_rate 153700 # Simulator instruction rate (inst/s) -host_mem_usage 303376 # Number of bytes of host memory used -host_op_rate 196498 # Simulator op (including micro ops) rate (op/s) -host_seconds 1776.44 # Real time elapsed on the host -host_tick_rate 128034740 # Simulator tick rate (ticks/s) +sim_seconds 0.212377 # Number of seconds simulated +sim_ticks 212377413000 # Number of ticks simulated +final_tick 212377413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 273037854 # Number of instructions simulated -sim_ops 349065592 # Number of ops (including micro ops) simulated -sim_seconds 0.227446 # Number of seconds simulated -sim_ticks 227445516000 # Number of ticks simulated +host_inst_rate 166098 # Simulator instruction rate (inst/s) +host_op_rate 199419 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 129195965 # Simulator tick rate (ticks/s) +host_mem_usage 326468 # Number of bytes of host memory used +host_seconds 1643.84 # Real time elapsed on the host +sim_insts 273037856 # Number of instructions simulated +sim_ops 327812213 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.362247 # BTB Hit Percentage -system.cpu.branchPred.BTBHits 16723894 # Number of BTB hits -system.cpu.branchPred.BTBLookups 20061712 # Number of BTB lookups -system.cpu.branchPred.RASInCorrect 121 # Number of incorrect RAS predictions. -system.cpu.branchPred.condIncorrect 1671536 # Number of conditional branches incorrect -system.cpu.branchPred.condPredicted 21059526 # Number of conditional branches predicted -system.cpu.branchPred.lookups 35363260 # Number of BP lookups -system.cpu.branchPred.usedRAS 6617396 # Number of times the RAS was used to get a target. -system.cpu.committedInsts 273037854 # Number of instructions committed -system.cpu.committedOps 349065592 # Number of ops (including micro ops) committed -system.cpu.cpi 1.666037 # CPI: cycles per instruction -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 10895 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 10895 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses::cpu.inst 95145110 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 95145110 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61749.740048 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61749.740048 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61620.734497 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61620.734497 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits::cpu.inst 95143025 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 95143025 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 128748208 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 128748208 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::cpu.inst 2085 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2085 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 424 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 102352040 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 102352040 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000017 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1661 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1661 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::cpu.inst 10895 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68469.206380 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 68469.206380 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68654.108392 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68654.108392 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits::cpu.inst 82047473 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047473 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 356313750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 356313750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000063 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000063 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::cpu.inst 5204 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5204 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2344 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2344 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 196350750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 196350750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2860 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2860 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::cpu.inst 177197787 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 177197787 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66547.120044 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66547.120044 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66070.070781 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66070.070781 # average overall mshr miss latency -system.cpu.dcache.demand_hits::cpu.inst 177190498 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 177190498 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::cpu.inst 485061958 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 485061958 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000041 # miss rate for demand accesses -system.cpu.dcache.demand_misses::cpu.inst 7289 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7289 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::cpu.inst 2768 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2768 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 298702790 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 298702790 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::cpu.inst 4521 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4521 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses::cpu.inst 177197787 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 177197787 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66547.120044 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66547.120044 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66070.070781 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66070.070781 # average overall mshr miss latency -system.cpu.dcache.overall_hits::cpu.inst 177190498 # number of overall hits -system.cpu.dcache.overall_hits::total 177190498 # number of overall hits -system.cpu.dcache.overall_miss_latency::cpu.inst 485061958 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 485061958 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.dcache.overall_misses::cpu.inst 7289 # number of overall misses -system.cpu.dcache.overall_misses::total 7289 # number of overall misses -system.cpu.dcache.overall_mshr_hits::cpu.inst 2768 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2768 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 298702790 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 298702790 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::cpu.inst 4521 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4521 # number of overall MSHR misses -system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 674 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2436 # Occupied blocks per task id -system.cpu.dcache.tags.avg_refs 39197.586375 # Average number of references to valid blocks. -system.cpu.dcache.tags.data_accesses 354443675 # Number of data accesses -system.cpu.dcache.tags.occ_blocks::cpu.inst 3089.554835 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.754286 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.754286 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3161 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.771729 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.replacements 1360 # number of replacements -system.cpu.dcache.tags.sampled_refs 4521 # Sample count of references to valid blocks. -system.cpu.dcache.tags.tag_accesses 354443675 # Number of tag accesses -system.cpu.dcache.tags.tagsinuse 3089.554835 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 177212288 # Total number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks::writebacks 1013 # number of writebacks -system.cpu.dcache.writebacks::total 1013 # number of writebacks -system.cpu.discardedOps 6932970 # Number of ops (including micro ops) which were discarded before commit -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses::cpu.inst 77471042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 77471042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17858.870336 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17858.870336 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15825.006083 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15825.006083 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::cpu.inst 77429612 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 77429612 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::cpu.inst 739892998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 739892998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000535 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000535 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::cpu.inst 41430 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 41430 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 655630002 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 655630002 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000535 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 41430 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 41430 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::cpu.inst 77471042 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 77471042 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17858.870336 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17858.870336 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15825.006083 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15825.006083 # average overall mshr miss latency -system.cpu.icache.demand_hits::cpu.inst 77429612 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 77429612 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::cpu.inst 739892998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 739892998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::cpu.inst 0.000535 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000535 # miss rate for demand accesses -system.cpu.icache.demand_misses::cpu.inst 41430 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 41430 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 655630002 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 655630002 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000535 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::cpu.inst 41430 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 41430 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses::cpu.inst 77471042 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 77471042 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17858.870336 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17858.870336 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15825.006083 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15825.006083 # average overall mshr miss latency -system.cpu.icache.overall_hits::cpu.inst 77429612 # number of overall hits -system.cpu.icache.overall_hits::total 77429612 # number of overall hits -system.cpu.icache.overall_miss_latency::cpu.inst 739892998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 739892998 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::cpu.inst 0.000535 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000535 # miss rate for overall accesses -system.cpu.icache.overall_misses::cpu.inst 41430 # number of overall misses -system.cpu.icache.overall_misses::total 41430 # number of overall misses -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 655630002 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 655630002 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000535 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::cpu.inst 41430 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 41430 # number of overall MSHR misses -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 288 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1478 # Occupied blocks per task id -system.cpu.icache.tags.avg_refs 1868.971300 # Average number of references to valid blocks. -system.cpu.icache.tags.data_accesses 154983513 # Number of data accesses -system.cpu.icache.tags.occ_blocks::cpu.inst 1927.026996 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.940931 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.940931 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1941 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.947754 # Percentage of cache occupancy per task id -system.cpu.icache.tags.replacements 39488 # number of replacements -system.cpu.icache.tags.sampled_refs 41429 # Sample count of references to valid blocks. -system.cpu.icache.tags.tag_accesses 154983513 # Number of tag accesses -system.cpu.icache.tags.tagsinuse 1927.026996 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 77429612 # Total number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.idleCycles 4029946 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.ipc 0.600227 # IPC: instructions per cycle -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2860 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2860 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67967.563291 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67967.563291 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55399.173699 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55399.173699 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits::cpu.inst 16 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 193299750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 193299750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.994406 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.994406 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 2844 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2844 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 157555250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 157555250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994406 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994406 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 2844 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 2844 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 43091 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 43091 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68852.642487 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68852.642487 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56391.699770 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56391.699770 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits::cpu.inst 38266 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 38266 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 332214000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 332214000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.111972 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.111972 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 4825 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4825 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 42 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 269721500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 269721500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.110998 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.110998 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4783 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4783 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses::writebacks 1013 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1013 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits::writebacks 1013 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1013 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses::cpu.inst 45951 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 45951 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68524.416482 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68524.416482 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56021.600892 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56021.600892 # average overall mshr miss latency -system.cpu.l2cache.demand_hits::cpu.inst 38282 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 38282 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::cpu.inst 525513750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 525513750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.166895 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.166895 # miss rate for demand accesses -system.cpu.l2cache.demand_misses::cpu.inst 7669 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7669 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits::cpu.inst 42 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 42 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 427276750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 427276750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.165981 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.165981 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7627 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7627 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses::cpu.inst 45951 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 45951 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68524.416482 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68524.416482 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56021.600892 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56021.600892 # average overall mshr miss latency -system.cpu.l2cache.overall_hits::cpu.inst 38282 # number of overall hits -system.cpu.l2cache.overall_hits::total 38282 # number of overall hits -system.cpu.l2cache.overall_miss_latency::cpu.inst 525513750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 525513750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.166895 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.166895 # miss rate for overall accesses -system.cpu.l2cache.overall_misses::cpu.inst 7669 # number of overall misses -system.cpu.l2cache.overall_misses::total 7669 # number of overall misses -system.cpu.l2cache.overall_mshr_hits::cpu.inst 42 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 42 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 427276750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 427276750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.165981 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.165981 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7627 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7627 # number of overall MSHR misses -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1262 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4305 # Occupied blocks per task id -system.cpu.l2cache.tags.avg_refs 6.727368 # Average number of references to valid blocks. -system.cpu.l2cache.tags.data_accesses 384272 # Number of data accesses -system.cpu.l2cache.tags.occ_blocks::writebacks 356.812936 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3883.048925 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.010889 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.118501 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.129390 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5700 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.173950 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.sampled_refs 5700 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.tag_accesses 384272 # Number of tag accesses -system.cpu.l2cache.tags.tagsinuse 4239.861860 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 38346 # Total number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.numCycles 454891032 # number of cpu cycles simulated -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.tickCycles 450861086 # Number of cycles that the CPU actually ticked -system.cpu.toL2Bus.data_through_bus 3005632 # Total data (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 82859 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10055 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 92914 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 24495000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 62845998 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7514710 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.throughput 13214734 # Throughput (bytes/s) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2651456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 354176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 3005632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.trans_dist::ReadReq 43091 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 43090 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1013 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2860 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2860 # Transaction distribution -system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.membus.data_through_bus 488128 # Total data (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15254 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15254 # Packet count per connected master and slave (bytes) -system.membus.reqLayer0.occupancy 8910000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 71341750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.throughput 2146132 # Throughput (bytes/s) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 488128 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 488128 # Cumulative packet size per connected master and slave (bytes) -system.membus.trans_dist::ReadReq 4783 # Transaction distribution -system.membus.trans_dist::ReadResp 4783 # Transaction distribution -system.membus.trans_dist::ReadExReq 2844 # Transaction distribution -system.membus.trans_dist::ReadExResp 2844 # Transaction distribution -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgGap 29821084.57 # Average gap between requests -system.physmem.avgMemAccLat 25580.41 # Average memory access latency per DRAM burst -system.physmem.avgQLat 6830.41 # Average queueing delay per DRAM burst -system.physmem.avgRdBW 2.15 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.15 # Average system read bandwidth in MiByte/s -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.busUtil 0.02 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.bw_inst_read::cpu.inst 974721 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 974721 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 2146132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2146132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2146132 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2146132 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytesPerActivate::samples 1544 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 315.689119 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 184.950751 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.584238 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 593 38.41% 38.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 326 21.11% 59.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 172 11.14% 70.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 76 4.92% 75.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 71 4.60% 80.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 58 3.76% 83.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 38 2.46% 86.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 28 1.81% 88.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 182 11.79% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1544 # Bytes accessed per row activation -system.physmem.bytesReadDRAM 488128 # Total number of bytes read from DRAM -system.physmem.bytesReadSys 488128 # Total read bytes from the system interface side +system.physmem.bytes_read::cpu.inst 485312 # Number of bytes read from this memory +system.physmem.bytes_read::total 485312 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219008 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 7583 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2285139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2285139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1031221 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1031221 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2285139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2285139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7583 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 7583 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 485312 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 485312 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory -system.physmem.bytes_read::cpu.inst 488128 # Number of bytes read from this memory -system.physmem.bytes_read::total 488128 # Number of bytes read from this memory -system.physmem.memoryStateTime::IDLE 217468466000 # Time in different power states -system.physmem.memoryStateTime::REF 7594860000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 2381096500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.num_reads::cpu.inst 7627 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7627 # Number of read requests responded to by this memory -system.physmem.pageHitRate 79.70 # Row buffer hit rate, read and write combined -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.perBankRdBursts::0 637 # Per bank write bursts -system.physmem.perBankRdBursts::1 850 # Per bank write bursts -system.physmem.perBankRdBursts::2 633 # Per bank write bursts +system.physmem.perBankRdBursts::0 630 # Per bank write bursts +system.physmem.perBankRdBursts::1 843 # Per bank write bursts +system.physmem.perBankRdBursts::2 628 # Per bank write bursts system.physmem.perBankRdBursts::3 541 # Per bank write bursts -system.physmem.perBankRdBursts::4 470 # Per bank write bursts -system.physmem.perBankRdBursts::5 350 # Per bank write bursts -system.physmem.perBankRdBursts::6 175 # Per bank write bursts -system.physmem.perBankRdBursts::7 229 # Per bank write bursts -system.physmem.perBankRdBursts::8 210 # Per bank write bursts -system.physmem.perBankRdBursts::9 309 # Per bank write bursts -system.physmem.perBankRdBursts::10 346 # Per bank write bursts +system.physmem.perBankRdBursts::4 466 # Per bank write bursts +system.physmem.perBankRdBursts::5 349 # Per bank write bursts +system.physmem.perBankRdBursts::6 173 # Per bank write bursts +system.physmem.perBankRdBursts::7 228 # Per bank write bursts +system.physmem.perBankRdBursts::8 209 # Per bank write bursts +system.physmem.perBankRdBursts::9 310 # Per bank write bursts +system.physmem.perBankRdBursts::10 342 # Per bank write bursts system.physmem.perBankRdBursts::11 428 # Per bank write bursts -system.physmem.perBankRdBursts::12 552 # Per bank write bursts -system.physmem.perBankRdBursts::13 714 # Per bank write bursts -system.physmem.perBankRdBursts::14 639 # Per bank write bursts -system.physmem.perBankRdBursts::15 544 # Per bank write bursts +system.physmem.perBankRdBursts::12 554 # Per bank write bursts +system.physmem.perBankRdBursts::13 705 # Per bank write bursts +system.physmem.perBankRdBursts::14 637 # Per bank write bursts +system.physmem.perBankRdBursts::15 540 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -571,9 +69,26 @@ system.physmem.perBankWrBursts::12 0 # Pe system.physmem.perBankWrBursts::13 0 # Per bank write bursts system.physmem.perBankWrBursts::14 0 # Per bank write bursts system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.rdQLenPdf::0 6680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 887 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 212377186000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 7583 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 6625 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -603,22 +118,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.readBursts 7627 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7627 # Read request sizes (log2) -system.physmem.readReqs 7627 # Number of read requests accepted -system.physmem.readRowHitRate 79.70 # Row buffer hit rate for reads -system.physmem.readRowHits 6079 # Number of row buffer hits during reads -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.totBusLat 38135000 # Total ticks spent in databus transfers -system.physmem.totGap 227445412000 # Total gap between requests -system.physmem.totMemAccLat 195101750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totQLat 52095500 # Total ticks spent queuing system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -683,17 +182,518 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.bytesPerActivate::samples 1498 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 322.691589 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.527839 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 333.553355 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 554 36.98% 36.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 333 22.23% 59.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 160 10.68% 69.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 67 4.47% 74.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 72 4.81% 79.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 61 4.07% 83.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 43 2.87% 86.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 33 2.20% 88.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 175 11.68% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1498 # Bytes accessed per row activation +system.physmem.totQLat 52122500 # Total ticks spent queuing +system.physmem.totMemAccLat 194303750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37915000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6873.60 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 25623.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 6077 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.voltage_domain.voltage 1 # Voltage in Volts +system.physmem.readRowHitRate 80.14 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 28007013.85 # Average gap between requests +system.physmem.pageHitRate 80.14 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 202838268250 # Time in different power states +system.physmem.memoryStateTime::REF 7091500000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 2441586750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 2285139 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4730 # Transaction distribution +system.membus.trans_dist::ReadResp 4730 # Transaction distribution +system.membus.trans_dist::ReadExReq 2853 # Transaction distribution +system.membus.trans_dist::ReadExResp 2853 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15166 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15166 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 485312 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 8812000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 70869000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 33146135 # Number of BP lookups +system.cpu.branchPred.condPredicted 17115100 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1582628 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18038083 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15622031 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 86.605827 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6627212 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 191 # Number of system calls +system.cpu.numCycles 424754826 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 273037856 # Number of instructions committed +system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed +system.cpu.discardedOps 4318160 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.555663 # CPI: cycles per instruction +system.cpu.ipc 0.642813 # IPC: instructions per cycle +system.cpu.tickCycles 420995897 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3758929 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 36952 # number of replacements +system.cpu.icache.tags.tagsinuse 1924.941242 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 73208047 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 38889 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1882.487259 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.941242 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939913 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939913 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1488 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 146532763 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146532763 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 73208047 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 73208047 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 73208047 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 73208047 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 73208047 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 625804254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 625804254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 625804254 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 625804254 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000531 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000531 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000531 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16091.649627 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16091.649627 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16091.649627 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16091.649627 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16091.649627 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16091.649627 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 13382365 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 40531 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 40530 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1009 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2869 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2869 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77779 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10029 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 87808 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2488896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 2842112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 2842112 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 23213500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 59031746 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 7495460 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 4198.136947 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 35837 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5644 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.349575 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 353.492029 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.644919 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.010788 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117329 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.128117 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5644 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1251 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4259 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172241 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 363785 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 363785 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 35758 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 35758 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1009 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1009 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 16 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 35774 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 35774 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 35774 # number of overall hits +system.cpu.l2cache.overall_hits::total 35774 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 4773 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4773 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 2853 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2853 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 7626 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7626 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 7626 # number of overall misses +system.cpu.l2cache.overall_misses::total 7626 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 328392750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 328392750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194194500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 194194500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 522587250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 522587250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 522587250 # 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number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.117762 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.117762 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.994423 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.994423 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.175714 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.175714 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.175714 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.175714 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68802.168448 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68802.168448 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68066.771819 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68066.771819 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68527.045633 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68527.045633 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68527.045633 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68527.045633 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 43 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 43 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 43 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 43 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 43 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 43 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4730 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4730 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 2853 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 2853 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7583 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7583 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7583 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7583 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266719500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266719500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158382000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158382000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425101500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 425101500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425101500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 425101500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.116701 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116701 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994423 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994423 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174724 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.174724 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174724 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.174724 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56388.900634 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56388.900634 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55514.195584 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55514.195584 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56059.804827 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56059.804827 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56059.804827 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56059.804827 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.tags.replacements 1353 # number of replacements +system.cpu.dcache.tags.tagsinuse 3085.890933 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168774540 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4510 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37422.292683 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 3085.890933 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.753391 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.753391 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 671 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2433 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 337568172 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337568172 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 86705299 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86705299 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 82047451 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047451 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 10895 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.inst 10895 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.inst 168752750 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168752750 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 168752750 # number of overall hits +system.cpu.dcache.overall_hits::total 168752750 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 2065 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2065 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 5226 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5226 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 7291 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7291 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 7291 # number of overall misses +system.cpu.dcache.overall_misses::total 7291 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 127204208 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 127204208 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 358851000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 358851000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 486055208 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 486055208 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 486055208 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 486055208 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 86707364 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86707364 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 10895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 168760041 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168760041 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 168760041 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168760041 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000064 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.000043 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61600.100726 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61600.100726 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68666.475316 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 68666.475316 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66665.095049 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66665.095049 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66665.095049 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66665.095049 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 1009 # number of writebacks +system.cpu.dcache.writebacks::total 1009 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 424 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2357 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2357 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 2781 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2781 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 2781 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2781 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1641 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1641 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2869 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2869 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 4510 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4510 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 4510 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4510 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100713040 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 100713040 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197262500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 197262500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297975540 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 297975540 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297975540 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 297975540 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61372.967703 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61372.967703 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68756.535378 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68756.535378 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66069.964523 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66069.964523 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66069.964523 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66069.964523 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |