diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
| commit | 84f138ba96201431513eb2ae5f847389ac731aa2 (patch) | |
| tree | 3aee721699295c85e4e0c2d3d4a6bb27595bfabd /tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt | |
| parent | a288c94387b110112461ff5686fa727a43ddbe9c (diff) | |
| download | gem5-84f138ba96201431513eb2ae5f847389ac731aa2.tar.xz | |
stats: update references
Diffstat (limited to 'tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt | 882 |
1 files changed, 442 insertions, 440 deletions
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 521f1135c..0b49d498f 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.211715 # Number of seconds simulated -sim_ticks 211714953000 # Number of ticks simulated -final_tick 211714953000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.225030 # Number of seconds simulated +sim_ticks 225030243000 # Number of ticks simulated +final_tick 225030243000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 271910 # Simulator instruction rate (inst/s) -host_op_rate 326458 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 210840466 # Simulator tick rate (ticks/s) -host_mem_usage 322892 # Number of bytes of host memory used -host_seconds 1004.15 # Real time elapsed on the host -sim_insts 273037857 # Number of instructions simulated -sim_ops 327812214 # Number of ops (including micro ops) simulated +host_inst_rate 131394 # Simulator instruction rate (inst/s) +host_op_rate 157754 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 108291606 # Simulator tick rate (ticks/s) +host_mem_usage 275248 # Number of bytes of host memory used +host_seconds 2078.00 # Real time elapsed on the host +sim_insts 273037855 # Number of instructions simulated +sim_ops 327812212 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 219136 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 266432 # Number of bytes read from this memory -system.physmem.bytes_read::total 485504 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3423 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 485568 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219136 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4163 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7586 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1034750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1258447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2293197 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1034750 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1034750 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1034750 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1258447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2293197 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7586 # Number of read requests accepted +system.physmem.num_reads::total 7587 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 973807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1183983 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2157790 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 973807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 973807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 973807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1183983 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2157790 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7587 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7586 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7587 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 485504 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 485568 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 485504 # Total read bytes from the system interface side +system.physmem.bytesReadSys 485568 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -51,13 +51,13 @@ system.physmem.perBankRdBursts::5 349 # Pe system.physmem.perBankRdBursts::6 171 # Per bank write bursts system.physmem.perBankRdBursts::7 228 # Per bank write bursts system.physmem.perBankRdBursts::8 208 # Per bank write bursts -system.physmem.perBankRdBursts::9 310 # Per bank write bursts +system.physmem.perBankRdBursts::9 309 # Per bank write bursts system.physmem.perBankRdBursts::10 343 # Per bank write bursts system.physmem.perBankRdBursts::11 428 # Per bank write bursts system.physmem.perBankRdBursts::12 553 # Per bank write bursts system.physmem.perBankRdBursts::13 705 # Per bank write bursts -system.physmem.perBankRdBursts::14 638 # Per bank write bursts -system.physmem.perBankRdBursts::15 542 # Per bank write bursts +system.physmem.perBankRdBursts::14 639 # Per bank write bursts +system.physmem.perBankRdBursts::15 543 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 211714708500 # Total gap between requests +system.physmem.totGap 225029996000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7586 # Read request sizes (log2) +system.physmem.readPktSize::6 7587 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6629 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6713 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -187,86 +187,86 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1530 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 316.067974 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 186.296863 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.878934 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 560 36.60% 36.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 363 23.73% 60.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 160 10.46% 70.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 74 4.84% 75.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 70 4.58% 80.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 59 3.86% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 34 2.22% 86.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 28 1.83% 88.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 182 11.90% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1530 # Bytes accessed per row activation -system.physmem.totQLat 52630500 # Total ticks spent queuing -system.physmem.totMemAccLat 194868000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37930000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6937.85 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1511 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 320.084712 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.611752 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 331.049486 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 552 36.53% 36.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 328 21.71% 58.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 178 11.78% 70.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 86 5.69% 75.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 72 4.77% 80.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 49 3.24% 83.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 32 2.12% 85.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 31 2.05% 87.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 183 12.11% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1511 # Bytes accessed per row activation +system.physmem.totQLat 51456750 # Total ticks spent queuing +system.physmem.totMemAccLat 193713000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37935000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6782.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25687.85 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25532.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6048 # Number of row buffer hits during reads +system.physmem.readRowHits 6068 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.73 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.98 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 27908609.08 # Average gap between requests -system.physmem.pageHitRate 79.73 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5080320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2772000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 29659944.11 # Average gap between requests +system.physmem.pageHitRate 79.98 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5012280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2734875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 29881800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 13827746400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5529396150 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 122174691000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 141569591070 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.700877 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 203247000500 # Time in different power states -system.physmem_0.memoryStateTime::REF 7069400000 # Time in different power states +system.physmem_0.refreshEnergy 14697384000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5831471925 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 129898404750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 150464889630 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.664832 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 216095628500 # Time in different power states +system.physmem_0.memoryStateTime::REF 7514000000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1392729000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1413270250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6463800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3526875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 28992600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 6380640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3481500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 29000400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 13827746400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5726317185 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 122001953250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 141595000110 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.820896 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 202960400000 # Time in different power states -system.physmem_1.memoryStateTime::REF 7069400000 # Time in different power states +system.physmem_1.refreshEnergy 14697384000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6004643625 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 129746499750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 150487389915 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.764823 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 215845139250 # Time in different power states +system.physmem_1.memoryStateTime::REF 7514000000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1682763000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1668675750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 32413931 # Number of BP lookups -system.cpu.branchPred.condPredicted 16919661 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 738142 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17496692 # Number of BTB lookups -system.cpu.branchPred.BTBHits 12856502 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 32430290 # Number of BP lookups +system.cpu.branchPred.condPredicted 16924100 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 738493 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17494980 # Number of BTB lookups +system.cpu.branchPred.BTBHits 12858502 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 73.479615 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6512761 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2303892 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2264485 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 39407 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 128263 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 73.498238 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6523127 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 2303930 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2264813 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 39117 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 128237 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,18 +387,18 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 211714953000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 423429906 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 450060486 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 273037857 # Number of instructions committed -system.cpu.committedOps 327812214 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2127081 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 273037855 # Number of instructions committed +system.cpu.committedOps 327812212 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2063972 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.550810 # CPI: cycles per instruction -system.cpu.ipc 0.644824 # IPC: instructions per cycle +system.cpu.cpi 1.648345 # CPI: cycles per instruction +system.cpu.ipc 0.606669 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.op_class_0::IntAlu 104312544 31.82% 31.82% # Class of committed instruction +system.cpu.op_class_0::IntAlu 104312542 31.82% 31.82% # Class of committed instruction system.cpu.op_class_0::IntMult 2145905 0.65% 32.48% # Class of committed instruction system.cpu.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction system.cpu.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction @@ -431,93 +431,93 @@ system.cpu.op_class_0::MemRead 85732248 26.15% 74.87% # Cl system.cpu.op_class_0::MemWrite 82375599 25.13% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 327812214 # Class of committed instruction -system.cpu.tickCycles 420106568 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3323338 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states +system.cpu.op_class_0::total 327812212 # Class of committed instruction +system.cpu.tickCycles 434886518 # Number of cycles that the object actually ticked +system.cpu.idleCycles 15173968 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1355 # number of replacements -system.cpu.dcache.tags.tagsinuse 3085.570959 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168654881 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3086.261687 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168654217 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4512 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37379.184619 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37379.037456 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3085.570959 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.753313 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.753313 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3086.261687 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.753482 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.753482 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 337328856 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 337328856 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 86522107 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86522107 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82047451 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047451 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 63533 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 63533 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 337326818 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337326818 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 86521433 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86521433 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82047456 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047456 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 63538 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 63538 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168569558 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168569558 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168633091 # number of overall hits -system.cpu.dcache.overall_hits::total 168633091 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2060 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2060 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5226 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5226 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 168568889 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168568889 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168632427 # number of overall hits +system.cpu.dcache.overall_hits::total 168632427 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1710 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1710 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5221 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5221 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 7286 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7286 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7291 # number of overall misses -system.cpu.dcache.overall_misses::total 7291 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 136635000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 136635000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 394688000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 394688000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 531323000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 531323000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 531323000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 531323000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86524167 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86524167 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 6931 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6931 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6936 # number of overall misses +system.cpu.dcache.overall_misses::total 6936 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 114932500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 114932500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 393586500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 393586500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 508519000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 508519000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 508519000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 508519000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86523143 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86523143 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 63538 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 63538 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 63543 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 63543 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168576844 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168576844 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168640382 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168640382 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 168575820 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168575820 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168639363 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168639363 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000079 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.000079 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66327.669903 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66327.669903 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75523.918867 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75523.918867 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72923.826517 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72923.826517 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72873.817035 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72873.817035 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.000041 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000041 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000041 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000041 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67211.988304 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67211.988304 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75385.271021 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75385.271021 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73368.777954 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73368.777954 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73315.888120 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73315.888120 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -526,14 +526,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks system.cpu.dcache.writebacks::total 1010 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 421 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 421 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2356 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2356 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2777 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2777 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2777 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2777 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 71 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2351 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2351 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2422 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2422 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2422 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2422 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1639 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1639 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses @@ -544,16 +544,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4509 system.cpu.dcache.demand_mshr_misses::total 4509 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4512 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4512 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109916500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 109916500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219842000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 219842000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 481000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 481000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329758500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 329758500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 330239500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 330239500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 110662500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 110662500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219478500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 219478500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 238000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 238000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 330141000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 330141000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 330379000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 330379000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -564,208 +564,208 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67063.148261 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67063.148261 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76600 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76600 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 160333.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 160333.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73133.399867 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73133.399867 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73191.378546 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73191.378546 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 38168 # number of replacements -system.cpu.icache.tags.tagsinuse 1923.744161 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 69641436 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 40104 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1736.520946 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67518.303844 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67518.303844 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76473.344948 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76473.344948 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73218.230206 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73218.230206 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73222.296099 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73222.296099 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 38188 # number of replacements +system.cpu.icache.tags.tagsinuse 1925.010528 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 69819783 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 40125 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1740.056897 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1923.744161 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939328 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939328 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 276 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1483 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 139403186 # Number of tag accesses -system.cpu.icache.tags.data_accesses 139403186 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 69641436 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 69641436 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 69641436 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 69641436 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 69641436 # number of overall hits -system.cpu.icache.overall_hits::total 69641436 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 40105 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 40105 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 40105 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 40105 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 40105 # number of overall misses -system.cpu.icache.overall_misses::total 40105 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 757528000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 757528000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 757528000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 757528000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 757528000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 757528000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 69681541 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 69681541 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 69681541 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 69681541 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 69681541 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 69681541 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000576 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000576 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000576 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000576 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000576 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000576 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18888.617379 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18888.617379 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18888.617379 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18888.617379 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18888.617379 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18888.617379 # average overall miss latency +system.cpu.icache.tags.occ_blocks::cpu.inst 1925.010528 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939947 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939947 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 277 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 139759943 # Number of tag accesses +system.cpu.icache.tags.data_accesses 139759943 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 69819783 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 69819783 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 69819783 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 69819783 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 69819783 # number of overall hits +system.cpu.icache.overall_hits::total 69819783 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 40126 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 40126 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 40126 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 40126 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 40126 # number of overall misses +system.cpu.icache.overall_misses::total 40126 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 756662500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 756662500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 756662500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 756662500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 756662500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 756662500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 69859909 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 69859909 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 69859909 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 69859909 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 69859909 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 69859909 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000574 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000574 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000574 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000574 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000574 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000574 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18857.162438 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18857.162438 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18857.162438 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18857.162438 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18857.162438 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18857.162438 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 38168 # number of writebacks -system.cpu.icache.writebacks::total 38168 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 40105 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 40105 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 40105 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 40105 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 40105 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 40105 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 717424000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 717424000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 717424000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 717424000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 717424000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 717424000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000576 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000576 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000576 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000576 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000576 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000576 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17888.642314 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17888.642314 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17888.642314 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17888.642314 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17888.642314 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17888.642314 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states +system.cpu.icache.writebacks::writebacks 38188 # number of writebacks +system.cpu.icache.writebacks::total 38188 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 40126 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 40126 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 40126 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 40126 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 40126 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 40126 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 716537500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 716537500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 716537500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 716537500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 716537500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 716537500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000574 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000574 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000574 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17857.187360 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17857.187360 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17857.187360 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17857.187360 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17857.187360 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17857.187360 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4199.701287 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 60529 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5648 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.716891 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 4201.230054 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 60569 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5649 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.722075 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 353.800339 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.579629 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 678.321319 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.010797 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096667 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.020701 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.128165 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5648 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1251 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 354.127692 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3168.434045 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 678.668317 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.010807 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096693 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.020711 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.128211 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5649 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1257 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4262 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172363 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 561366 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 561366 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172394 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 561687 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 561687 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 1010 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 1010 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 23251 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 23251 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::writebacks 23270 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 23270 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36680 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 36680 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 291 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 291 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 36680 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 307 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 36987 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 36680 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 307 # number of overall hits -system.cpu.l2cache.overall_hits::total 36987 # number of overall hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36700 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 36700 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 292 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 292 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 36700 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 308 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 37008 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 36700 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 308 # number of overall hits +system.cpu.l2cache.overall_hits::total 37008 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 2854 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 2854 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65100.496640 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65100.496640 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67876.623377 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67876.623377 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65100.496640 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66213.067499 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65711.046665 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65100.496640 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66213.067499 # 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average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68289.152024 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68289.152024 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64748.977804 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66256.785972 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65576.314749 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64748.977804 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66256.785972 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65576.314749 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 84181 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 39645 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15035 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 41746 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 41767 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 38168 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 38188 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 40105 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 40126 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1642 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118377 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118439 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10379 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 128756 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5009408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 128818 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5012032 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 5362816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 5365440 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 44617 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.339243 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.473458 # Request fanout histogram +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 44638 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.339106 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.473411 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 29481 66.08% 66.08% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 15136 33.92% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 29501 66.09% 66.09% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 15137 33.91% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 44617 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 81248000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 44638 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 81288500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 60156998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 60188498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6789457 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4732 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 4733 # Transaction distribution system.membus.trans_dist::ReadExReq 2854 # Transaction distribution system.membus.trans_dist::ReadExResp 2854 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4732 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15172 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15172 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 485504 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 4733 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15174 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15174 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 485568 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7586 # Request fanout histogram +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 7587 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7586 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7587 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7586 # Request fanout histogram -system.membus.reqLayer0.occupancy 8883500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7587 # Request fanout histogram +system.membus.reqLayer0.occupancy 9083500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 40266000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40284000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |