diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-09-25 07:27:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-09-25 07:27:03 -0400 |
| commit | 806e1fbf0f63d386d4ae80ff0d4ab77e6c37f9d6 (patch) | |
| tree | bf8944a02c194cb657534276190f2a17859b3675 /tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt | |
| parent | a9a7002a3b3ad1e423d16ace826e80574d4ddc4f (diff) | |
| download | gem5-806e1fbf0f63d386d4ae80ff0d4ab77e6c37f9d6.tar.xz | |
stats: Update stats to reflect snoop-filter changes
Diffstat (limited to 'tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt | 486 |
1 files changed, 246 insertions, 240 deletions
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 333ae52c9..5974a793e 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.215506 # Number of seconds simulated -sim_ticks 215505832500 # Number of ticks simulated -final_tick 215505832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.215510 # Number of seconds simulated +sim_ticks 215510486500 # Number of ticks simulated +final_tick 215510486500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114925 # Simulator instruction rate (inst/s) -host_op_rate 137980 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90709005 # Simulator tick rate (ticks/s) -host_mem_usage 317788 # Number of bytes of host memory used -host_seconds 2375.79 # Real time elapsed on the host +host_inst_rate 166248 # Simulator instruction rate (inst/s) +host_op_rate 199599 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 131220473 # Simulator tick rate (ticks/s) +host_mem_usage 326292 # Number of bytes of host memory used +host_seconds 1642.35 # Real time elapsed on the host sim_insts 273037857 # Number of instructions simulated sim_ops 327812214 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 218880 # Nu system.physmem.num_reads::cpu.inst 3420 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory system.physmem.num_reads::total 7582 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1015657 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1236013 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2251670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1015657 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1015657 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1015657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1236013 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2251670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1015635 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1235986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2251621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1015635 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1015635 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1015635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1235986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2251621 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7582 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7582 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 215505593500 # Total gap between requests +system.physmem.totGap 215510247500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6629 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 892 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6628 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 893 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1519 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 318.272548 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.961816 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.159233 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 550 36.21% 36.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 342 22.51% 58.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 179 11.78% 70.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 82 5.40% 75.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 73 4.81% 80.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 43 2.83% 83.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 37 2.44% 85.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 30 1.97% 87.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 183 12.05% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1519 # Bytes accessed per row activation -system.physmem.totQLat 52046750 # Total ticks spent queuing -system.physmem.totMemAccLat 194209250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1514 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 319.408190 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.009179 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 331.260420 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 549 36.26% 36.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 346 22.85% 59.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 166 10.96% 70.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 79 5.22% 75.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 78 5.15% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 48 3.17% 83.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 37 2.44% 86.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 27 1.78% 87.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 184 12.15% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1514 # Bytes accessed per row activation +system.physmem.totQLat 52026250 # Total ticks spent queuing +system.physmem.totMemAccLat 194188750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37910000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6864.51 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6861.81 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25614.51 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25611.81 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.25 # Average system read bandwidth in MiByte/s @@ -216,47 +216,47 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6056 # Number of row buffer hits during reads +system.physmem.readRowHits 6062 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.87 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.95 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28423317.53 # Average gap between requests -system.physmem.pageHitRate 79.87 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4997160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2726625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 28423931.35 # Average gap between requests +system.physmem.pageHitRate 79.95 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5050080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2755500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 29952000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14075415120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5632744275 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 124359177000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 144104965380 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.699601 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 206882994500 # Time in different power states -system.physmem_0.memoryStateTime::REF 7196020000 # Time in different power states +system.physmem_0.refreshEnergy 14075923680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5660638650 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 124339380000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 144113699910 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.715971 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 206848311250 # Time in different power states +system.physmem_0.memoryStateTime::REF 7196280000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1423707500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1464242250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6463800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3526875 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 6388200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3485625 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 28977000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14075415120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5808881115 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 124204671000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 144127934910 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.806188 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 206624169250 # Time in different power states -system.physmem_1.memoryStateTime::REF 7196020000 # Time in different power states +system.physmem_1.refreshEnergy 14075923680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5785657605 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 124229714250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 144130146360 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.792285 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 206662748250 # Time in different power states +system.physmem_1.memoryStateTime::REF 7196280000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1683261250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1649073000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 32816945 # Number of BP lookups -system.cpu.branchPred.condPredicted 16892744 # Number of conditional branches predicted +system.cpu.branchPred.lookups 32816918 # Number of BP lookups +system.cpu.branchPred.condPredicted 16892730 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1463888 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17497063 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15468368 # Number of BTB hits +system.cpu.branchPred.BTBLookups 17497037 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15468342 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.405511 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 88.405494 # BTB Hit Percentage system.cpu.branchPred.usedRAS 6575577 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -377,24 +377,24 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 431011665 # number of cpu cycles simulated +system.cpu.numCycles 431020973 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 273037857 # Number of instructions committed system.cpu.committedOps 327812214 # Number of ops (including micro ops) committed -system.cpu.discardedOps 3889170 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 3889164 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.578578 # CPI: cycles per instruction -system.cpu.ipc 0.633481 # IPC: instructions per cycle -system.cpu.tickCycles 427409330 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3602335 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.578612 # CPI: cycles per instruction +system.cpu.ipc 0.633468 # IPC: instructions per cycle +system.cpu.tickCycles 427416493 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3604480 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 1354 # number of replacements -system.cpu.dcache.tags.tagsinuse 3085.814933 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168714880 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3085.814208 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168714884 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37400.771448 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37400.772334 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3085.814933 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 3085.814208 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.753373 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.753373 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id @@ -404,42 +404,42 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 337448855 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 337448855 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 86582107 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86582107 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82047449 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047449 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 337448859 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337448859 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86582109 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86582109 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82047451 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047451 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 63534 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 63534 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168629556 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168629556 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168693090 # number of overall hits -system.cpu.dcache.overall_hits::total 168693090 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 168629560 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168629560 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168693094 # number of overall hits +system.cpu.dcache.overall_hits::total 168693094 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 2059 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2059 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5228 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5228 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5226 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5226 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 7287 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7287 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7292 # number of overall misses -system.cpu.dcache.overall_misses::total 7292 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 135542000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 135542000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 392317500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 392317500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 527859500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 527859500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 527859500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 527859500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86584166 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86584166 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7285 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7285 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7290 # number of overall misses +system.cpu.dcache.overall_misses::total 7290 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 136254500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 136254500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 393515500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 393515500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 529770000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 529770000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 529770000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 529770000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86584168 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86584168 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 63539 # number of SoftPFReq accesses(hits+misses) @@ -448,10 +448,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168636843 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168636843 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168700382 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168700382 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168636845 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168636845 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168700384 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168700384 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses @@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65829.043225 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 65829.043225 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75041.602907 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75041.602907 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72438.520653 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72438.520653 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72388.850795 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72388.850795 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66175.084993 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66175.084993 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75299.559893 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75299.559893 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72720.658888 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72720.658888 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72670.781893 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72670.781893 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,12 +482,12 @@ system.cpu.dcache.writebacks::writebacks 1010 # nu system.cpu.dcache.writebacks::total 1010 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 421 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 421 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2358 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2358 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2779 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2779 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2779 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2779 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2356 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2356 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2777 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2777 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2777 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2777 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1638 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1638 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses @@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4508 system.cpu.dcache.demand_mshr_misses::total 4508 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109498500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 109498500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 218637500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 218637500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109975000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 109975000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219249000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 219249000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 238000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 238000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 328136000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 328136000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 328374000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 328374000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329224000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 329224000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329462000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 329462000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -518,26 +518,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66848.901099 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66848.901099 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76180.313589 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76180.313589 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67139.804640 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67139.804640 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76393.379791 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76393.379791 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79333.333333 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79333.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72789.707187 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72789.707187 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72794.058967 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72794.058967 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73031.055901 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73031.055901 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73035.247174 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73035.247174 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 36873 # number of replacements -system.cpu.icache.tags.tagsinuse 1923.841153 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 72548906 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1923.840697 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 72548791 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 38809 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1869.383545 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1869.380582 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1923.841153 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939376 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939376 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1923.840697 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939375 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939375 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id @@ -545,44 +545,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 34 system.cpu.icache.tags.age_task_id_blocks_1024::3 276 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1485 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 145214241 # Number of tag accesses -system.cpu.icache.tags.data_accesses 145214241 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 72548906 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 72548906 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 72548906 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 72548906 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 72548906 # number of overall hits -system.cpu.icache.overall_hits::total 72548906 # number of overall hits +system.cpu.icache.tags.tag_accesses 145214011 # Number of tag accesses +system.cpu.icache.tags.data_accesses 145214011 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 72548791 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 72548791 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 72548791 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 72548791 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 72548791 # number of overall hits +system.cpu.icache.overall_hits::total 72548791 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 38810 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 38810 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 38810 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 38810 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 38810 # number of overall misses system.cpu.icache.overall_misses::total 38810 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 726866500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 726866500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 726866500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 726866500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 726866500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 726866500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 72587716 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 72587716 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 72587716 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 72587716 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 72587716 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 72587716 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 740838000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 740838000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 740838000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 740838000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 740838000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 740838000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 72587601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 72587601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 72587601 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 72587601 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 72587601 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 72587601 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000535 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000535 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000535 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000535 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000535 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000535 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18728.845658 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18728.845658 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18728.845658 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18728.845658 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18728.845658 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18728.845658 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19088.843082 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19088.843082 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19088.843082 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19088.843082 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19088.843082 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19088.843082 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -597,34 +597,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 38810 system.cpu.icache.demand_mshr_misses::total 38810 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 38810 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 38810 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 688057500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 688057500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 688057500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 688057500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 688057500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 688057500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 702029000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 702029000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 702029000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 702029000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 702029000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 702029000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000535 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000535 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000535 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17728.871425 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17728.871425 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17728.871425 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17728.871425 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17728.871425 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17728.871425 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18088.868848 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18088.868848 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18088.868848 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18088.868848 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18088.868848 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18088.868848 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4197.344986 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4197.348676 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 57958 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5644 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 10.268958 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 353.814355 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.200376 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 678.330255 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 353.816119 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.200424 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 678.332133 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010798 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096594 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.020701 # Average percentage of cache occupancy @@ -664,18 +664,18 @@ system.cpu.l2cache.demand_misses::total 7626 # nu system.cpu.l2cache.overall_misses::cpu.inst 3422 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses system.cpu.l2cache.overall_misses::total 7626 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 214130000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 214130000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 258275500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 258275500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 104189000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 104189000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 258275500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 318319000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 576594500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 258275500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 318319000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 576594500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 214741500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 214741500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 257334000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 257334000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 104502500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 104502500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 257334000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 319244000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 576578000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 257334000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 319244000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 576578000 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 1010 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 1010 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 2870 # number of ReadExReq accesses(hits+misses) @@ -702,18 +702,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.176035 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088173 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.931944 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.176035 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75028.030834 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75028.030834 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75475.014611 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75475.014611 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77177.037037 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77177.037037 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75475.014611 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75718.125595 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75609.034881 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75475.014611 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75718.125595 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75609.034881 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75242.291521 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75242.291521 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75199.883109 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75199.883109 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77409.259259 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77409.259259 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75199.883109 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75938.154139 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75606.871230 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75199.883109 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75938.154139 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75606.871230 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -744,18 +744,18 @@ system.cpu.l2cache.demand_mshr_misses::total 7582 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3420 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4162 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7582 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 185590000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 185590000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 223941000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 223941000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 88101000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 88101000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 223941000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 273691000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 497632000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 223941000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 273691000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 497632000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 186201500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 186201500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 222999500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 222999500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 88418500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 88418500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 222999500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 274620000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 497619500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 222999500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 274620000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 497619500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.088122 # mshr miss rate for ReadCleanReq accesses @@ -768,19 +768,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.175019 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088122 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.175019 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65028.030834 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65028.030834 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65479.824561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65479.824561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67355.504587 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67355.504587 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65479.824561 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65759.490630 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65633.342126 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65479.824561 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65759.490630 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65633.342126 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65242.291521 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65242.291521 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65204.532164 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65204.532164 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67598.241590 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67598.241590 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65204.532164 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65982.700625 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65631.693485 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65204.532164 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65982.700625 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65631.693485 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 81548 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 38331 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15017 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 40450 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 22200 # Transaction distribution @@ -796,14 +802,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 2837120 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 81548 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.369574 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.482692 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 81548 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 51410 63.04% 63.04% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 30138 36.96% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 81548 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 41784000 # Layer occupancy (ticks) @@ -831,9 +837,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7582 # Request fanout histogram -system.membus.reqLayer0.occupancy 8861000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8866500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 40238250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40241250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |