diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-04-30 14:17:43 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-04-30 14:17:43 -0500 |
| commit | f71fa1715793c764ffa95411e87b73179a7c7b3f (patch) | |
| tree | b4095efe0bda4413326c5860754921b7d8ae78e3 /tests/long/se/30.eon/ref/arm/linux/minor-timing | |
| parent | 42fe2df35495685e616f74ad3342953714c7dcc1 (diff) | |
| download | gem5-f71fa1715793c764ffa95411e87b73179a7c7b3f.tar.xz | |
stats: arm: updates
Diffstat (limited to 'tests/long/se/30.eon/ref/arm/linux/minor-timing')
| -rw-r--r-- | tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt | 716 |
1 files changed, 358 insertions, 358 deletions
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 048a31a06..5070249ec 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.216865 # Number of seconds simulated -sim_ticks 216864820000 # Number of ticks simulated -final_tick 216864820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.216744 # Number of seconds simulated +sim_ticks 216744260000 # Number of ticks simulated +final_tick 216744260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114758 # Simulator instruction rate (inst/s) -host_op_rate 137779 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 91148248 # Simulator tick rate (ticks/s) -host_mem_usage 250616 # Number of bytes of host memory used -host_seconds 2379.25 # Real time elapsed on the host -sim_insts 273037856 # Number of instructions simulated -sim_ops 327812213 # Number of ops (including micro ops) simulated +host_inst_rate 123383 # Simulator instruction rate (inst/s) +host_op_rate 148134 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 97944157 # Simulator tick rate (ticks/s) +host_mem_usage 314844 # Number of bytes of host memory used +host_seconds 2212.94 # Real time elapsed on the host +sim_insts 273037857 # Number of instructions simulated +sim_ops 327812214 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 219008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 218944 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 266368 # Number of bytes read from this memory -system.physmem.bytes_read::total 485376 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219008 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3422 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 485312 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 218944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 218944 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3421 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7584 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1009883 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1228267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2238150 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1009883 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1009883 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1009883 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1228267 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2238150 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7584 # Number of read requests accepted +system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1010149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1228951 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2239100 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1010149 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1010149 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1010149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1228951 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2239100 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7583 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7584 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7583 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 485376 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 485312 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 485376 # Total read bytes from the system interface side +system.physmem.bytesReadSys 485312 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -46,8 +46,8 @@ system.physmem.perBankRdBursts::1 843 # Pe system.physmem.perBankRdBursts::2 628 # Per bank write bursts system.physmem.perBankRdBursts::3 541 # Per bank write bursts system.physmem.perBankRdBursts::4 466 # Per bank write bursts -system.physmem.perBankRdBursts::5 349 # Per bank write bursts -system.physmem.perBankRdBursts::6 172 # Per bank write bursts +system.physmem.perBankRdBursts::5 348 # Per bank write bursts +system.physmem.perBankRdBursts::6 173 # Per bank write bursts system.physmem.perBankRdBursts::7 228 # Per bank write bursts system.physmem.perBankRdBursts::8 209 # Per bank write bursts system.physmem.perBankRdBursts::9 311 # Per bank write bursts @@ -56,7 +56,7 @@ system.physmem.perBankRdBursts::11 428 # Pe system.physmem.perBankRdBursts::12 553 # Per bank write bursts system.physmem.perBankRdBursts::13 706 # Per bank write bursts system.physmem.perBankRdBursts::14 637 # Per bank write bursts -system.physmem.perBankRdBursts::15 541 # Per bank write bursts +system.physmem.perBankRdBursts::15 540 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 216864583500 # Total gap between requests +system.physmem.totGap 216744023500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7584 # Read request sizes (log2) +system.physmem.readPktSize::6 7583 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6625 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 899 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1521 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 318.190664 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.796192 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.520878 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 546 35.90% 35.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 355 23.34% 59.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 175 11.51% 70.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 75 4.93% 75.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 71 4.67% 80.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 52 3.42% 83.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 37 2.43% 86.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 29 1.91% 88.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 181 11.90% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1521 # Bytes accessed per row activation -system.physmem.totQLat 53624000 # Total ticks spent queuing -system.physmem.totMemAccLat 195824000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37920000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7070.68 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1519 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 318.314681 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.160813 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 331.826555 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 551 36.27% 36.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 356 23.44% 59.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 165 10.86% 70.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 80 5.27% 75.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 68 4.48% 80.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 50 3.29% 83.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 36 2.37% 85.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 26 1.71% 87.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 187 12.31% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1519 # Bytes accessed per row activation +system.physmem.totQLat 54921500 # Total ticks spent queuing +system.physmem.totMemAccLat 197102750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37915000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7242.71 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25820.68 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25992.71 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.24 # Average system read bandwidth in MiByte/s @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6058 # Number of row buffer hits during reads +system.physmem.readRowHits 6057 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 79.88 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28595013.65 # Average gap between requests +system.physmem.avgGap 28582885.86 # Average gap between requests system.physmem.pageHitRate 79.88 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5012280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2734875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 29952000 # Energy for read commands per rank (pJ) +system.physmem_0.actEnergy 5027400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2743125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14164413120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5663385765 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 125149854750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 145015352790 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.696011 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 208196147750 # Time in different power states -system.physmem_0.memoryStateTime::REF 7241520000 # Time in different power states +system.physmem_0.refreshEnergy 14156276160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5639665500 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 125095914000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 144929531385 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.684406 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 208108813000 # Time in different power states +system.physmem_0.memoryStateTime::REF 7237360000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1425508750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1394961500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6486480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3539250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 29031600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 6433560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3510375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 28984800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14164413120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5827279860 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 125006088000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 145036838310 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.795085 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 207953796500 # Time in different power states -system.physmem_1.memoryStateTime::REF 7241520000 # Time in different power states +system.physmem_1.refreshEnergy 14156276160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5856004440 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 124906143000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 144957352335 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.812768 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 207790968250 # Time in different power states +system.physmem_1.memoryStateTime::REF 7237360000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1667592250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1713539250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 33219593 # Number of BP lookups -system.cpu.branchPred.condPredicted 17177082 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1581285 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17974979 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15661112 # Number of BTB hits +system.cpu.branchPred.lookups 33185861 # Number of BP lookups +system.cpu.branchPred.condPredicted 17151464 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1557357 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17401044 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15621725 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.127290 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6612086 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 89.774642 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6610647 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,26 +377,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 433729640 # number of cpu cycles simulated +system.cpu.numCycles 433488520 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 273037856 # Number of instructions committed -system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4054236 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 273037857 # Number of instructions committed +system.cpu.committedOps 327812214 # Number of ops (including micro ops) committed +system.cpu.discardedOps 4013329 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.588533 # CPI: cycles per instruction -system.cpu.ipc 0.629512 # IPC: instructions per cycle -system.cpu.tickCycles 430193126 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3536514 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.587650 # CPI: cycles per instruction +system.cpu.ipc 0.629862 # IPC: instructions per cycle +system.cpu.tickCycles 429966989 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3521531 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 1354 # number of replacements -system.cpu.dcache.tags.tagsinuse 3085.769078 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168782221 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3085.753926 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168769445 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37415.699623 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37412.867435 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3085.769078 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.753362 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.753362 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3085.753926 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.753358 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.753358 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id @@ -404,54 +404,54 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 337583521 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 337583521 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 86649433 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86649433 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82047458 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047458 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 63540 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 63540 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 337557971 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337557971 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86636657 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86636657 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82047457 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047457 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 63541 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 63541 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168696891 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168696891 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168760431 # number of overall hits -system.cpu.dcache.overall_hits::total 168760431 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 168684114 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168684114 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168747655 # number of overall hits +system.cpu.dcache.overall_hits::total 168747655 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 2059 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2059 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5219 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5219 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5220 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5220 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 6 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 6 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 7278 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7278 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7284 # number of overall misses -system.cpu.dcache.overall_misses::total 7284 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 136977706 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 136977706 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 400661500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 400661500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 537639206 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 537639206 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 537639206 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 537639206 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86651492 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86651492 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7279 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7279 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7285 # number of overall misses +system.cpu.dcache.overall_misses::total 7285 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 137443456 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 137443456 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 400907250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 400907250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 538350706 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 538350706 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 538350706 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 538350706 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86638716 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86638716 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 63546 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 63546 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 63547 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 63547 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168704169 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168704169 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168767715 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168767715 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168691393 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168691393 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168754940 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168754940 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses @@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66526.326372 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66526.326372 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76769.783483 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76769.783483 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73871.833746 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73871.833746 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73810.983800 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73810.983800 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66752.528412 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66752.528412 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76802.155172 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76802.155172 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73959.432065 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73959.432065 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73898.518325 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73898.518325 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,12 +482,12 @@ system.cpu.dcache.writebacks::writebacks 1010 # nu system.cpu.dcache.writebacks::total 1010 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2349 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2349 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2771 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2771 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2771 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2771 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2350 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2350 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2772 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2772 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2772 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2772 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1637 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1637 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses @@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4507 system.cpu.dcache.demand_mshr_misses::total 4507 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109140792 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 109140792 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 220213500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 220213500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109995542 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 109995542 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 220772750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 220772750 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 320750 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 320750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329354292 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 329354292 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329675042 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 329675042 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 330768292 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 330768292 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 331089042 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 331089042 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -518,71 +518,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66671.222969 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66671.222969 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76729.442509 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76729.442509 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67193.367135 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67193.367135 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76924.303136 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76924.303136 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80187.500000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80187.500000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73076.168627 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73076.168627 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73082.474396 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73082.474396 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73389.902818 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73389.902818 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73395.930392 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73395.930392 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 36897 # number of replacements -system.cpu.icache.tags.tagsinuse 1924.852858 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 73252007 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 38834 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1886.285394 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 36918 # number of replacements +system.cpu.icache.tags.tagsinuse 1924.846019 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 73120141 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 38855 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1881.872114 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1924.852858 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939870 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939870 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.846019 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939866 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939866 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1487 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 274 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1490 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146620518 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146620518 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 73252007 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 73252007 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 73252007 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 73252007 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 73252007 # number of overall hits -system.cpu.icache.overall_hits::total 73252007 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 38835 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 38835 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 38835 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 38835 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 38835 # number of overall misses -system.cpu.icache.overall_misses::total 38835 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 728387498 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 728387498 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 728387498 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 728387498 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 728387498 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 728387498 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 73290842 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 73290842 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 73290842 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 73290842 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 73290842 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 73290842 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000530 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000530 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000530 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000530 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000530 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000530 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18755.954629 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18755.954629 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18755.954629 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18755.954629 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18755.954629 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18755.954629 # average overall miss latency +system.cpu.icache.tags.tag_accesses 146356849 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146356849 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 73120141 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 73120141 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 73120141 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 73120141 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 73120141 # number of overall hits +system.cpu.icache.overall_hits::total 73120141 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 38856 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 38856 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 38856 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 38856 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 38856 # number of overall misses +system.cpu.icache.overall_misses::total 38856 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 728255248 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 728255248 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 728255248 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 728255248 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 728255248 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 728255248 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 73158997 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 73158997 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 73158997 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 73158997 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 73158997 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 73158997 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000531 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000531 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000531 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000531 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000531 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000531 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18742.414247 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18742.414247 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18742.414247 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18742.414247 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18742.414247 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18742.414247 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,123 +591,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38835 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 38835 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 38835 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 38835 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 38835 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 38835 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 668686502 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 668686502 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 668686502 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 668686502 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 668686502 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 668686502 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000530 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000530 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000530 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17218.655903 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17218.655903 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17218.655903 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17218.655903 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17218.655903 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17218.655903 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38856 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 38856 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 38856 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 38856 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 38856 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 38856 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 668527252 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 668527252 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 668527252 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 668527252 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 668527252 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 668527252 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000531 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000531 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000531 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17205.251493 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17205.251493 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17205.251493 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17205.251493 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17205.251493 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17205.251493 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4197.194738 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 35781 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5646 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.337407 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 4198.154832 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 35803 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5645 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.342427 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 353.722054 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.177954 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 678.294730 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 353.729151 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3166.134287 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 678.291394 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010795 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096594 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096623 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.020700 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.128088 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5646 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::total 0.128118 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5645 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 42 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1252 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4259 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172302 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 363364 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 363364 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 35411 # number of ReadReq hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1250 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4260 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172272 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 363531 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 363531 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 35433 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 291 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 35702 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 35724 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 1010 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 1010 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 35411 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 35433 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 307 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 35718 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 35411 # number of overall hits +system.cpu.l2cache.demand_hits::total 35740 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 35433 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 307 # number of overall hits -system.cpu.l2cache.overall_hits::total 35718 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3424 # number of ReadReq misses +system.cpu.l2cache.overall_hits::total 35740 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3423 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 1350 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4774 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4773 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 2854 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 2854 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3424 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 3423 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 4204 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7628 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3424 # number of overall misses +system.cpu.l2cache.demand_misses::total 7627 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3423 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses -system.cpu.l2cache.overall_misses::total 7628 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 258045000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 104755500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 362800500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 217140500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 217140500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 258045000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 321896000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 579941000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 258045000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 321896000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 579941000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 38835 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 7627 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 257633750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 105610250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 363244000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 217699750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 217699750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 257633750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 323310000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 580943750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 257633750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 323310000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 580943750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 38856 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1641 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 40476 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 40497 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 1010 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 1010 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 2870 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 2870 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 38835 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 38856 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4511 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 43346 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 38835 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 43367 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 38856 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4511 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 43346 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.088168 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 43367 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.088095 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.822669 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.117946 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.117861 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994425 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.994425 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088168 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088095 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.931944 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.175979 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088168 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.175871 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088095 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.931944 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.175979 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75363.609813 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77596.666667 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75995.077503 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76082.866153 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76082.866153 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75363.609813 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76568.981922 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76027.923440 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75363.609813 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76568.981922 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76027.923440 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.175871 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75265.483494 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78229.814815 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76103.917871 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76278.819201 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76278.819201 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75265.483494 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76905.328259 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76169.365412 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75265.483494 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76905.328259 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76169.365412 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -725,104 +725,104 @@ system.cpu.l2cache.demand_mshr_hits::total 44 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 42 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 44 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3422 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3421 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1308 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4730 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4729 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2854 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 2854 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3422 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3421 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 4162 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7584 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3422 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7583 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3421 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4162 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7584 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 215060000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 85447750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 300507750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 181443000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 181443000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 215060000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 266890750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 481950750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 215060000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 266890750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 481950750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 7583 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 214664750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 86513250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 301178000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 181997750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 181997750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 214664750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 268511000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 483175750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 214664750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 268511000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 483175750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088043 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.797075 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116859 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116774 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088043 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.174964 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.174856 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088043 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.174964 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62846.288720 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65327.025994 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63532.293869 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63574.982481 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63574.982481 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62846.288720 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64125.600673 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63548.358386 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62846.288720 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64125.600673 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63548.358386 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.174856 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62749.123063 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66141.628440 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63687.460351 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63769.358795 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63769.358795 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62749.123063 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64514.896684 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63718.284320 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62749.123063 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64514.896684 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63718.284320 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 40476 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 40475 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 40497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 40496 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77669 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77711 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10032 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 87701 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2485376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 87743 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2486720 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2838720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2840064 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 44356 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 44377 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 44356 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 44377 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 44356 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 23188000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 44377 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 23198500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 58975998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 59005248 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 7577458 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 4730 # Transaction distribution -system.membus.trans_dist::ReadResp 4730 # Transaction distribution +system.membus.trans_dist::ReadReq 4729 # Transaction distribution +system.membus.trans_dist::ReadResp 4729 # Transaction distribution system.membus.trans_dist::ReadExReq 2854 # Transaction distribution system.membus.trans_dist::ReadExResp 2854 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15168 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15168 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485376 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 485376 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15166 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15166 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7584 # Request fanout histogram +system.membus.snoop_fanout::samples 7583 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7584 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7583 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7584 # Request fanout histogram -system.membus.reqLayer0.occupancy 8969000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7583 # Request fanout histogram +system.membus.reqLayer0.occupancy 8950500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 40262750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40258250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |