stats: Cumulative stats update

This patch updates the stats to reflect the: 1) addition of the
internal queue in SimpleMemory, 2) moving of the memory class outside
FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying
burst size and interface width for the DRAM instead of relying on
cache-line size, 5) performing merging in the DRAM controller write
buffer, and 6) fixing how idle cycles are counted in the atomic and
timing CPU models.

The main reason for bundling them up is to minimise the changeset
size.

1 files changed, 47 insertions, 46 deletions

diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
index 31843ed63..cfe46b65a 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.068375                       # Nu
 sim_ticks                                 68375005500                       # Number of ticks simulated
 final_tick                                68375005500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 171790                       # Simulator instruction rate (inst/s)
-host_op_rate                                   219625                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               43020256                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 254724                       # Number of bytes of host memory used
-host_seconds                                  1589.37                       # Real time elapsed on the host
+host_inst_rate                                 121198                       # Simulator instruction rate (inst/s)
+host_op_rate                                   154946                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               30350947                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 251080                       # Number of bytes of host memory used
+host_seconds                                  2252.81                       # Real time elapsed on the host
 sim_insts                                   273036725                       # Number of instructions simulated
 sim_ops                                     349064449                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            194176                       # Number of bytes read from this memory
@@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total            2839868                       # In
 system.physmem.bw_total::cpu.inst             2839868                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data             3981806                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total                6821674                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          7288                       # Total number of read requests seen
-system.physmem.writeReqs                            0                       # Total number of write requests seen
-system.physmem.cpureqs                           7293                       # Reqs generatd by CPU via cache - shady
+system.physmem.readReqs                          7288                       # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs                            0                       # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts                        7288                       # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts                          0                       # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
 system.physmem.bytesRead                       466432                       # Total number of bytes read from memory
 system.physmem.bytesWritten                         0                       # Total number of bytes written to memory
 system.physmem.bytesConsumedRd                 466432                       # bytesRead derated as per pkt->getSize()
 system.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
+system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by write Q
 system.physmem.neitherReadNorWrite                  5                       # Reqs where no action is needed
 system.physmem.perBankRdReqs::0                   605                       # Track reads on a per bank basis
 system.physmem.perBankRdReqs::1                   802                       # Track reads on a per bank basis
@@ -243,10 +244,10 @@ system.membus.trans_dist::UpgradeReq                5                       # Tr
 system.membus.trans_dist::UpgradeResp               5                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              2821                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             2821                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side        14586                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count                         14586                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side       466432                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size                     466432                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14586                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  14586                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       466432                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total              466432                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                 466432                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.membus.reqLayer0.occupancy             8910500                       # Layer occupancy (ticks)
@@ -575,12 +576,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq            5                       # T
 system.cpu.toL2Bus.trans_dist::UpgradeResp            5                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         2838                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         2838                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side        31674                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side        10263                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count                    41937                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side      1013376                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side       361280                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size               1374656                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        31674                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10263                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             41937                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1013376                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       361280                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total        1374656                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.data_through_bus           1374656                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus          384                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy       11782000                       # Layer occupancy (ticks)
@@ -589,15 +590,15 @@ system.cpu.toL2Bus.respLayer0.occupancy      24379238                       # La
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       7509966                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements                  13946                       # number of replacements
-system.cpu.icache.tags.tagsinuse               1848.498389                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                 37543488                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                  15836                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                2370.768376                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst    1848.498389                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.902587                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.902587                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements             13946                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1848.498389                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            37543488                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             15836                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           2370.768376                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1848.498389                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.902587                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.902587                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst     37543488                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        37543488                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      37543488                       # number of demand (read+write) hits
@@ -673,19 +674,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 22057.528977
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22057.528977                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 22057.528977                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements                     0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse              3937.726706                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                   13182                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs                  5389                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                  2.446094                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse         3937.726706                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              13182                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             5389                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             2.446094                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.tags.occ_blocks::writebacks   375.051576                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   2781.709770                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    780.965360                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2781.709770                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   780.965360                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.011446                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.084891                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.023833                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.120170                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.120170                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst        12788                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data          298                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total          13086                       # number of ReadReq hits
@@ -832,15 +833,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54944.133158
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55178.479079                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55080.920692                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                   1414                       # number of replacements
-system.cpu.dcache.tags.tagsinuse               3101.863625                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                170862922                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                   4608                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs               37079.627170                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    3101.863625                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.757291                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.757291                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements              1414                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          3101.863625                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           170862922                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              4608                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          37079.627170                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  3101.863625                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.757291                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.757291                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data     88809743                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        88809743                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     82031242                       # number of WriteReq hits