stats: Update stats to match cache changes

1 files changed, 166 insertions, 159 deletions

diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
index e29d83073..863619ff4 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.517243                       # Number of seconds simulated
-sim_ticks                                517243165500                       # Number of ticks simulated
-final_tick                               517243165500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.517291                       # Number of seconds simulated
+sim_ticks                                517291025500                       # Number of ticks simulated
+final_tick                               517291025500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 702843                       # Simulator instruction rate (inst/s)
-host_op_rate                                   843789                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1332923086                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 322968                       # Number of bytes of host memory used
-host_seconds                                   388.05                       # Real time elapsed on the host
+host_inst_rate                                 635145                       # Simulator instruction rate (inst/s)
+host_op_rate                                   762516                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1204648551                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 323584                       # Number of bytes of host memory used
+host_seconds                                   429.41                       # Real time elapsed on the host
 sim_insts                                   272739286                       # Number of instructions simulated
 sim_ops                                     327433744                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total          166912                       # Nu
 system.physmem.num_reads::cpu.inst               2608                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               4224                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  6832                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               322695                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               522648                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                  845343                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          322695                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             322695                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              322695                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              522648                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                 845343                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               322666                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               522599                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                  845265                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          322666                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             322666                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              322666                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              522599                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                 845265                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -147,7 +147,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu.numCycles                       1034486331                       # number of cpu cycles simulated
+system.cpu.numCycles                       1034582051                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   272739286                       # Number of instructions committed
@@ -168,7 +168,7 @@ system.cpu.num_mem_refs                     168107847                       # nu
 system.cpu.num_load_insts                    85732248                       # Number of load instructions
 system.cpu.num_store_insts                   82375599                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               1034486330.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               1034582050.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          30563503                       # Number of branches fetched
@@ -208,14 +208,14 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  327812214                       # Class of executed instruction
 system.cpu.dcache.tags.replacements              1332                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3078.444355                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          3078.335714                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           168359617                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              4478                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs          37597.056052                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3078.444355                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.751573                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.751573                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  3078.335714                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.751547                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.751547                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3146                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
@@ -249,14 +249,14 @@ system.cpu.dcache.demand_misses::cpu.data         4476                       # n
 system.cpu.dcache.demand_misses::total           4476                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data         4479                       # number of overall misses
 system.cpu.dcache.overall_misses::total          4479                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     78469000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     78469000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    157423500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    157423500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    235892500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    235892500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    235892500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    235892500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     88052000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     88052000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    177422500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    177422500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    265474500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    265474500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    265474500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    265474500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     86235567                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     86235567                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     82052677                       # number of WriteReq accesses(hits+misses)
@@ -281,14 +281,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000027
 system.cpu.dcache.demand_miss_rate::total     0.000027                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000027                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000027                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48920.822943                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 48920.822943                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.196379                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.196379                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 52701.630920                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 52701.630920                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 52666.331770                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 52666.331770                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54895.261845                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 54895.261845                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61776.636490                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 61776.636490                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 59310.656836                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 59310.656836                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 59270.931011                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 59270.931011                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -315,16 +315,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         4475
 system.cpu.dcache.demand_mshr_misses::total         4475                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         4478                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         4478                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     76826000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     76826000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    154551500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    154551500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       162000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       162000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    231377500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    231377500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    231539500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    231539500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     86402000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     86402000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    174550500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    174550500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       183000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       183000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    260952500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    260952500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    261135500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    261135500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000019                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000019                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for WriteReq accesses
@@ -335,26 +335,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47926.388022                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47926.388022                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53813.196379                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53813.196379                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        54000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        54000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51704.469274                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 51704.469274                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51706.007146                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 51706.007146                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53900.187149                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53900.187149                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        61000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        61000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             13796                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1766.007280                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1765.948116                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           348644750                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             15603                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          22344.725373                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1766.007280                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.862308                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.862308                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1765.948116                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.862279                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.862279                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1807                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           66                       # Occupied blocks per task id
@@ -376,12 +376,12 @@ system.cpu.icache.demand_misses::cpu.inst        15603                       # n
 system.cpu.icache.demand_misses::total          15603                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        15603                       # number of overall misses
 system.cpu.icache.overall_misses::total         15603                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    320168000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    320168000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    320168000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    320168000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    320168000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    320168000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    338446000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    338446000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    338446000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    338446000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    338446000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    338446000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    348660353                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    348660353                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    348660353                       # number of demand (read+write) accesses
@@ -394,12 +394,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000045
 system.cpu.icache.demand_miss_rate::total     0.000045                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000045                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000045                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20519.643658                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 20519.643658                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 20519.643658                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 20519.643658                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 20519.643658                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 20519.643658                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21691.085048                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 21691.085048                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 21691.085048                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 21691.085048                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 21691.085048                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 21691.085048                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -408,44 +408,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks::writebacks        13796                       # number of writebacks
+system.cpu.icache.writebacks::total             13796                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15603                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total        15603                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst        15603                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total        15603                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        15603                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        15603                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    304565000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    304565000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    304565000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    304565000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    304565000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    304565000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    322843000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    322843000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    322843000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    322843000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    322843000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    322843000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000045                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000045                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000045                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000045                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000045                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000045                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19519.643658                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19519.643658                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19519.643658                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 19519.643658                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19519.643658                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 19519.643658                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         3487.764139                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse         3487.622109                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs              19775                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             4882                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             4.050594                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   341.622938                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2407.426609                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   738.714591                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.010426                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.073469                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.022544                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.106438                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks   341.605293                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2407.328378                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   738.688437                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.010425                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.073466                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.022543                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.106434                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024         4882                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           35                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           46                       # Occupied blocks per task id
@@ -455,8 +457,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3543
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.148987                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses           228106                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses          228106                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks          998                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total          998                       # number of Writeback hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks          998                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total          998                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks         6212                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total         6212                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           16                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           16                       # number of ReadExReq hits
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        12995                       # number of ReadCleanReq hits
@@ -481,20 +485,22 @@ system.cpu.l2cache.demand_misses::total          6832                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         2608                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         4224                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         6832                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    150075000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    150075000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    137027500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    137027500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     72007000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     72007000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    137027500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    222082000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    359109500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    137027500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    222082000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    359109500                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks          998                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total          998                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    170070500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    170070500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    155292000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    155292000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     81591000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     81591000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    155292000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    251661500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    406953500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    155292000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    251661500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    406953500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks          998                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total          998                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks         6212                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total         6212                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         2872                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         2872                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        15603                       # number of ReadCleanReq accesses(hits+misses)
@@ -519,18 +525,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.340222                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.167147                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.943278                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.340222                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52547.268908                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52547.268908                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52541.219325                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52541.219325                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52636.695906                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52636.695906                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52541.219325                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52576.231061                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52562.865925                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52541.219325                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52576.231061                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52562.865925                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.494398                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.494398                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.478528                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.478528                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59642.543860                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59642.543860                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.478528                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59578.953598                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 59565.793326                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.478528                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59578.953598                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 59565.793326                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -551,18 +557,18 @@ system.cpu.l2cache.demand_mshr_misses::total         6832
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         2608                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         4224                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         6832                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    121515000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    121515000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    110947500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    110947500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     58327000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     58327000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    110947500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    179842000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    290789500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    110947500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    179842000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    290789500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    141510500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    141510500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    129212000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    129212000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     67911000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     67911000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    129212000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    209421500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    338633500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    129212000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    209421500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    338633500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994429                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994429                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.167147                       # mshr miss rate for ReadCleanReq accesses
@@ -575,18 +581,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.340222
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.167147                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.943278                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.340222                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42547.268908                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42547.268908                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42541.219325                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42541.219325                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42636.695906                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42636.695906                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42541.219325                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42576.231061                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42562.865925                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42541.219325                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42576.231061                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42562.865925                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.494398                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.494398                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.478528                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.478528                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.478528                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49578.953598                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests        35209                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests        15221                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
@@ -595,8 +601,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       #
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadResp         17209                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback          998                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict         6465                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty          998                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         6212                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict          253                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         2872                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         2872                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq        15603                       # Transaction distribution
@@ -604,22 +611,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq         1606
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        37418                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10207                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total             47625                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       998592                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1396160                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       350464                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total            1349056                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total            1746624                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        35209                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.438041                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.496153                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples        20081                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.386335                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.486921                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0              19786     56.20%     56.20% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              15423     43.80%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0              12323     61.37%     61.37% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               7758     38.63%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          35209                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy       18602500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          20081                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       32398500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy      23404500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
@@ -644,9 +651,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                6833                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             7261500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             7281500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           34588500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           34160000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------