regressions: stats update due to decoder changes

1 files changed, 132 insertions, 132 deletions

diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
index e8af9a733..210b47f80 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.068267                       # Nu
 sim_ticks                                 68267465500                       # Number of ticks simulated
 final_tick                                68267465500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 130031                       # Simulator instruction rate (inst/s)
-host_op_rate                                   166236                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               32510221                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 238756                       # Number of bytes of host memory used
-host_seconds                                  2099.88                       # Real time elapsed on the host
+host_inst_rate                                 160764                       # Simulator instruction rate (inst/s)
+host_op_rate                                   205527                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               40194170                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 285344                       # Number of bytes of host memory used
+host_seconds                                  1698.44                       # Real time elapsed on the host
 sim_insts                                   273048375                       # Number of instructions simulated
 sim_ops                                     349076099                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            193920                       # Number of bytes read from this memory
@@ -496,7 +496,7 @@ system.cpu.int_regfile_reads               1769305779                       # nu
 system.cpu.int_regfile_writes               232713829                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                 188383123                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                132609484                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               973808735                       # number of misc regfile reads
+system.cpu.misc_regfile_reads               567370356                       # number of misc regfile reads
 system.cpu.misc_regfile_writes               34426415                       # number of misc regfile writes
 system.cpu.icache.replacements                  13908                       # number of replacements
 system.cpu.icache.tagsinuse               1849.811927                       # Cycle average of tags in use
@@ -582,6 +582,132 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 18468.059323
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18468.059323                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 18468.059323                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                   1414                       # number of replacements
+system.cpu.dcache.tagsinuse               3122.405383                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                170873491                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   4624                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               36953.609645                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    3122.405383                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.762306                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.762306                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     88815229                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        88815229                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     82031562                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       82031562                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        13475                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        13475                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data        13225                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total        13225                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     170846791                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        170846791                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    170846791                       # number of overall hits
+system.cpu.dcache.overall_hits::total       170846791                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         4046                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          4046                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        21103                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        21103                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data        25149                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total          25149                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data        25149                       # number of overall misses
+system.cpu.dcache.overall_misses::total         25149                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    164690000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    164690000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    831954164                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    831954164                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       115000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       115000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    996644164                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    996644164                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    996644164                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    996644164                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     88819275                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     88819275                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     82052665                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     82052665                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        13477                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        13477                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data        13225                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total        13225                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    170871940                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    170871940                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    170871940                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    170871940                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000046                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000046                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000257                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000257                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000148                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000148                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000147                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000147                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000147                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000147                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40704.399407                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 40704.399407                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39423.502061                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 39423.502061                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        57500                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        57500                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 39629.574297                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 39629.574297                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 39629.574297                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 39629.574297                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        13562                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          751                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               431                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              12                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    31.466357                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    62.583333                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks         1040                       # number of writebacks
+system.cpu.dcache.writebacks::total              1040                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data         2234                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total         2234                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        18291                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        18291                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        20525                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        20525                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        20525                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        20525                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1812                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total         1812                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2812                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         2812                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         4624                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         4624                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         4624                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         4624                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     79757000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     79757000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    131966500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    131966500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    211723500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    211723500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    211723500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    211723500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000020                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000020                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000034                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000034                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44016.004415                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44016.004415                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46929.765292                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46929.765292                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45787.954152                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 45787.954152                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45787.954152                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 45787.954152                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse              3959.582107                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                   13162                       # Total number of references to valid blocks.
@@ -727,131 +853,5 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36140.626733
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34915.655730                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35424.311635                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                   1414                       # number of replacements
-system.cpu.dcache.tagsinuse               3122.405383                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                170873491                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                   4624                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs               36953.609645                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    3122.405383                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.762306                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.762306                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     88815229                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        88815229                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     82031562                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       82031562                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        13475                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        13475                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data        13225                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total        13225                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     170846791                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        170846791                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    170846791                       # number of overall hits
-system.cpu.dcache.overall_hits::total       170846791                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         4046                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          4046                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        21103                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        21103                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data        25149                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total          25149                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data        25149                       # number of overall misses
-system.cpu.dcache.overall_misses::total         25149                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    164690000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    164690000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    831954164                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    831954164                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       115000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       115000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    996644164                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    996644164                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    996644164                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    996644164                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     88819275                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     88819275                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     82052665                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     82052665                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        13477                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        13477                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data        13225                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total        13225                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    170871940                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    170871940                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    170871940                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    170871940                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000046                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000046                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000257                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000257                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000148                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000148                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000147                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000147                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000147                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000147                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40704.399407                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 40704.399407                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39423.502061                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 39423.502061                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        57500                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        57500                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 39629.574297                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 39629.574297                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 39629.574297                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 39629.574297                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        13562                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets          751                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               431                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              12                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    31.466357                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    62.583333                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks         1040                       # number of writebacks
-system.cpu.dcache.writebacks::total              1040                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data         2234                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total         2234                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        18291                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        18291                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        20525                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        20525                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        20525                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        20525                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1812                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total         1812                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2812                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         2812                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         4624                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         4624                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         4624                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         4624                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     79757000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     79757000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    131966500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    131966500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    211723500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    211723500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    211723500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    211723500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000020                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000020                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000034                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000034                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44016.004415                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44016.004415                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46929.765292                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46929.765292                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45787.954152                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 45787.954152                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45787.954152                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 45787.954152                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------