stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee

4 files changed, 74 insertions, 20 deletions

diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
index 787a34237..521f1135c 100644
--- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
@@ -4,15 +4,16 @@ sim_seconds                                  0.211715                       # Nu
 sim_ticks                                211714953000                       # Number of ticks simulated
 final_tick                               211714953000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 119593                       # Simulator instruction rate (inst/s)
-host_op_rate                                   143584                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               92732901                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 275300                       # Number of bytes of host memory used
-host_seconds                                  2283.06                       # Real time elapsed on the host
+host_inst_rate                                 271910                       # Simulator instruction rate (inst/s)
+host_op_rate                                   326458                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              210840466                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 322892                       # Number of bytes of host memory used
+host_seconds                                  1004.15                       # Real time elapsed on the host
 sim_insts                                   273037857                       # Number of instructions simulated
 sim_ops                                     327812214                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 211714953000                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst            219072                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            266432                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               485504                       # Number of bytes read from this memory
@@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF      7069400000                       # Ti
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT      1682763000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 211714953000                       # Cumulative time (in ticks) in various power states
 system.cpu.branchPred.lookups                32413931                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          16919661                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            738142                       # Number of conditional branches incorrect
@@ -264,6 +266,7 @@ system.cpu.branchPred.indirectHits            2264485                       # Nu
 system.cpu.branchPred.indirectMisses            39407                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted       128263                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 211714953000                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -293,6 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 211714953000                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -322,6 +326,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 211714953000                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -351,6 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 211714953000                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -381,6 +387,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON    211714953000                       # Cumulative time (in ticks) in various power states
 system.cpu.numCycles                        423429906                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
@@ -427,6 +434,7 @@ system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Cl
 system.cpu.op_class_0::total                327812214                       # Class of committed instruction
 system.cpu.tickCycles                       420106568                       # Number of cycles that the object actually ticked
 system.cpu.idleCycles                         3323338                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 211714953000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements              1355                       # number of replacements
 system.cpu.dcache.tags.tagsinuse          3085.570959                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           168654881                       # Total number of references to valid blocks.
@@ -445,6 +453,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4         2431
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.770752                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses         337328856                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses        337328856                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 211714953000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data     86522107                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        86522107                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     82047451                       # number of WriteReq hits
@@ -565,6 +574,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73133.399867
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 73133.399867                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73191.378546                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 73191.378546                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 211714953000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements             38168                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1923.744161                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            69641436                       # Total number of references to valid blocks.
@@ -583,6 +593,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4         1483
 system.cpu.icache.tags.occ_task_id_percent::1024     0.945312                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses         139403186                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses        139403186                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 211714953000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.ReadReq_hits::cpu.inst     69641436                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        69641436                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      69641436                       # number of demand (read+write) hits
@@ -651,6 +662,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17888.642314
 system.cpu.icache.demand_avg_mshr_miss_latency::total 17888.642314                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17888.642314                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 17888.642314                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 211714953000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse         4199.701287                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs              60529                       # Total number of references to valid blocks.
@@ -673,6 +685,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4262
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.172363                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses           561366                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses          561366                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 211714953000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks         1010                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total         1010                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks        23251                       # number of WritebackClean hits
@@ -823,6 +836,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests        15034
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 211714953000                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp         41746                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty         1010                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean        38168                       # Transaction distribution
@@ -855,6 +869,7 @@ system.cpu.toL2Bus.respLayer0.occupancy      60156998                       # La
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       6789457                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 211714953000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp               4732                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              2854                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             2854                       # Transaction distribution
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
index 14b00e16f..f64410488 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -4,15 +4,16 @@ sim_seconds                                  0.111754                       # Nu
 sim_ticks                                111753553500                       # Number of ticks simulated
 final_tick                               111753553500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 210028                       # Simulator instruction rate (inst/s)
-host_op_rate                                   252162                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               85964130                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 334160                       # Number of bytes of host memory used
-host_seconds                                  1300.00                       # Real time elapsed on the host
+host_inst_rate                                 201687                       # Simulator instruction rate (inst/s)
+host_op_rate                                   242148                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               82550264                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 334820                       # Number of bytes of host memory used
+host_seconds                                  1353.76                       # Real time elapsed on the host
 sim_insts                                   273037220                       # Number of instructions simulated
 sim_ops                                     327811602                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 111753553500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst            620544                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           4626112                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.l2cache.prefetcher       168832                       # Number of bytes read from this memory
@@ -254,6 +255,7 @@ system.physmem_1.memoryStateTime::REF      3731520000                       # Ti
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT     12405217621                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 111753553500                       # Cumulative time (in ticks) in various power states
 system.cpu.branchPred.lookups                35971731                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          19265386                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            984189                       # Number of conditional branches incorrect
@@ -268,6 +270,7 @@ system.cpu.branchPred.indirectHits            2473442                       # Nu
 system.cpu.branchPred.indirectMisses            43901                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted       128855                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -297,6 +300,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -326,6 +330,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -355,6 +360,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -385,6 +391,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON    111753553500                       # Cumulative time (in ticks) in various power states
 system.cpu.numCycles                        223507108                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
@@ -676,6 +683,7 @@ system.cpu.cc_regfile_reads                1279432977                       # nu
 system.cpu.cc_regfile_writes                 80060950                       # number of cc regfile writes
 system.cpu.misc_regfile_reads              1056766060                       # number of misc regfile reads
 system.cpu.misc_regfile_writes               34421755                       # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 111753553500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements           1542955                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.836799                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           162076726                       # Total number of references to valid blocks.
@@ -693,6 +701,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4            1
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses         333528119                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses        333528119                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 111753553500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data     81065236                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        81065236                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     80920030                       # number of WriteReq hits
@@ -823,6 +832,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11098.570877
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 11098.570877                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11098.942385                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 11098.942385                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 111753553500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements            726201                       # number of replacements
 system.cpu.icache.tags.tagsinuse           511.803602                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            81470529                       # Total number of references to valid blocks.
@@ -841,6 +851,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4           69
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses         165133375                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses        165133375                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 111753553500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.ReadReq_hits::cpu.inst     81470529                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        81470529                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      81470529                       # number of demand (read+write) hits
@@ -915,12 +926,14 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  8406.318013
 system.cpu.icache.demand_avg_mshr_miss_latency::total  8406.318013                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  8406.318013                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total  8406.318013                       # average overall mshr miss latency
+system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 111753553500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.prefetcher.num_hwpf_issued       402434                       # number of hwpf issued
 system.cpu.l2cache.prefetcher.pfIdentified       402547                       # number of prefetch candidates identified
 system.cpu.l2cache.prefetcher.pfBufferHit          102                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
 system.cpu.l2cache.prefetcher.pfSpanPage        28085                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 111753553500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse         5603.177963                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            3041133                       # Total number of references to valid blocks.
@@ -948,6 +961,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1022     0.030334
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.381653                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses         69530063                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses        69530063                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 111753553500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks       968360                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total       968360                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks      1046226                       # number of WritebackClean hits
@@ -1132,6 +1146,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests       254586
 system.cpu.toL2Bus.snoop_filter.tot_snoops       130262                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops        52910                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops        77352                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 111753553500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp       2049447                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty       968360                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean      1300796                       # Transaction distribution
@@ -1167,6 +1182,7 @@ system.cpu.toL2Bus.respLayer0.occupancy    1090392888                       # La
 system.cpu.toL2Bus.respLayer0.utilization          1.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy    2315538337                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.1                       # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 111753553500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp              83887                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq               13                       # Transaction distribution
 system.membus.trans_dist::ReadExReq               730                       # Transaction distribution
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
index ae8086be1..ddaf7206c 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
@@ -4,15 +4,16 @@ sim_seconds                                  0.201717                       # Nu
 sim_ticks                                201717314000                       # Number of ticks simulated
 final_tick                               201717314000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1495302                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1795276                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1104713261                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 309028                       # Number of bytes of host memory used
-host_seconds                                   182.60                       # Real time elapsed on the host
+host_inst_rate                                1421524                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1706697                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1050207028                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 310740                       # Number of bytes of host memory used
+host_seconds                                   192.07                       # Real time elapsed on the host
 sim_insts                                   273037595                       # Number of instructions simulated
 sim_ops                                     327811950                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 201717314000                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst        1394641096                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         480709216                       # Number of bytes read from this memory
 system.physmem.bytes_read::total           1875350312                       # Number of bytes read from this memory
@@ -35,7 +36,9 @@ system.physmem.bw_write::total             1983209845                       # Wr
 system.physmem.bw_total::cpu.inst          6913839315                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data          4366293411                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total            11280132726                       # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 201717314000                       # Cumulative time (in ticks) in various power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -65,6 +68,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -94,6 +98,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -123,6 +128,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -153,6 +159,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON    201717314000                       # Cumulative time (in ticks) in various power states
 system.cpu.numCycles                        403434629                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
@@ -213,6 +220,7 @@ system.cpu.op_class::MemWrite                82375594     25.13%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  327812145                       # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 201717314000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq           434895828                       # Transaction distribution
 system.membus.trans_dist::ReadResp          434906723                       # Transaction distribution
 system.membus.trans_dist::WriteReq           82052672                       # Transaction distribution
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
index fadffed88..ea2a43ab9 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
@@ -4,15 +4,16 @@ sim_seconds                                  0.517291                       # Nu
 sim_ticks                                517291025500                       # Number of ticks simulated
 final_tick                               517291025500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 977708                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1173775                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1854370201                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 319164                       # Number of bytes of host memory used
-host_seconds                                   278.96                       # Real time elapsed on the host
+host_inst_rate                                 968617                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1162861                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1837127354                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 320856                       # Number of bytes of host memory used
+host_seconds                                   281.58                       # Real time elapsed on the host
 sim_insts                                   272739286                       # Number of instructions simulated
 sim_ops                                     327433744                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 517291025500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst            166912                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            270336                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               437248                       # Number of bytes read from this memory
@@ -29,7 +30,9 @@ system.physmem.bw_inst_read::total             322666                       # In
 system.physmem.bw_total::cpu.inst              322666                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data              522599                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total                 845265                       # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 517291025500                       # Cumulative time (in ticks) in various power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -59,6 +62,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -88,6 +92,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -117,6 +122,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -147,6 +153,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON    517291025500                       # Cumulative time (in ticks) in various power states
 system.cpu.numCycles                       1034582051                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
@@ -207,6 +214,7 @@ system.cpu.op_class::MemWrite                82375599     25.13%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  327812214                       # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements              1332                       # number of replacements
 system.cpu.dcache.tags.tagsinuse          3078.335714                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           168359617                       # Total number of references to valid blocks.
@@ -225,6 +233,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4         2428
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.768066                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses         336732670                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses        336732670                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 517291025500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data     86233963                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        86233963                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     82049805                       # number of WriteReq hits
@@ -343,6 +352,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements             13796                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1765.948116                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           348644750                       # Total number of references to valid blocks.
@@ -361,6 +371,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4         1524
 system.cpu.icache.tags.occ_task_id_percent::1024     0.882324                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses         697336309                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses        697336309                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 517291025500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.ReadReq_hits::cpu.inst    348644750                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       348644750                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     348644750                       # number of demand (read+write) hits
@@ -429,6 +440,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048
 system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse         3487.622109                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs              19775                       # Total number of references to valid blocks.
@@ -451,6 +463,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3543
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.148987                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses           228106                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses          228106                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 517291025500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks          998                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total          998                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks         6212                       # number of WritebackClean hits
@@ -591,6 +604,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests         7665
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 517291025500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp         17209                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty          998                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean        13796                       # Transaction distribution
@@ -623,6 +637,7 @@ system.cpu.toL2Bus.respLayer0.occupancy      23404500                       # La
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       6717000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 517291025500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp               3976                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              2856                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             2856                       # Transaction distribution