diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-09-25 07:27:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-09-25 07:27:03 -0400 |
| commit | 806e1fbf0f63d386d4ae80ff0d4ab77e6c37f9d6 (patch) | |
| tree | bf8944a02c194cb657534276190f2a17859b3675 /tests/long/se/30.eon/ref/arm | |
| parent | a9a7002a3b3ad1e423d16ace826e80574d4ddc4f (diff) | |
| download | gem5-806e1fbf0f63d386d4ae80ff0d4ab77e6c37f9d6.tar.xz | |
stats: Update stats to reflect snoop-filter changes
Diffstat (limited to 'tests/long/se/30.eon/ref/arm')
3 files changed, 990 insertions, 971 deletions
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 333ae52c9..5974a793e 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.215506 # Number of seconds simulated -sim_ticks 215505832500 # Number of ticks simulated -final_tick 215505832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.215510 # Number of seconds simulated +sim_ticks 215510486500 # Number of ticks simulated +final_tick 215510486500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114925 # Simulator instruction rate (inst/s) -host_op_rate 137980 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90709005 # Simulator tick rate (ticks/s) -host_mem_usage 317788 # Number of bytes of host memory used -host_seconds 2375.79 # Real time elapsed on the host +host_inst_rate 166248 # Simulator instruction rate (inst/s) +host_op_rate 199599 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 131220473 # Simulator tick rate (ticks/s) +host_mem_usage 326292 # Number of bytes of host memory used +host_seconds 1642.35 # Real time elapsed on the host sim_insts 273037857 # Number of instructions simulated sim_ops 327812214 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 218880 # Nu system.physmem.num_reads::cpu.inst 3420 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory system.physmem.num_reads::total 7582 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1015657 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1236013 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2251670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1015657 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1015657 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1015657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1236013 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2251670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1015635 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1235986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2251621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1015635 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1015635 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1015635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1235986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2251621 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7582 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7582 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 215505593500 # Total gap between requests +system.physmem.totGap 215510247500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6629 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 892 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6628 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 893 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1519 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 318.272548 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.961816 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.159233 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 550 36.21% 36.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 342 22.51% 58.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 179 11.78% 70.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 82 5.40% 75.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 73 4.81% 80.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 43 2.83% 83.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 37 2.44% 85.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 30 1.97% 87.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 183 12.05% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1519 # Bytes accessed per row activation -system.physmem.totQLat 52046750 # Total ticks spent queuing -system.physmem.totMemAccLat 194209250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1514 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 319.408190 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.009179 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 331.260420 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 549 36.26% 36.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 346 22.85% 59.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 166 10.96% 70.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 79 5.22% 75.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 78 5.15% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 48 3.17% 83.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 37 2.44% 86.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 27 1.78% 87.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 184 12.15% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1514 # Bytes accessed per row activation +system.physmem.totQLat 52026250 # Total ticks spent queuing +system.physmem.totMemAccLat 194188750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37910000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6864.51 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6861.81 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25614.51 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25611.81 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.25 # Average system read bandwidth in MiByte/s @@ -216,47 +216,47 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6056 # Number of row buffer hits during reads +system.physmem.readRowHits 6062 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.87 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.95 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28423317.53 # Average gap between requests -system.physmem.pageHitRate 79.87 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4997160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2726625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 28423931.35 # Average gap between requests +system.physmem.pageHitRate 79.95 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5050080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2755500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 29952000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14075415120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5632744275 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 124359177000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 144104965380 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.699601 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 206882994500 # Time in different power states -system.physmem_0.memoryStateTime::REF 7196020000 # Time in different power states +system.physmem_0.refreshEnergy 14075923680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5660638650 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 124339380000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 144113699910 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.715971 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 206848311250 # Time in different power states +system.physmem_0.memoryStateTime::REF 7196280000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1423707500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1464242250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6463800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3526875 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 6388200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3485625 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 28977000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14075415120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5808881115 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 124204671000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 144127934910 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.806188 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 206624169250 # Time in different power states -system.physmem_1.memoryStateTime::REF 7196020000 # Time in different power states +system.physmem_1.refreshEnergy 14075923680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5785657605 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 124229714250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 144130146360 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.792285 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 206662748250 # Time in different power states +system.physmem_1.memoryStateTime::REF 7196280000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1683261250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1649073000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 32816945 # Number of BP lookups -system.cpu.branchPred.condPredicted 16892744 # Number of conditional branches predicted +system.cpu.branchPred.lookups 32816918 # Number of BP lookups +system.cpu.branchPred.condPredicted 16892730 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1463888 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17497063 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15468368 # Number of BTB hits +system.cpu.branchPred.BTBLookups 17497037 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15468342 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.405511 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 88.405494 # BTB Hit Percentage system.cpu.branchPred.usedRAS 6575577 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -377,24 +377,24 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 431011665 # number of cpu cycles simulated +system.cpu.numCycles 431020973 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 273037857 # Number of instructions committed system.cpu.committedOps 327812214 # Number of ops (including micro ops) committed -system.cpu.discardedOps 3889170 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 3889164 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.578578 # CPI: cycles per instruction -system.cpu.ipc 0.633481 # IPC: instructions per cycle -system.cpu.tickCycles 427409330 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3602335 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.578612 # CPI: cycles per instruction +system.cpu.ipc 0.633468 # IPC: instructions per cycle +system.cpu.tickCycles 427416493 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3604480 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 1354 # number of replacements -system.cpu.dcache.tags.tagsinuse 3085.814933 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168714880 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3085.814208 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168714884 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37400.771448 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37400.772334 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3085.814933 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 3085.814208 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.753373 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.753373 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id @@ -404,42 +404,42 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 337448855 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 337448855 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 86582107 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86582107 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82047449 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047449 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 337448859 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337448859 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86582109 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86582109 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82047451 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047451 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 63534 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 63534 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168629556 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168629556 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168693090 # number of overall hits -system.cpu.dcache.overall_hits::total 168693090 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 168629560 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168629560 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168693094 # number of overall hits +system.cpu.dcache.overall_hits::total 168693094 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 2059 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2059 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5228 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5228 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5226 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5226 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 7287 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7287 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7292 # number of overall misses -system.cpu.dcache.overall_misses::total 7292 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 135542000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 135542000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 392317500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 392317500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 527859500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 527859500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 527859500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 527859500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86584166 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86584166 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7285 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7285 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7290 # number of overall misses +system.cpu.dcache.overall_misses::total 7290 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 136254500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 136254500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 393515500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 393515500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 529770000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 529770000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 529770000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 529770000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86584168 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86584168 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 63539 # number of SoftPFReq accesses(hits+misses) @@ -448,10 +448,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168636843 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168636843 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168700382 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168700382 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168636845 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168636845 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168700384 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168700384 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses @@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65829.043225 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 65829.043225 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75041.602907 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75041.602907 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72438.520653 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72438.520653 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72388.850795 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72388.850795 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66175.084993 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66175.084993 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75299.559893 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75299.559893 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72720.658888 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72720.658888 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72670.781893 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72670.781893 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,12 +482,12 @@ system.cpu.dcache.writebacks::writebacks 1010 # nu system.cpu.dcache.writebacks::total 1010 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 421 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 421 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2358 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2358 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2779 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2779 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2779 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2779 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2356 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2356 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2777 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2777 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2777 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2777 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1638 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1638 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses @@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4508 system.cpu.dcache.demand_mshr_misses::total 4508 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109498500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 109498500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 218637500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 218637500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109975000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 109975000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219249000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 219249000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 238000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 238000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 328136000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 328136000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 328374000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 328374000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329224000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 329224000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329462000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 329462000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -518,26 +518,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66848.901099 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66848.901099 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76180.313589 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76180.313589 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67139.804640 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67139.804640 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76393.379791 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76393.379791 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79333.333333 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79333.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72789.707187 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72789.707187 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72794.058967 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72794.058967 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73031.055901 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73031.055901 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73035.247174 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73035.247174 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 36873 # number of replacements -system.cpu.icache.tags.tagsinuse 1923.841153 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 72548906 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1923.840697 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 72548791 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 38809 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1869.383545 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1869.380582 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1923.841153 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939376 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939376 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1923.840697 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939375 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939375 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id @@ -545,44 +545,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 34 system.cpu.icache.tags.age_task_id_blocks_1024::3 276 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1485 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 145214241 # Number of tag accesses -system.cpu.icache.tags.data_accesses 145214241 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 72548906 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 72548906 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 72548906 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 72548906 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 72548906 # number of overall hits -system.cpu.icache.overall_hits::total 72548906 # number of overall hits +system.cpu.icache.tags.tag_accesses 145214011 # Number of tag accesses +system.cpu.icache.tags.data_accesses 145214011 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 72548791 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 72548791 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 72548791 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 72548791 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 72548791 # number of overall hits +system.cpu.icache.overall_hits::total 72548791 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 38810 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 38810 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 38810 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 38810 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 38810 # number of overall misses system.cpu.icache.overall_misses::total 38810 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 726866500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 726866500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 726866500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 726866500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 726866500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 726866500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 72587716 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 72587716 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 72587716 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 72587716 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 72587716 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 72587716 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 740838000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 740838000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 740838000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 740838000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 740838000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 740838000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 72587601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 72587601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 72587601 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 72587601 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 72587601 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 72587601 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000535 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000535 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000535 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000535 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000535 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000535 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18728.845658 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18728.845658 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18728.845658 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18728.845658 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18728.845658 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18728.845658 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19088.843082 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19088.843082 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19088.843082 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19088.843082 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19088.843082 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19088.843082 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -597,34 +597,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 38810 system.cpu.icache.demand_mshr_misses::total 38810 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 38810 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 38810 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 688057500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 688057500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 688057500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 688057500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 688057500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 688057500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 702029000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 702029000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 702029000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 702029000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 702029000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 702029000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000535 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000535 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000535 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17728.871425 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17728.871425 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17728.871425 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17728.871425 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17728.871425 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17728.871425 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18088.868848 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18088.868848 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18088.868848 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18088.868848 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18088.868848 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18088.868848 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4197.344986 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4197.348676 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 57958 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5644 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 10.268958 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 353.814355 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.200376 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 678.330255 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 353.816119 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.200424 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 678.332133 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010798 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096594 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.020701 # Average percentage of cache occupancy @@ -664,18 +664,18 @@ system.cpu.l2cache.demand_misses::total 7626 # nu system.cpu.l2cache.overall_misses::cpu.inst 3422 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses system.cpu.l2cache.overall_misses::total 7626 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 214130000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 214130000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 258275500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 258275500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 104189000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 104189000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 258275500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 318319000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 576594500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 258275500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 318319000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 576594500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 214741500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 214741500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 257334000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 257334000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 104502500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 104502500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 257334000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 319244000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 576578000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 257334000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 319244000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 576578000 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 1010 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 1010 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 2870 # number of ReadExReq accesses(hits+misses) @@ -702,18 +702,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.176035 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088173 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.931944 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.176035 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75028.030834 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75028.030834 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75475.014611 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75475.014611 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77177.037037 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77177.037037 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75475.014611 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75718.125595 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75609.034881 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75475.014611 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75718.125595 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75609.034881 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75242.291521 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75242.291521 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75199.883109 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75199.883109 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77409.259259 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77409.259259 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75199.883109 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75938.154139 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75606.871230 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75199.883109 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75938.154139 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75606.871230 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -744,18 +744,18 @@ system.cpu.l2cache.demand_mshr_misses::total 7582 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3420 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4162 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7582 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 185590000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 185590000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 223941000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 223941000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 88101000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 88101000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 223941000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 273691000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 497632000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 223941000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 273691000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 497632000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 186201500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 186201500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 222999500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 222999500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 88418500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 88418500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 222999500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 274620000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 497619500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 222999500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 274620000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 497619500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.088122 # mshr miss rate for ReadCleanReq accesses @@ -768,19 +768,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.175019 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088122 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.175019 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65028.030834 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65028.030834 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65479.824561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65479.824561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67355.504587 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67355.504587 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65479.824561 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65759.490630 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65633.342126 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65479.824561 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65759.490630 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65633.342126 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65242.291521 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65242.291521 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65204.532164 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65204.532164 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67598.241590 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67598.241590 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65204.532164 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65982.700625 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65631.693485 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65204.532164 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65982.700625 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65631.693485 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 81548 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 38331 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15017 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 40450 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 22200 # Transaction distribution @@ -796,14 +802,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 2837120 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 81548 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.369574 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.482692 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 81548 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 51410 63.04% 63.04% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 30138 36.96% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 81548 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 41784000 # Layer occupancy (ticks) @@ -831,9 +837,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7582 # Request fanout histogram -system.membus.reqLayer0.occupancy 8861000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8866500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 40238250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40241250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index c456278d9..b3c953357 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.112687 # Number of seconds simulated -sim_ticks 112687034500 # Number of ticks simulated -final_tick 112687034500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.112728 # Number of seconds simulated +sim_ticks 112728298500 # Number of ticks simulated +final_tick 112728298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 126437 # Simulator instruction rate (inst/s) -host_op_rate 151802 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52182660 # Simulator tick rate (ticks/s) -host_mem_usage 327844 # Number of bytes of host memory used -host_seconds 2159.47 # Real time elapsed on the host +host_inst_rate 116763 # Simulator instruction rate (inst/s) +host_op_rate 140187 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48207604 # Simulator tick rate (ticks/s) +host_mem_usage 330392 # Number of bytes of host memory used +host_seconds 2338.39 # Real time elapsed on the host sim_insts 273037220 # Number of instructions simulated sim_ops 327811602 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 187072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 112448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 169152 # Number of bytes read from this memory -system.physmem.bytes_read::total 468672 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 187072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 187072 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2923 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1757 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 2643 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7323 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1660102 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 997879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 1501078 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4159059 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1660102 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1660102 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1660102 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 997879 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 1501078 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4159059 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7323 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 187008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 169408 # Number of bytes read from this memory +system.physmem.bytes_read::total 469184 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 187008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 187008 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2922 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1762 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2647 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7331 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1658927 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1000352 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1502799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4162078 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1658927 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1658927 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1658927 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1000352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1502799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4162078 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7331 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7323 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7331 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 468672 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 469184 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 468672 # Total read bytes from the system interface side +system.physmem.bytesReadSys 469184 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -50,16 +50,16 @@ system.physmem.perBankRdBursts::1 789 # Pe system.physmem.perBankRdBursts::2 601 # Per bank write bursts system.physmem.perBankRdBursts::3 520 # Per bank write bursts system.physmem.perBankRdBursts::4 444 # Per bank write bursts -system.physmem.perBankRdBursts::5 346 # Per bank write bursts +system.physmem.perBankRdBursts::5 345 # Per bank write bursts system.physmem.perBankRdBursts::6 153 # Per bank write bursts -system.physmem.perBankRdBursts::7 251 # Per bank write bursts +system.physmem.perBankRdBursts::7 255 # Per bank write bursts system.physmem.perBankRdBursts::8 219 # Per bank write bursts system.physmem.perBankRdBursts::9 290 # Per bank write bursts system.physmem.perBankRdBursts::10 315 # Per bank write bursts system.physmem.perBankRdBursts::11 411 # Per bank write bursts system.physmem.perBankRdBursts::12 547 # Per bank write bursts system.physmem.perBankRdBursts::13 678 # Per bank write bursts -system.physmem.perBankRdBursts::14 615 # Per bank write bursts +system.physmem.perBankRdBursts::14 620 # Per bank write bursts system.physmem.perBankRdBursts::15 555 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 112686876000 # Total gap between requests +system.physmem.totGap 112728140000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7323 # Read request sizes (log2) +system.physmem.readPktSize::6 7331 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,20 +94,20 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4012 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1463 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4022 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1455 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 286 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 170 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 170 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 233 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 204 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 179 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 165 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 54 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -190,26 +190,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1371 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 339.932896 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 197.349943 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 349.457617 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 486 35.45% 35.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 309 22.54% 57.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 132 9.63% 67.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 75 5.47% 73.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 64 4.67% 77.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 48 3.50% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 26 1.90% 83.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 25 1.82% 84.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 206 15.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1371 # Bytes accessed per row activation -system.physmem.totQLat 95174041 # Total ticks spent queuing -system.physmem.totMemAccLat 232480291 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 36615000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12996.59 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1373 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 339.670794 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 197.560456 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 349.691004 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 480 34.96% 34.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 312 22.72% 57.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 141 10.27% 67.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 79 5.75% 73.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 55 4.01% 77.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 48 3.50% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 23 1.68% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 27 1.97% 84.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 208 15.15% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1373 # Bytes accessed per row activation +system.physmem.totQLat 90206647 # Total ticks spent queuing +system.physmem.totMemAccLat 227662897 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36655000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12304.82 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31746.59 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31054.82 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.16 # Average system read bandwidth in MiByte/s @@ -218,50 +218,50 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.45 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.50 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5943 # Number of row buffer hits during reads +system.physmem.readRowHits 5948 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.16 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.13 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 15388075.38 # Average gap between requests -system.physmem.pageHitRate 81.16 # Row buffer hit rate, read and write combined +system.physmem.avgGap 15376911.74 # Average gap between requests +system.physmem.pageHitRate 81.13 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 4815720 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 2627625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 28641600 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 28618200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 7359880320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3233168820 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 64773630750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 75402764835 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.158858 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 107753956620 # Time in different power states -system.physmem_0.memoryStateTime::REF 3762720000 # Time in different power states +system.physmem_0.refreshEnergy 7362423120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3214163025 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 64813639500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 75426287190 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.136639 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 107820696894 # Time in different power states +system.physmem_0.memoryStateTime::REF 3764020000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1166688380 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1137632606 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5526360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3015375 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 5511240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3007125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 28126800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 7359880320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3309876000 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 64706325000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 75412749855 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.247655 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 107640832624 # Time in different power states -system.physmem_1.memoryStateTime::REF 3762720000 # Time in different power states +system.physmem_1.refreshEnergy 7362423120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3285750465 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 64750835250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 75435654000 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.219817 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 107714946135 # Time in different power states +system.physmem_1.memoryStateTime::REF 3764020000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1279848380 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1243230865 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 37743135 # Number of BP lookups -system.cpu.branchPred.condPredicted 20164607 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1746155 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18663607 # Number of BTB lookups -system.cpu.branchPred.BTBHits 17299273 # Number of BTB hits +system.cpu.branchPred.lookups 37743002 # Number of BP lookups +system.cpu.branchPred.condPredicted 20164593 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1746138 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18663724 # Number of BTB lookups +system.cpu.branchPred.BTBHits 17299181 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.689870 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7223670 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 92.688796 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7223599 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -381,129 +381,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 225374070 # number of cpu cycles simulated +system.cpu.numCycles 225456598 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12439227 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 334051995 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37743135 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24522943 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 210854521 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3510703 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1310 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 2474 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 89092353 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 21704 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 225052883 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.800484 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.229411 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12486047 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 334063522 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37743002 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24522780 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 210891035 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3510673 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1258 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 2507 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 89094273 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 21774 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 225136183 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.799914 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.229503 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 51372314 22.83% 22.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42891452 19.06% 41.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 30054577 13.35% 55.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 100734540 44.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 51412756 22.84% 22.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42958324 19.08% 41.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 30027813 13.34% 55.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 100737290 44.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 225052883 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.167469 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.482211 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 27836779 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63911722 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108618516 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 23065273 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1620593 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6880055 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 135197 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 363544847 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 6170021 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1620593 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 45199707 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 17872689 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 341815 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 113380410 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 46637669 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 355768309 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 2890306 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 6609751 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 177931 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7804271 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 21223751 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 2890543 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 403406246 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2534025265 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 350247395 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 194894231 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 225136183 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.167407 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.481720 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 27896248 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63927882 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108602791 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 23088664 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1620598 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6880038 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 135173 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 363542969 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6170181 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1620598 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 45231914 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 18002517 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 341926 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 113354912 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 46584316 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 355763735 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 2890412 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 6625666 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 177937 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7803151 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 21129906 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 2817742 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 403401676 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2534003745 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 350242817 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 194894499 # Number of floating rename lookups system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31176195 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 31171625 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 17016 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 17025 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 55506509 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 92416612 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 88498373 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1661373 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1847329 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 353252571 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 55451024 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 92416595 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 88498352 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1661185 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1846398 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 353252669 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 28026 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 346438287 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 2302047 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 25468995 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 73729207 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 346437634 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 2301476 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 25469093 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 73749076 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 5906 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 225052883 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.539364 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.099868 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 225136183 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.538791 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.099493 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 40665148 18.07% 18.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 78299865 34.79% 52.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 60995131 27.10% 79.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34883362 15.50% 95.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9557615 4.25% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 642958 0.29% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8804 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 40701776 18.08% 18.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 78366146 34.81% 52.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 60939580 27.07% 79.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34977344 15.54% 95.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9507598 4.22% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 632530 0.28% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 11209 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 225052883 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 225136183 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9490613 7.63% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7317 0.01% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 255761 0.21% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 126865 0.10% 7.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 93219 0.07% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 68015 0.05% 8.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 721837 0.58% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 297231 0.24% 8.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 683044 0.55% 9.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 53642383 43.14% 52.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 58959382 47.42% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9586225 7.69% 7.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7350 0.01% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 255762 0.21% 7.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 132929 0.11% 8.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 93071 0.07% 8.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 61949 0.05% 8.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 719141 0.58% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 303244 0.24% 8.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 683031 0.55% 9.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 53752847 43.14% 52.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 59000415 47.35% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 110655137 31.94% 31.94% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148355 0.62% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 110655046 31.94% 31.94% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148359 0.62% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.56% # Type of FU issued @@ -522,93 +522,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.56% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6798397 1.96% 34.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6798342 1.96% 34.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8668117 2.50% 37.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8667218 2.50% 37.03% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 3332482 0.96% 37.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1592458 0.46% 38.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20930149 6.04% 44.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7182320 2.07% 46.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7148962 2.06% 48.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592517 0.46% 38.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20930304 6.04% 44.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7182327 2.07% 46.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7148965 2.06% 48.63% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 91923270 26.53% 75.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 85883354 24.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 91923294 26.53% 75.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 85883494 24.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 346438287 # Type of FU issued -system.cpu.iq.rate 1.537170 # Inst issue rate -system.cpu.iq.fu_busy_cnt 124345667 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.358926 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 757022758 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 251740405 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 223260402 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 287554413 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 127019437 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 117424930 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 303229780 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 167554174 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5064825 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 346437634 # Type of FU issued +system.cpu.iq.rate 1.536605 # Inst issue rate +system.cpu.iq.fu_busy_cnt 124595964 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.359649 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 757212589 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 251740831 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 223259855 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 287696302 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 127019209 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 117423886 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 303336303 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 167697295 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5085757 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6684337 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13570 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 10254 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6122756 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6684320 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13571 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 10256 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6122735 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 155338 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 607759 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 155306 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 607778 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1620593 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2118874 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 332196 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 353281462 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 1620598 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2118913 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 332541 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 353281560 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 92416612 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 88498373 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 92416595 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 88498352 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 16993 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 8049 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 338656 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 10254 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1220664 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 439075 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1659739 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 342448688 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 90703769 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3989599 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 8047 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 339026 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 10256 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1220653 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 439070 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1659723 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 342447875 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 90703562 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3989759 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 865 # number of nop insts executed -system.cpu.iew.exec_refs 175291174 # number of memory reference insts executed -system.cpu.iew.exec_branches 31752726 # Number of branches executed -system.cpu.iew.exec_stores 84587405 # Number of stores executed -system.cpu.iew.exec_rate 1.519468 # Inst execution rate -system.cpu.iew.wb_sent 340944051 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 340685332 # cumulative count of insts written-back -system.cpu.iew.wb_producers 153662647 # num instructions producing a value -system.cpu.iew.wb_consumers 266737544 # num instructions consuming a value +system.cpu.iew.exec_refs 175290975 # number of memory reference insts executed +system.cpu.iew.exec_branches 31752712 # Number of branches executed +system.cpu.iew.exec_stores 84587413 # Number of stores executed +system.cpu.iew.exec_rate 1.518908 # Inst execution rate +system.cpu.iew.wb_sent 340942422 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 340683741 # cumulative count of insts written-back +system.cpu.iew.wb_producers 153622639 # num instructions producing a value +system.cpu.iew.wb_consumers 266573014 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.511644 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.576082 # average fanout of values written-back +system.cpu.iew.wb_rate 1.511083 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.576287 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23083260 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23082594 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1611397 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 221327720 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.481117 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.050757 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1611400 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 221410973 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.480560 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.051639 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 87528718 39.55% 39.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 70478843 31.84% 71.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 20814822 9.40% 80.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13433890 6.07% 86.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8801339 3.98% 90.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4513701 2.04% 92.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2986759 1.35% 94.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2449542 1.11% 95.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10320106 4.66% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 87667745 39.60% 39.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 70465931 31.83% 71.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 20808534 9.40% 80.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13377083 6.04% 86.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8762034 3.96% 90.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4538069 2.05% 92.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3005918 1.36% 94.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2461295 1.11% 95.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10324364 4.66% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 221327720 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 221410973 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037832 # Number of instructions committed system.cpu.commit.committedOps 327812214 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -654,32 +654,32 @@ system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 327812214 # Class of committed instruction -system.cpu.commit.bw_lim_events 10320106 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 561900565 # The number of ROB reads -system.cpu.rob.rob_writes 705520050 # The number of ROB writes -system.cpu.timesIdled 50865 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 321187 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 10324364 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 561978894 # The number of ROB reads +system.cpu.rob.rob_writes 705518745 # The number of ROB writes +system.cpu.timesIdled 51182 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320415 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273037220 # Number of Instructions Simulated system.cpu.committedOps 327811602 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.825434 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.825434 # CPI: Total CPI of All Threads -system.cpu.ipc 1.211485 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.211485 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 331332035 # number of integer regfile reads -system.cpu.int_regfile_writes 136939352 # number of integer regfile writes -system.cpu.fp_regfile_reads 187107868 # number of floating regfile reads -system.cpu.fp_regfile_writes 132178738 # number of floating regfile writes -system.cpu.cc_regfile_reads 1297133606 # number of cc regfile reads -system.cpu.cc_regfile_writes 80241640 # number of cc regfile writes -system.cpu.misc_regfile_reads 1183127847 # number of misc regfile reads +system.cpu.cpi 0.825736 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.825736 # CPI: Total CPI of All Threads +system.cpu.ipc 1.211041 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.211041 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 331331297 # number of integer regfile reads +system.cpu.int_regfile_writes 136939218 # number of integer regfile writes +system.cpu.fp_regfile_reads 187106677 # number of floating regfile reads +system.cpu.fp_regfile_writes 132176732 # number of floating regfile writes +system.cpu.cc_regfile_reads 1297128117 # number of cc regfile reads +system.cpu.cc_regfile_writes 80240781 # number of cc regfile writes +system.cpu.misc_regfile_reads 1183123878 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1533845 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.843427 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 163642817 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1534357 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 106.652374 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 82681000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.843427 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 1533840 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.843429 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 163621677 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1534352 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 106.638944 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 82703000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.843429 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999694 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999694 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -688,148 +688,148 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 310 system.cpu.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336637061 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336637061 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 82609464 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 82609464 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80941053 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80941053 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 70494 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 70494 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 336594804 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336594804 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 82588364 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 82588364 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80941030 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80941030 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 70477 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 70477 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 163550517 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 163550517 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 163621011 # number of overall hits -system.cpu.dcache.overall_hits::total 163621011 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2796868 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2796868 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1111646 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1111646 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 163529394 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 163529394 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 163599871 # number of overall hits +system.cpu.dcache.overall_hits::total 163599871 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2796859 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2796859 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1111669 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1111669 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3908514 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3908514 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3908532 # number of overall misses -system.cpu.dcache.overall_misses::total 3908532 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 22403262000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 22403262000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8965991000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8965991000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3908528 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3908528 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3908546 # number of overall misses +system.cpu.dcache.overall_misses::total 3908546 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 22523988500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 22523988500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8974716998 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8974716998 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 189000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31369253000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31369253000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31369253000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31369253000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 85406332 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 85406332 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 31498705498 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31498705498 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31498705498 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31498705498 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 85385223 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 85385223 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 70512 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 70512 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 70495 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 70495 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 167459031 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 167459031 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 167529543 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 167529543 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032748 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032748 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 167437922 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 167437922 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 167508417 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 167508417 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032756 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032756 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013548 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.013548 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000255 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.000255 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023340 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023340 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023330 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023330 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8010.124897 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 8010.124897 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8065.509164 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8065.509164 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.023343 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023343 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023333 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023333 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8053.315702 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 8053.315702 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8073.191749 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8073.191749 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37800 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37800 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 8025.877098 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 8025.877098 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 8025.840136 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 8025.840136 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 8058.968875 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 8058.968875 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 8058.931761 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 8058.931761 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1060412 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1061983 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 134750 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7.869477 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7.881135 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 966339 # number of writebacks system.cpu.dcache.writebacks::total 966339 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1483175 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1483175 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 890991 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 890991 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1483171 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1483171 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 891014 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 891014 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2374166 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2374166 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2374166 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2374166 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313693 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1313693 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 2374185 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2374185 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2374185 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2374185 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313688 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1313688 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220655 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 220655 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1534348 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1534348 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1534359 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1534359 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10623648000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10623648000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1826747781 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1826747781 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 681000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 681000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12450395781 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12450395781 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12451076781 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12451076781 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015382 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015382 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1534343 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1534343 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1534354 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1534354 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10737741500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10737741500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1828416279 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1828416279 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 682500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 682500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12566157779 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12566157779 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12566840279 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12566840279 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015385 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015385 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002689 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002689 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000156 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000156 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009163 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.009163 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009159 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.009159 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8086.857432 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8086.857432 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8278.750905 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8278.750905 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61909.090909 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61909.090909 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8114.453684 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8114.453684 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8114.839344 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8114.839344 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009164 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.009164 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009160 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.009160 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8173.737980 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8173.737980 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8286.312474 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8286.312474 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62045.454545 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62045.454545 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8189.927402 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8189.927402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8190.313499 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8190.313499 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 715635 # number of replacements -system.cpu.icache.tags.tagsinuse 511.829472 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 88370544 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 716147 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 123.397213 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 326419500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.829472 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 715629 # 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Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 178900820 # Number of tag accesses -system.cpu.icache.tags.data_accesses 178900820 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 88370544 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 88370544 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 88370544 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 88370544 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 88370544 # number of overall hits -system.cpu.icache.overall_hits::total 88370544 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 721792 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 721792 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 721792 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 721792 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 721792 # number of overall misses -system.cpu.icache.overall_misses::total 721792 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 5973239447 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 5973239447 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 5973239447 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 5973239447 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 5973239447 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 5973239447 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 89092336 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 89092336 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 89092336 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 89092336 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 89092336 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 89092336 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008102 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008102 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008102 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008102 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008102 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008102 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8275.568927 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8275.568927 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8275.568927 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8275.568927 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8275.568927 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8275.568927 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 62302 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 178904656 # Number of tag accesses +system.cpu.icache.tags.data_accesses 178904656 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 88372474 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 88372474 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 88372474 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 88372474 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 88372474 # number of overall hits +system.cpu.icache.overall_hits::total 88372474 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 721783 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 721783 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 721783 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 721783 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 721783 # number of overall misses +system.cpu.icache.overall_misses::total 721783 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 5996265446 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 5996265446 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 5996265446 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 5996265446 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 5996265446 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 5996265446 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 89094257 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 89094257 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 89094257 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 89094257 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 89094257 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 89094257 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008101 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008101 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008101 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008101 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008101 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008101 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8307.573670 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8307.573670 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8307.573670 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8307.573670 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8307.573670 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8307.573670 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 62233 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2158 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2180 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.870250 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.547248 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 31.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 5644 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 5644 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 5644 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 5644 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 5644 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 5644 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 716148 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 716148 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 716148 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 716148 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 716148 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 716148 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5551358955 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 5551358955 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5551358955 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 5551358955 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5551358955 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 5551358955 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 5641 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 5641 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 5641 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 5641 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 5641 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 5641 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 716142 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 716142 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 716142 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 716142 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 716142 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 716142 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5575388455 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 5575388455 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5575388455 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 5575388455 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5575388455 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 5575388455 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008038 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008038 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008038 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.008038 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008038 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.008038 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7751.692325 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7751.692325 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7751.692325 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7751.692325 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7751.692325 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7751.692325 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7785.311370 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7785.311370 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7785.311370 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7785.311370 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7785.311370 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7785.311370 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 405270 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 405390 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 107 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 404899 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 404967 # 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Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3840397 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 7305 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 525.721697 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2575.177185 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2680.633084 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 617.470420 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 114.704950 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.157176 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.163613 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.037687 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 773 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 127 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5749 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.030884 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.414490 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 68225328 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 68225328 # Number of data accesses +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 771 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 128 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5745 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.031677 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.414185 # 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number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 739 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2922 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2922 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1023 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1023 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2922 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1762 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 4684 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2922 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1762 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 30448 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 35132 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 176616285 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 176616285 # number of HardPFReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 17000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 17000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49936000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49936000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 182660500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 182660500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 69288000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 69288000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 182660500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 119224000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 301884500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 182660500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 119224000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 180653766 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 482538266 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 50771000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 50771000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 181268500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 181268500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 69264000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 69264000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 181268500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 120035000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 301303500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 181268500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 120035000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 176616285 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 477919785 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003313 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003313 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004087 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004087 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000781 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000781 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004087 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001145 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.002080 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004087 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001145 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003349 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003349 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004085 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004085 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000779 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000779 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004085 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001148 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.002082 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004085 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001148 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.015606 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5937.284846 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 5937.284846 # average HardPFReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.015617 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5800.587395 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 5800.587395 # average HardPFReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68311.901505 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68311.901505 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62490.762915 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62490.762915 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67532.163743 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67532.163743 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62490.762915 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67856.573705 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64505.235043 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62490.762915 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67856.573705 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5937.284846 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13744.787820 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68702.300406 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68702.300406 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62035.763176 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62035.763176 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67706.744868 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67706.744868 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62035.763176 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68124.290579 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64326.110162 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62035.763176 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68124.290579 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5800.587395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13603.546197 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 2029852 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 4499965 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2249489 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 249352 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 27801 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 27801 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 2029841 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 966339 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1033896 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 31809 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1033885 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 31840 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 220653 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 220653 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 716148 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1313704 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2122580 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4377763 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6500343 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45775488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160044544 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205820032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 32715 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4531796 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.007019 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.083485 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 716142 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1313699 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2122562 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4377748 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6500310 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45775104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160044224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205819328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 32746 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4531805 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.116184 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.320445 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4499987 99.30% 99.30% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 31809 0.70% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 4005282 88.38% 88.38% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 526523 11.62% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4531796 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3216332500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4531805 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3216321500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1074486969 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1074578268 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2301554963 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2302086882 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) system.membus.trans_dist::ReadResp 6592 # Transaction distribution system.membus.trans_dist::UpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 731 # Transaction distribution -system.membus.trans_dist::ReadExResp 731 # Transaction distribution +system.membus.trans_dist::ReadExReq 739 # Transaction distribution +system.membus.trans_dist::ReadExResp 739 # Transaction distribution system.membus.trans_dist::ReadSharedReq 6592 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14648 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14648 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 468672 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 468672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14664 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14664 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 469184 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 469184 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7324 # Request fanout histogram +system.membus.snoop_fanout::samples 7332 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7324 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7332 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7324 # Request fanout histogram -system.membus.reqLayer0.occupancy 9437390 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7332 # Request fanout histogram +system.membus.reqLayer0.occupancy 9416916 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 38347412 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 38389399 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index b10e642ea..e29d83073 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.517235 # Number of seconds simulated -sim_ticks 517235407500 # Number of ticks simulated -final_tick 517235407500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.517243 # Number of seconds simulated +sim_ticks 517243165500 # Number of ticks simulated +final_tick 517243165500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 785915 # Simulator instruction rate (inst/s) -host_op_rate 943520 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1490444540 # Simulator tick rate (ticks/s) -host_mem_usage 321320 # Number of bytes of host memory used -host_seconds 347.03 # Real time elapsed on the host +host_inst_rate 702843 # Simulator instruction rate (inst/s) +host_op_rate 843789 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1332923086 # Simulator tick rate (ticks/s) +host_mem_usage 322968 # Number of bytes of host memory used +host_seconds 388.05 # Real time elapsed on the host sim_insts 272739286 # Number of instructions simulated sim_ops 327433744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 166912 # Nu system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 322700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 522656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 845356 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 322700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 322700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 322700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 522656 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 322695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 522648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 845343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 322695 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 322695 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 322695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 522648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 845343 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 1034470815 # number of cpu cycles simulated +system.cpu.numCycles 1034486331 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 272739286 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 168107847 # nu system.cpu.num_load_insts 85732248 # Number of load instructions system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1034470814.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1034486330.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 30563503 # Number of branches fetched @@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812214 # Class of executed instruction system.cpu.dcache.tags.replacements 1332 # number of replacements -system.cpu.dcache.tags.tagsinuse 3078.445031 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3078.444355 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445031 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 3078.444355 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id @@ -249,14 +249,14 @@ system.cpu.dcache.demand_misses::cpu.data 4476 # n system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses system.cpu.dcache.overall_misses::total 4479 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 78396000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 78396000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 78469000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 78469000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 157423500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 157423500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 235819500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 235819500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 235819500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 235819500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 235892500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 235892500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 235892500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 235892500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) @@ -281,14 +281,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48875.311721 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 48875.311721 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48920.822943 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 48920.822943 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.196379 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.196379 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52685.321716 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52685.321716 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52650.033490 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52650.033490 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52701.630920 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52701.630920 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52666.331770 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52666.331770 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -315,16 +315,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4475 system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76753000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 76753000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76826000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 76826000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 154551500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 154551500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 162000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 162000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 231304500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 231304500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 231466500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 231466500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 231377500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 231377500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 231539500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 231539500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -335,24 +335,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47880.848409 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47880.848409 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47926.388022 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47926.388022 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53813.196379 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53813.196379 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51688.156425 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51688.156425 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51689.705226 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51689.705226 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51704.469274 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51704.469274 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51706.007146 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51706.007146 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13796 # number of replacements -system.cpu.icache.tags.tagsinuse 1766.007653 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1766.007280 # Cycle average of tags in use system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007653 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007280 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id @@ -376,12 +376,12 @@ system.cpu.icache.demand_misses::cpu.inst 15603 # n system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses system.cpu.icache.overall_misses::total 15603 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 312483000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 312483000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 312483000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 312483000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 312483000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 312483000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 320168000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 320168000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 320168000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 320168000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 320168000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 320168000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses @@ -394,12 +394,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20027.110171 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20027.110171 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20027.110171 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20027.110171 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20027.110171 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20027.110171 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20519.643658 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20519.643658 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20519.643658 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20519.643658 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20519.643658 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20519.643658 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -414,34 +414,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603 system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 296880000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 296880000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 296880000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 296880000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 296880000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 296880000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 304565000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 304565000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 304565000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 304565000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 304565000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 304565000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19027.110171 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19027.110171 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19027.110171 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19027.110171 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19027.110171 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19027.110171 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19519.643658 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19519.643658 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19519.643658 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19519.643658 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19519.643658 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19519.643658 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3487.764994 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3487.764139 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 341.623058 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.427152 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 738.714783 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 341.622938 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.426609 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 738.714591 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010426 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073469 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.022544 # Average percentage of cache occupancy @@ -588,6 +588,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42541.219325 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42576.231061 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42562.865925 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6465 # Transaction distribution @@ -603,14 +609,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 35209 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.438041 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.496153 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 35209 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 19786 56.20% 56.20% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 15423 43.80% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 35209 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 18602500 # Layer occupancy (ticks) |