diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-12-05 16:48:34 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-12-05 16:48:34 -0500 |
| commit | ebd9018a139178aed432b257ff4ce6dc2d5f795f (patch) | |
| tree | 0d844028751908a7c7f66f82e5bd9564467086c9 /tests/long/se/30.eon/ref/arm | |
| parent | 9e57e4e89d3c6b6d7e0f0f182bfd01c5585c16c5 (diff) | |
| download | gem5-ebd9018a139178aed432b257ff4ce6dc2d5f795f.tar.xz | |
stats: Update stats to reflect cache changes
Diffstat (limited to 'tests/long/se/30.eon/ref/arm')
| -rw-r--r-- | tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt | 154 | ||||
| -rw-r--r-- | tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt | 1483 |
2 files changed, 818 insertions, 819 deletions
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index d7f32d52d..b2bc0dd63 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.225207 # Nu sim_ticks 225206521000 # Number of ticks simulated final_tick 225206521000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 284094 # Simulator instruction rate (inst/s) -host_op_rate 341086 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 234325505 # Simulator tick rate (ticks/s) -host_mem_usage 279956 # Number of bytes of host memory used -host_seconds 961.08 # Real time elapsed on the host +host_inst_rate 289736 # Simulator instruction rate (inst/s) +host_op_rate 347860 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 238979319 # Simulator tick rate (ticks/s) +host_mem_usage 279872 # Number of bytes of host memory used +host_seconds 942.37 # Real time elapsed on the host sim_insts 273037855 # Number of instructions simulated sim_ops 327812212 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 33 2.18% 86.17% # By system.physmem.bytesPerActivate::896-1023 36 2.38% 88.55% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 173 11.45% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1511 # Bytes accessed per row activation -system.physmem.totQLat 232482000 # Total ticks spent queuing -system.physmem.totMemAccLat 374738250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 232471000 # Total ticks spent queuing +system.physmem.totMemAccLat 374727250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37935000 # Total ticks spent in databus transfers -system.physmem.avgQLat 30642.15 # Average queueing delay per DRAM burst +system.physmem.avgQLat 30640.70 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 49392.15 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 49390.70 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s @@ -228,28 +228,28 @@ system.physmem_0.preEnergy 2504700 # En system.physmem_0.readEnergy 27553260 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 284578320.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 100450530 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 100446540 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 15488640 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 721250640 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 385416480 # Energy for precharge power-down per rank (pJ) +system.physmem_0.actPowerDownEnergy 721249500 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 385420800 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 53424510300 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 54966479550 # Total energy per rank (pJ) -system.physmem_0.averagePower 244.071438 # Core power per rank (mW) -system.physmem_0.totalIdleTime 224945701750 # Total Idle time Per DRAM Rank +system.physmem_0.totalEnergy 54966478740 # Total energy per rank (pJ) +system.physmem_0.averagePower 244.071435 # Core power per rank (mW) +system.physmem_0.totalIdleTime 224945712750 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 29370000 # Time in different power states system.physmem_0.memoryStateTime::REF 121010000 # Time in different power states system.physmem_0.memoryStateTime::SREF 222360521000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 1003697750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 110222000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 1003708750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 110211000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 1581700250 # Time in different power states system.physmem_1.actEnergy 6083280 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 3229545 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 26617920 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 394598880.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 121239570 # Energy for active background per rank (pJ) +system.physmem_1.actBackEnergy 121237860 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 22348800 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 914379180 # Energy for active power-down per rank (pJ) +system.physmem_1.actPowerDownEnergy 914380890 # Energy for active power-down per rank (pJ) system.physmem_1.prePowerDownEnergy 605052000 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 53195794545 # Energy for self refresh per rank (pJ) system.physmem_1.totalEnergy 55289408190 # Total energy per rank (pJ) @@ -446,16 +446,16 @@ system.cpu.op_class_0::FloatMemWrite 27367218 8.35% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 327812212 # Class of committed instruction -system.cpu.tickCycles 434950533 # Number of cycles that the object actually ticked -system.cpu.idleCycles 15462509 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 434950536 # Number of cycles that the object actually ticked +system.cpu.idleCycles 15462506 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1355 # number of replacements -system.cpu.dcache.tags.tagsinuse 3085.768112 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3085.768110 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168654205 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4512 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37379.034796 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768112 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768110 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.753361 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.753361 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id @@ -590,12 +590,12 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101521.387411 system.cpu.dcache.overall_avg_mshr_miss_latency::total 101521.387411 # average overall mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 38188 # number of replacements -system.cpu.icache.tags.tagsinuse 1924.800725 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1924.800722 # Cycle average of tags in use system.cpu.icache.tags.total_refs 69819801 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 40125 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1740.057346 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1924.800725 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.800722 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.939844 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.939844 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id @@ -620,12 +620,12 @@ system.cpu.icache.demand_misses::cpu.inst 40126 # n system.cpu.icache.demand_misses::total 40126 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 40126 # number of overall misses system.cpu.icache.overall_misses::total 40126 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 817901000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 817901000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 817901000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 817901000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 817901000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 817901000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 817900500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 817900500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 817900500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 817900500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 817900500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 817900500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 69859927 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 69859927 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 69859927 # number of demand (read+write) accesses @@ -638,12 +638,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000574 system.cpu.icache.demand_miss_rate::total 0.000574 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000574 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000574 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20383.317550 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20383.317550 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20383.317550 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20383.317550 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20383.317550 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20383.317550 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20383.305089 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20383.305089 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20383.305089 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20383.305089 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20383.305089 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20383.305089 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -658,33 +658,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 40126 system.cpu.icache.demand_mshr_misses::total 40126 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 40126 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 40126 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 777776000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 777776000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 777776000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 777776000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 777776000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 777776000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 777775500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 777775500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 777775500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 777775500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 777775500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 777775500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000574 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000574 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000574 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19383.342471 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19383.342471 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19383.342471 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19383.342471 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19383.342471 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19383.342471 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19383.330010 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19383.330010 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19383.330010 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19383.330010 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19383.330010 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19383.330010 # average overall mshr miss latency system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 6596.216026 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 6596.216022 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 61516 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 7587 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 8.108080 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.840745 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.375281 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.840742 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.375280 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096675 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.104626 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.201301 # Average percentage of cache occupancy @@ -728,16 +728,16 @@ system.cpu.l2cache.overall_misses::cpu.data 4204 # system.cpu.l2cache.overall_misses::total 7630 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 281205000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 281205000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 317313000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 317313000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 317302500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 317302500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 166631000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 166631000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 317313000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 317302500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 447836000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 765149000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 317313000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 765138500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 317302500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 447836000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 765149000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 765138500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 1010 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 1010 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 23270 # number of WritebackClean accesses(hits+misses) @@ -768,16 +768,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.931738 system.cpu.l2cache.overall_miss_rate::total 0.170931 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98530.133146 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98530.133146 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92619.089317 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92619.089317 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92616.024518 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92616.024518 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123430.370370 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123430.370370 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92619.089317 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92616.024518 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106526.165557 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 100281.651376 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92619.089317 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 100280.275229 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92616.024518 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106526.165557 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 100281.651376 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 100280.275229 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -808,16 +808,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 4163 system.cpu.l2cache.overall_mshr_misses::total 7587 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 252665000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 252665000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 282924500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 282924500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 282914000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 282914000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 150580000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 150580000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 282924500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 282914000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 403245000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 686169500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 282924500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 686159000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 282914000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 403245000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 686169500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 686159000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for ReadCleanReq accesses @@ -832,16 +832,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922651 system.cpu.l2cache.overall_mshr_miss_rate::total 0.169967 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88530.133146 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88530.133146 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82629.818925 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82629.818925 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82626.752336 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82626.752336 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115034.377387 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115034.377387 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82629.818925 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82626.752336 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96864.040356 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90440.160801 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82629.818925 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90438.776855 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82626.752336 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96864.040356 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90440.160801 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90438.776855 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 84181 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 39645 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15035 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -909,7 +909,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7587 # Request fanout histogram -system.membus.reqLayer0.occupancy 9082000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9082500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 40299000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index fc2854304..c49c5de69 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.124291 # Number of seconds simulated -sim_ticks 124290972500 # Number of ticks simulated -final_tick 124290972500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.124349 # Number of seconds simulated +sim_ticks 124348696500 # Number of ticks simulated +final_tick 124348696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 226846 # Simulator instruction rate (inst/s) -host_op_rate 272354 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 103264191 # Simulator tick rate (ticks/s) -host_mem_usage 292872 # Number of bytes of host memory used -host_seconds 1203.62 # Real time elapsed on the host +host_inst_rate 233440 # Simulator instruction rate (inst/s) +host_op_rate 280271 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 106315167 # Simulator tick rate (ticks/s) +host_mem_usage 292792 # Number of bytes of host memory used +host_seconds 1169.62 # Real time elapsed on the host sim_insts 273037218 # Number of instructions simulated sim_ops 327811600 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1883840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 14654016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 168640 # Number of bytes read from this memory -system.physmem.bytes_read::total 16706496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1883840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1883840 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 29435 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 228969 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 2635 # Number of read requests responded to by this memory -system.physmem.num_reads::total 261039 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 15156692 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 117900888 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 1356816 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 134414396 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 15156692 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 15156692 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 15156692 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 117900888 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 1356816 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 134414396 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 261040 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1887808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 14649536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 167872 # Number of bytes read from this memory +system.physmem.bytes_read::total 16705216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1887808 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1887808 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 29497 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 228899 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2623 # Number of read requests responded to by this memory +system.physmem.num_reads::total 261019 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 15181566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 117810129 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1350010 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 134341706 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 15181566 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 15181566 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 15181566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 117810129 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1350010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 134341706 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 261020 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 261040 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 261020 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 16706560 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 16705280 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 16706560 # Total read bytes from the system interface side +system.physmem.bytesReadSys 16705280 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1259 # Per bank write bursts -system.physmem.perBankRdBursts::1 69986 # Per bank write bursts +system.physmem.perBankRdBursts::0 1258 # Per bank write bursts +system.physmem.perBankRdBursts::1 69987 # Per bank write bursts system.physmem.perBankRdBursts::2 1297 # Per bank write bursts system.physmem.perBankRdBursts::3 10756 # Per bank write bursts -system.physmem.perBankRdBursts::4 42908 # Per bank write bursts +system.physmem.perBankRdBursts::4 42907 # Per bank write bursts system.physmem.perBankRdBursts::5 121816 # Per bank write bursts system.physmem.perBankRdBursts::6 153 # Per bank write bursts -system.physmem.perBankRdBursts::7 261 # Per bank write bursts -system.physmem.perBankRdBursts::8 228 # Per bank write bursts +system.physmem.perBankRdBursts::7 252 # Per bank write bursts +system.physmem.perBankRdBursts::8 224 # Per bank write bursts system.physmem.perBankRdBursts::9 562 # Per bank write bursts system.physmem.perBankRdBursts::10 7773 # Per bank write bursts system.physmem.perBankRdBursts::11 812 # Per bank write bursts system.physmem.perBankRdBursts::12 1213 # Per bank write bursts system.physmem.perBankRdBursts::13 743 # Per bank write bursts -system.physmem.perBankRdBursts::14 662 # Per bank write bursts -system.physmem.perBankRdBursts::15 611 # Per bank write bursts +system.physmem.perBankRdBursts::14 657 # Per bank write bursts +system.physmem.perBankRdBursts::15 610 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 124290963000 # Total gap between requests +system.physmem.totGap 124348687000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 261040 # Read request sizes (log2) +system.physmem.readPktSize::6 261020 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,20 +95,20 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 204132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 43333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 305 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 233 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 211 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 177 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 64 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 204123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 43351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 303 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 212 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 241 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 31 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -191,29 +191,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67943 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 245.854084 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.733686 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 200.637928 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18270 26.89% 26.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22179 32.64% 59.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11425 16.82% 76.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6866 10.11% 86.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4751 6.99% 93.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2068 3.04% 96.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1319 1.94% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 392 0.58% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 673 0.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67943 # Bytes accessed per row activation -system.physmem.totQLat 4615275409 # Total ticks spent queuing -system.physmem.totMemAccLat 9509775409 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1305200000 # Total ticks spent in databus transfers -system.physmem.avgQLat 17680.34 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 67933 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 245.871432 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.817049 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 200.519544 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18227 26.83% 26.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22195 32.67% 59.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11448 16.85% 76.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6857 10.09% 86.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4767 7.02% 93.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2062 3.04% 96.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1306 1.92% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 411 0.61% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 660 0.97% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67933 # Bytes accessed per row activation +system.physmem.totQLat 4577430956 # Total ticks spent queuing +system.physmem.totMemAccLat 9471555956 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1305100000 # Total ticks spent in databus transfers +system.physmem.avgQLat 17536.71 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 36430.34 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 134.41 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 36286.71 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 134.34 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 134.41 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 134.34 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.05 # Data bus utilization in percentage @@ -221,66 +221,66 @@ system.physmem.busUtilRead 1.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.60 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 193087 # Number of row buffer hits during reads +system.physmem.readRowHits 193077 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 73.97 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 476137.61 # Average gap between requests +system.physmem.avgGap 476395.25 # Average gap between requests system.physmem.pageHitRate 73.97 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 450177000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 239263365 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1773833040 # Energy for read commands per rank (pJ) +system.physmem_0.actEnergy 450269820 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 239312700 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1773761640 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 9685497120.000002 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4649003790 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 227628000 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 45880019340 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 3639028320 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 957591945 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 67502066010 # Total energy per rank (pJ) -system.physmem_0.averagePower 543.097094 # Core power per rank (mW) -system.physmem_0.totalIdleTime 113501776163 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 155671000 # Time in different power states -system.physmem_0.memoryStateTime::REF 4098592000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 3412225500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 9476337397 # Time in different power states -system.physmem_0.memoryStateTime::ACT 6534800587 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 100613346016 # Time in different power states -system.physmem_1.actEnergy 35000280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 18576525 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 89985420 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 9689184960.000002 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4649576640 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 227532000 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 45899424420 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 3643060800 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 957889500 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 67530012480 # Total energy per rank (pJ) +system.physmem_0.averagePower 543.069721 # Core power per rank (mW) +system.physmem_0.totalIdleTime 113559853415 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 155359000 # Time in different power states +system.physmem_0.memoryStateTime::REF 4100146000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 3415967750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 9487195385 # Time in different power states +system.physmem_0.memoryStateTime::ACT 6533205335 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 100656823030 # Time in different power states +system.physmem_1.actEnergy 34836060 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 18489240 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 89914020 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3070126800.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 722159790 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 122839680 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 10172185800 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 3790789440 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 22016840895 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 40039093920 # Total energy per rank (pJ) -system.physmem_1.averagePower 322.140000 # Core power per rank (mW) -system.physmem_1.totalIdleTime 122386077248 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 197400000 # Time in different power states -system.physmem_1.memoryStateTime::REF 1302732000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 90206777750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 9871788058 # Time in different power states -system.physmem_1.memoryStateTime::ACT 404763252 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 22307511440 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 35978086 # Number of BP lookups -system.cpu.branchPred.condPredicted 19268966 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 984583 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17896722 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13923101 # Number of BTB hits +system.physmem_1.refreshEnergy 3070741440.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 722151240 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 123038400 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 10175174880 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 3785444640 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 22033476180 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 40053946380 # Total energy per rank (pJ) +system.physmem_1.averagePower 322.109899 # Core power per rank (mW) +system.physmem_1.totalIdleTime 122443240524 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 197934000 # Time in different power states +system.physmem_1.memoryStateTime::REF 1303004000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 90271203500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 9858082832 # Time in different power states +system.physmem_1.memoryStateTime::ACT 404517976 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 22313954192 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 35976625 # Number of BP lookups +system.cpu.branchPred.condPredicted 19268286 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 984581 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17895680 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13922117 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 77.796934 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6952398 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 77.795965 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6952257 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4419 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2517542 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2473672 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 43870 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 129186 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 2517536 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2473662 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 43874 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 129189 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -310,7 +310,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -340,7 +340,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -370,7 +370,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -401,135 +401,135 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 124290972500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 248581946 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 248697394 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12982171 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 309515100 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35978086 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23349171 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 231243677 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1995433 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1630 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 13177926 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 309504909 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35976625 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23348036 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 231160130 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1995425 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1604 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 63 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3229 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 82227465 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 34636 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 245228486 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.518257 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.300334 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3168 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 82224377 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 34576 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 245340603 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.517503 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.300446 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 84781187 34.57% 34.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 40505386 16.52% 51.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 28011183 11.42% 62.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 91930730 37.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 84898952 34.60% 34.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 40504202 16.51% 51.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 28011427 11.42% 62.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 91926022 37.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 245228486 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.144733 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.245123 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 27310570 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 94773867 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 97190577 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 25089647 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 863825 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6682147 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 245340603 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.144660 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.244504 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 27511038 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 94682480 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 97198198 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 25085064 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 863823 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6682260 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 134191 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 348416966 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3358743 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 863825 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 44033987 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38819082 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 289712 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 104520763 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 56701117 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 344543720 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1460141 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 7869954 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 94767 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 8436803 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 28433094 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 3429388 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 394731046 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2217541719 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 335903437 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 192790757 # Number of floating rename lookups +system.cpu.decode.DecodedInsts 348414004 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3355254 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 863823 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44231004 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38750016 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 289461 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 104525811 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 56680488 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 344543449 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1457117 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7869034 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 94704 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 8433947 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 28409379 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 3429059 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 394730853 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2217537837 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 335903225 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 192790660 # Number of floating rename lookups system.cpu.rename.CommittedMaps 372230048 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22500998 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11600 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11566 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 59469204 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89978957 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 84398693 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2368147 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1979963 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 343241150 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22616 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 339372334 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 953627 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 15452166 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36722458 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 496 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 245228486 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.383903 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.138993 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 22500805 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11602 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11569 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 59464824 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89978946 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 84398563 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2367642 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1978869 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343240723 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22618 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 339371435 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 952430 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 15451741 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36726619 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 498 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 245340603 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.383266 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.138851 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 64185587 26.17% 26.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 77296840 31.52% 57.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 59648022 24.32% 82.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34412911 14.03% 96.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 8897509 3.63% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 775021 0.32% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 12596 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 64256390 26.19% 26.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 77349427 31.53% 57.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 59666013 24.32% 82.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34385256 14.02% 96.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 8895869 3.63% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 775150 0.32% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 12498 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 245228486 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 245340603 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8796506 6.82% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7321 0.01% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 160578 0.12% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 165226 0.13% 7.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 81752 0.06% 7.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 59978 0.05% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 823294 0.64% 7.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 313002 0.24% 8.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 382743 0.30% 8.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 27474499 21.29% 29.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 41314471 32.01% 61.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 30691566 23.78% 85.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 18785214 14.56% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8783262 6.81% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7311 0.01% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 160118 0.12% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 165260 0.13% 7.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 81600 0.06% 7.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 59605 0.05% 7.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 821029 0.64% 7.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 312918 0.24% 8.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 382736 0.30% 8.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 27486319 21.30% 29.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 41316597 32.01% 61.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 30690860 23.78% 85.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 18793838 14.56% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 108168622 31.87% 31.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148105 0.63% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 108168046 31.87% 31.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148103 0.63% 32.51% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.51% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.51% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.51% # Type of FU issued @@ -550,93 +550,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.51% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6799290 2.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6799230 2.00% 34.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8596304 2.53% 37.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3207462 0.95% 37.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1592646 0.47% 38.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20838335 6.14% 44.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7175285 2.11% 46.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7140600 2.10% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8596305 2.53% 37.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3207463 0.95% 37.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592644 0.47% 38.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20838397 6.14% 44.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7175267 2.11% 46.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7140594 2.10% 48.82% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 175297 0.05% 48.87% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 46512146 13.71% 62.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 55971174 16.49% 79.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 43494368 12.82% 91.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 27552700 8.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 46512276 13.71% 62.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 55971076 16.49% 79.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 43494028 12.82% 91.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 27552709 8.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 339372334 # Type of FU issued -system.cpu.iq.rate 1.365233 # Inst issue rate -system.cpu.iq.fu_busy_cnt 129056150 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.380279 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 765892553 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 235176629 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 219155615 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 288090378 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 123554179 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 116971321 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 298827775 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 169600709 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5587408 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 339371435 # Type of FU issued +system.cpu.iq.rate 1.364596 # Inst issue rate +system.cpu.iq.fu_busy_cnt 129061453 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.380296 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 766002730 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 235175743 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 219154982 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 288094626 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 123554211 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 116970856 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 298827396 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 169605492 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5587628 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4246682 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7095 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14879 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2023076 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4246671 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7079 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14875 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2022946 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 158632 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 537261 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 158625 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 537538 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 863825 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1349614 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1747627 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 343265167 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 863823 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1349690 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1747618 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343264743 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89978957 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 84398693 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11583 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6712 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1741146 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14879 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 437892 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 454499 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 892391 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 337381646 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 89446380 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1990688 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 89978946 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 84398563 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11585 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6720 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1741103 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14875 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 437791 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 454404 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 892195 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 337380808 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 89446151 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1990627 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1401 # number of nop insts executed -system.cpu.iew.exec_refs 172578078 # number of memory reference insts executed -system.cpu.iew.exec_branches 31542222 # Number of branches executed -system.cpu.iew.exec_stores 83131698 # Number of stores executed -system.cpu.iew.exec_rate 1.357225 # Inst execution rate -system.cpu.iew.wb_sent 336270787 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 336126936 # cumulative count of insts written-back -system.cpu.iew.wb_producers 153093104 # num instructions producing a value -system.cpu.iew.wb_consumers 267318257 # num instructions consuming a value -system.cpu.iew.wb_rate 1.352178 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.572700 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 14160521 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1402 # number of nop insts executed +system.cpu.iew.exec_refs 172577891 # number of memory reference insts executed +system.cpu.iew.exec_branches 31542264 # Number of branches executed +system.cpu.iew.exec_stores 83131740 # Number of stores executed +system.cpu.iew.exec_rate 1.356592 # Inst execution rate +system.cpu.iew.wb_sent 336269596 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 336125838 # cumulative count of insts written-back +system.cpu.iew.wb_producers 153087171 # num instructions producing a value +system.cpu.iew.wb_consumers 267302196 # num instructions consuming a value +system.cpu.iew.wb_rate 1.351545 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.572712 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 14157457 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 850692 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 243036852 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.348817 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.044097 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 243149020 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.348195 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.043585 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 113296519 46.62% 46.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 65998128 27.16% 73.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 21346559 8.78% 82.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13163754 5.42% 87.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8182652 3.37% 91.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4361649 1.79% 93.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2983865 1.23% 94.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2442147 1.00% 95.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11261579 4.63% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 113393055 46.64% 46.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 66012492 27.15% 73.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 21342156 8.78% 82.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13170021 5.42% 87.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8181798 3.36% 91.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4369731 1.80% 93.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2981979 1.23% 94.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2444680 1.01% 95.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11253108 4.63% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 243036852 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 243149020 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037830 # Number of instructions committed system.cpu.commit.committedOps 327812212 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -686,35 +686,35 @@ system.cpu.commit.op_class_0::FloatMemWrite 27367218 8.35% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 327812212 # Class of committed instruction -system.cpu.commit.bw_lim_events 11261579 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 573745483 # The number of ROB reads -system.cpu.rob.rob_writes 686139464 # The number of ROB writes -system.cpu.timesIdled 39266 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3353460 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 11253108 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 573863058 # The number of ROB reads +system.cpu.rob.rob_writes 686133284 # The number of ROB writes +system.cpu.timesIdled 39270 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3356791 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273037218 # Number of Instructions Simulated system.cpu.committedOps 327811600 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.910432 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.910432 # CPI: Total CPI of All Threads -system.cpu.ipc 1.098379 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.098379 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 325197340 # number of integer regfile reads -system.cpu.int_regfile_writes 134110925 # number of integer regfile writes -system.cpu.fp_regfile_reads 186451715 # number of floating regfile reads -system.cpu.fp_regfile_writes 131763174 # number of floating regfile writes -system.cpu.cc_regfile_reads 1279529156 # number of cc regfile reads -system.cpu.cc_regfile_writes 79965327 # number of cc regfile writes -system.cpu.misc_regfile_reads 1056169060 # number of misc regfile reads +system.cpu.cpi 0.910855 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.910855 # CPI: Total CPI of All Threads +system.cpu.ipc 1.097869 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.097869 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 325196483 # number of integer regfile reads +system.cpu.int_regfile_writes 134110146 # number of integer regfile writes +system.cpu.fp_regfile_reads 186451278 # number of floating regfile reads +system.cpu.fp_regfile_writes 131762607 # number of floating regfile writes +system.cpu.cc_regfile_reads 1279524952 # number of cc regfile reads +system.cpu.cc_regfile_writes 79965424 # number of cc regfile writes +system.cpu.misc_regfile_reads 1056166666 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1542798 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.843941 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 161960642 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1543310 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 104.943687 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 91635000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.843941 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999695 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999695 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1542800 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.844324 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 161972906 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1543312 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 104.951498 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 90889000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.844324 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999696 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999696 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id @@ -722,121 +722,121 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 89 system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 333233788 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 333233788 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 80947765 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 80947765 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80921307 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80921307 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 69703 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 69703 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 333232684 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 333232684 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 80960207 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 80960207 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80921128 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80921128 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 69704 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 69704 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10908 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10908 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 161869072 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 161869072 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 161938775 # number of overall hits -system.cpu.dcache.overall_hits::total 161938775 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2753247 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2753247 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1131392 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1131392 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 161881335 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 161881335 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 161951039 # number of overall hits +system.cpu.dcache.overall_hits::total 161951039 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2740251 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2740251 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1131571 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1131571 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3884639 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3884639 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3884657 # number of overall misses -system.cpu.dcache.overall_misses::total 3884657 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 47533202500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 47533202500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9194702918 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9194702918 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3871822 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3871822 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3871840 # number of overall misses +system.cpu.dcache.overall_misses::total 3871840 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 47426688500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 47426688500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9189520410 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9189520410 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 194000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 194000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 56727905418 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 56727905418 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 56727905418 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 56727905418 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 83701012 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 83701012 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 56616208910 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 56616208910 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 56616208910 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 56616208910 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 83700458 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 83700458 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 69721 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 69721 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 69722 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 69722 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10912 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10912 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 165753711 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 165753711 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 165823432 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 165823432 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032894 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032894 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013789 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013789 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 165753157 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 165753157 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 165822879 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 165822879 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032739 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032739 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013791 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013791 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000258 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.000258 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000367 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000367 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023436 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023436 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023426 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023426 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17264.416342 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17264.416342 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8126.894054 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8126.894054 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.023359 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023359 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023349 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023349 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17307.424940 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17307.424940 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8121.028561 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8121.028561 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14603.134401 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14603.134401 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14603.066736 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14603.066736 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14622.626998 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14622.626998 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14622.559018 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14622.559018 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1098365 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1097340 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 136254 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 136170 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8.061158 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1542798 # number of writebacks -system.cpu.dcache.writebacks::total 1542798 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1430654 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1430654 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910668 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 910668 # number of WriteReq MSHR hits +system.cpu.dcache.avg_blocked_cycles::no_targets 8.058603 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 1542800 # number of writebacks +system.cpu.dcache.writebacks::total 1542800 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1417655 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1417655 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910848 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 910848 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2341322 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2341322 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2341322 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2341322 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322593 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1322593 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220724 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 220724 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 2328503 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2328503 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2328503 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2328503 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322596 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1322596 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220723 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 220723 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1543317 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1543317 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1543328 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1543328 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27108294500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27108294500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1845527195 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1845527195 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1269000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1269000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28953821695 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28953821695 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28955090695 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28955090695 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015801 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015801 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1543319 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1543319 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1543330 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1543330 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27069234000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27069234000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1844364193 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1844364193 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1270000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1270000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28913598193 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28913598193 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28914868193 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28914868193 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015802 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015802 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002690 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002690 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000158 # mshr miss rate for SoftPFReq accesses @@ -845,397 +845,396 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009311 system.cpu.dcache.demand_mshr_miss_rate::total 0.009311 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009307 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.009307 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20496.323888 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20496.323888 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8361.243884 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8361.243884 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 115363.636364 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 115363.636364 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18760.774160 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18760.774160 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18761.462693 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18761.462693 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 726144 # number of replacements -system.cpu.icache.tags.tagsinuse 511.811939 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 81493663 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 726656 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 112.148889 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 348619500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.811939 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999633 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999633 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20466.744191 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20466.744191 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8356.012708 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8356.012708 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 115454.545455 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 115454.545455 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18734.686862 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18734.686862 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18735.376227 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18735.376227 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 725912 # number of replacements +system.cpu.icache.tags.tagsinuse 511.812539 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 81490807 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 726424 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 112.180775 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 347441500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.812539 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999634 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999634 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 157 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 100 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 160 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 97 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 70 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 165181558 # Number of tag accesses -system.cpu.icache.tags.data_accesses 165181558 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 81493663 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 81493663 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 81493663 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 81493663 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 81493663 # number of overall hits -system.cpu.icache.overall_hits::total 81493663 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 733780 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 733780 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 733780 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 733780 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 733780 # number of overall misses -system.cpu.icache.overall_misses::total 733780 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 8421387941 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 8421387941 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 8421387941 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 8421387941 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 8421387941 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 8421387941 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 82227443 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 82227443 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 82227443 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 82227443 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 82227443 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 82227443 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008924 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008924 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008924 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008924 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008924 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008924 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11476.720463 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 11476.720463 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 11476.720463 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 11476.720463 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 11476.720463 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 11476.720463 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 139290 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 165175152 # Number of tag accesses +system.cpu.icache.tags.data_accesses 165175152 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 81490807 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 81490807 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 81490807 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 81490807 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 81490807 # number of overall hits +system.cpu.icache.overall_hits::total 81490807 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 733549 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 733549 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 733549 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 733549 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 733549 # number of overall misses +system.cpu.icache.overall_misses::total 733549 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 8424023442 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 8424023442 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 8424023442 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 8424023442 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 8424023442 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 8424023442 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 82224356 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 82224356 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 82224356 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 82224356 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 82224356 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 82224356 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008921 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008921 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008921 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008921 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008921 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008921 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11483.927375 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 11483.927375 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 11483.927375 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 11483.927375 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 11483.927375 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 11483.927375 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 138949 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 124 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4412 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4383 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 31.570716 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 31.701802 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 41.333333 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 726144 # number of writebacks -system.cpu.icache.writebacks::total 726144 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7107 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 7107 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 7107 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 7107 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 7107 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 7107 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726673 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 726673 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 726673 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 726673 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 726673 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 726673 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7893866450 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 7893866450 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7893866450 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 7893866450 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7893866450 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 7893866450 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008837 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008837 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008837 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.008837 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008837 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.008837 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10863.024290 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10863.024290 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10863.024290 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 10863.024290 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10863.024290 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 10863.024290 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 402240 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 402337 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 88 # number of redundant prefetches already in prefetch queue +system.cpu.icache.writebacks::writebacks 725912 # number of writebacks +system.cpu.icache.writebacks::total 725912 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7108 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 7108 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 7108 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 7108 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 7108 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 7108 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726441 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 726441 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 726441 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 726441 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 726441 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 726441 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7897580451 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 7897580451 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7897580451 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 7897580451 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7897580451 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 7897580451 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008835 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008835 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008835 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.008835 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008835 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.008835 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10871.606161 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10871.606161 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10871.606161 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 10871.606161 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10871.606161 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 10871.606161 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 403113 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 403204 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 83 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 28103 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.pfSpanPage 28036 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 5253.910549 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1811940 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 6312 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 287.062738 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 5234.159238 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1826320 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 6292 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 290.260648 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 5156.372421 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 97.538128 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.314720 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005953 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.320673 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 189 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 6123 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 5154.317005 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 79.842232 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.314595 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004873 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.319468 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 172 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 6120 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 12 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::2 48 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 101 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 90 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 542 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 737 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 554 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4127 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011536 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.373718 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 70566797 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 70566797 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 968251 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 968251 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1046259 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1046259 # number of WritebackClean hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 747 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 544 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4124 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.010498 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.373535 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 70559178 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 70559178 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 968252 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 968252 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1046027 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1046027 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 219940 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 219940 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 697144 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 697144 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1094316 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1094316 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 697144 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1314256 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2011400 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 697144 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1314256 # number of overall hits -system.cpu.l2cache.overall_hits::total 2011400 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 219941 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 219941 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 696850 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 696850 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1094381 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1094381 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 696850 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1314322 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2011172 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 696850 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1314322 # number of overall hits +system.cpu.l2cache.overall_hits::total 2011172 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 17 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 17 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 790 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 790 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 29447 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 29447 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 228264 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 228264 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 29447 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 229054 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 258501 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 29447 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 229054 # number of overall misses -system.cpu.l2cache.overall_misses::total 258501 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 42000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 42000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 71200500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 71200500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2623850500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 2623850500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17976905500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 17976905500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 2623850500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 18048106000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20671956500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 2623850500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 18048106000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20671956500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 968251 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 968251 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1046259 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1046259 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 789 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 789 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 29509 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 29509 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 228201 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 228201 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 29509 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 228990 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 258499 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 29509 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 228990 # number of overall misses +system.cpu.l2cache.overall_misses::total 258499 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 43000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 43000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 69993500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 69993500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2629297500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 2629297500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17936282000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 17936282000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 2629297500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 18006275500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20635573000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 2629297500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 18006275500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20635573000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 968252 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 968252 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1046027 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1046027 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 18 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 18 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 220730 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 220730 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 726591 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 726591 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1322580 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1322580 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 726591 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1543310 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2269901 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 726591 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1543310 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2269901 # number of overall (read+write) accesses +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 726359 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 726359 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1322582 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1322582 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 726359 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1543312 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2269671 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 726359 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1543312 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2269671 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.944444 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.944444 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003579 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.003579 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.040528 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.040528 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.172590 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.172590 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.040528 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.148417 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.113882 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.040528 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.148417 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.113882 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2470.588235 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2470.588235 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90127.215190 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90127.215190 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89104.170204 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89104.170204 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78754.886885 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78754.886885 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89104.170204 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78794.109686 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79968.574590 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89104.170204 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78794.109686 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79968.574590 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003575 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.003575 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.040626 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.040626 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.172542 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.172542 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.040626 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.148376 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.113893 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.040626 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.148376 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.113893 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2529.411765 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2529.411765 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88711.660330 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88711.660330 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89101.545291 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89101.545291 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78598.612627 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78598.612627 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89101.545291 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78633.457793 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79828.444211 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89101.545291 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78633.457793 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79828.444211 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 51 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 51 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 56 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 56 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 11 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 34 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 34 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 35 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 35 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 85 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 96 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 91 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 102 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 85 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 96 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 54078 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 54078 # number of HardPFReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::cpu.data 91 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 102 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 54181 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 54181 # number of HardPFReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 17 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 739 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 739 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 29436 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 29436 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 228230 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 228230 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 29436 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 228969 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 258405 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 29436 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 228969 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 54078 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 312483 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 206290287 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 206290287 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 263000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 263000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 65107500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 65107500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2446651000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2446651000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16605070000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16605070000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2446651000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16670177500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19116828500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2446651000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16670177500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 206290287 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19323118787 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 733 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 733 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 29498 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 29498 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 228166 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 228166 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 29498 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 228899 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 258397 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 29498 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 228899 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 54181 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 312578 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 203172843 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 203172843 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 265000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 265000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63769500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63769500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2451726000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2451726000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16564497500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16564497500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2451726000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16628267000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19079993000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2451726000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16628267000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 203172843 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19283165843 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.944444 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.944444 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003348 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003348 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040512 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040512 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172564 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172564 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040512 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148362 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.113840 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040512 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148362 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003321 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003321 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040611 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040611 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172516 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172516 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040611 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148317 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.113848 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040611 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148317 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.137664 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3814.680406 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3814.680406 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15470.588235 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15470.588235 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88102.165088 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88102.165088 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 83117.645060 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 83117.645060 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72755.860316 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72755.860316 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83117.645060 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72805.390686 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73980.102939 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83117.645060 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72805.390686 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3814.680406 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61837.344070 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4538943 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2268977 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254452 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 51443 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51442 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.137720 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3749.890977 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3749.890977 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15588.235294 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15588.235294 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86997.953615 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86997.953615 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 83114.990847 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 83114.990847 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72598.448060 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72598.448060 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83114.990847 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72644.559391 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73839.839472 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83114.990847 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72644.559391 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3749.890977 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61690.732691 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4538483 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2268732 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254880 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 51558 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51557 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 2049252 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 968251 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1300691 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 55450 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 2049022 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 968252 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1300460 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 55547 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 18 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 18 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 220730 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 220730 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 726673 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322580 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2179407 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629454 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6808861 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92974976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197510912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 290485888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 55532 # Total snoops (count) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 726441 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322582 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2178711 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629460 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6808171 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92945280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197511168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 290456448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 55629 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 5248 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2325451 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.131557 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.338010 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 2325318 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.131791 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.338265 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2019523 86.84% 86.84% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 305927 13.16% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2018862 86.82% 86.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 306455 13.18% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2325451 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4538413500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 3.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1090077361 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2325318 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4537953500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 3.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1089727365 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2314996455 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2314999455 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 261057 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 261037 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 253739 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 260300 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 260286 # Transaction distribution system.membus.trans_dist::UpgradeReq 17 # Transaction distribution -system.membus.trans_dist::ReadExReq 739 # Transaction distribution -system.membus.trans_dist::ReadExResp 739 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 260301 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522096 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 522096 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16706496 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 16706496 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 733 # Transaction distribution +system.membus.trans_dist::ReadExResp 733 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 260287 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522056 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 522056 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16705216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 16705216 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 261057 # Request fanout histogram +system.membus.snoop_fanout::samples 261037 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 261057 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 261037 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 261057 # Request fanout histogram -system.membus.reqLayer0.occupancy 317283410 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 261037 # Request fanout histogram +system.membus.reqLayer0.occupancy 316168930 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1389540628 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1389509080 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |