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authorAli Saidi <Ali.Saidi@ARM.com>2012-02-13 12:30:30 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2012-02-13 12:30:30 -0600
commit0d46708dc20c438d29bd724fb7d4b54d4d2f318a (patch)
tree337e1a7404c57817cd08106a0369542ea5c4ac30 /tests/long/se/30.eon/ref
parent9b05e96b9efdb9cdcc4e40ef9c96b1228df7a175 (diff)
downloadgem5-0d46708dc20c438d29bd724fb7d4b54d4d2f318a.tar.xz
bp: fix up stats for changes to branch predictor
Diffstat (limited to 'tests/long/se/30.eon/ref')
-rwxr-xr-xtests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout6
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt454
-rwxr-xr-xtests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout8
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt1048
-rwxr-xr-xtests/long/se/30.eon/ref/arm/linux/o3-timing/simout6
-rw-r--r--tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt1014
6 files changed, 1268 insertions, 1268 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
index b600ef537..371dd4693 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
@@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 11 2012 13:05:17
-gem5 started Feb 11 2012 13:10:43
+gem5 compiled Feb 12 2012 17:15:14
+gem5 started Feb 12 2012 17:34:00
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
@@ -11,4 +11,4 @@ info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.133333
-Exiting @ tick 139995113500 because target called exit()
+Exiting @ tick 141175129500 because target called exit()
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
index 58ea20ddf..6b6e927bf 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
@@ -1,25 +1,25 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.139995 # Number of seconds simulated
-sim_ticks 139995113500 # Number of ticks simulated
-final_tick 139995113500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.141175 # Number of seconds simulated
+sim_ticks 141175129500 # Number of ticks simulated
+final_tick 141175129500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 154307 # Simulator instruction rate (inst/s)
-host_op_rate 154307 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 54186341 # Simulator tick rate (ticks/s)
-host_mem_usage 215920 # Number of bytes of host memory used
-host_seconds 2583.59 # Real time elapsed on the host
+host_inst_rate 157275 # Simulator instruction rate (inst/s)
+host_op_rate 157275 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 55694402 # Simulator tick rate (ticks/s)
+host_mem_usage 215928 # Number of bytes of host memory used
+host_seconds 2534.82 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
sim_ops 398664595 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 469184 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 214784 # Number of instructions bytes read from this memory
+system.physmem.bytes_read 468992 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 214592 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
-system.physmem.num_reads 7331 # Number of read requests responded to by this memory
+system.physmem.num_reads 7328 # Number of read requests responded to by this memory
system.physmem.num_writes 0 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 3351431 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 1534225 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total 3351431 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read 3322058 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 1520041 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 3322058 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@@ -36,10 +36,10 @@ system.cpu.dtb.data_hits 168277058 # DT
system.cpu.dtb.data_misses 56 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 168277114 # DTB accesses
-system.cpu.itb.fetch_hits 48859849 # ITB hits
-system.cpu.itb.fetch_misses 44521 # ITB misses
+system.cpu.itb.fetch_hits 49111850 # ITB hits
+system.cpu.itb.fetch_misses 88782 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 48904370 # ITB accesses
+system.cpu.itb.fetch_accesses 49200632 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -53,16 +53,16 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
-system.cpu.numCycles 279990228 # number of cpu cycles simulated
+system.cpu.numCycles 282350260 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 279561038 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 281921224 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 6809 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 13513618 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 266476610 # Number of cycles cpu stages are processed.
-system.cpu.activity 95.173539 # Percentage of cycles cpu is active
+system.cpu.timesIdled 6799 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 13475974 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 268874286 # Number of cycles cpu stages are processed.
+system.cpu.activity 95.227214 # Percentage of cycles cpu is active
system.cpu.comLoads 94754489 # Number of Load instructions committed
system.cpu.comStores 73520729 # Number of Store instructions committed
system.cpu.comBranches 44587532 # Number of Branches instructions committed
@@ -74,92 +74,92 @@ system.cpu.committedInsts 398664595 # Nu
system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total)
-system.cpu.cpi 0.702320 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 0.708240 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
-system.cpu.cpi_total 0.702320 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.423852 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 0.708240 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.411951 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
-system.cpu.ipc_total 1.423852 # IPC: Total IPC of All Threads
-system.cpu.branch_predictor.lookups 53456377 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 30648707 # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 15206922 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 35068414 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 15659516 # Number of BTB hits
+system.cpu.ipc_total 1.411951 # IPC: Total IPC of All Threads
+system.cpu.branch_predictor.lookups 53870351 # Number of BP lookups
+system.cpu.branch_predictor.condPredicted 30921654 # Number of conditional branches predicted
+system.cpu.branch_predictor.condIncorrect 16037209 # Number of conditional branches incorrect
+system.cpu.branch_predictor.BTBLookups 33426940 # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits 15653987 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target.
-system.cpu.branch_predictor.RASInCorrect 20 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 44.654189 # BTB Hit Percentage
-system.cpu.branch_predictor.predictedTaken 29689183 # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken 23767194 # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads 280275252 # Number of Reads from Int. Register File
+system.cpu.branch_predictor.RASInCorrect 18 # Number of incorrect RAS predictions.
+system.cpu.branch_predictor.BTBHitPct 46.830452 # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken 29683846 # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken 24186505 # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads 280818442 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses 439611111 # Total Accesses (Read+Write) to the Int. Register File
-system.cpu.regfile_manager.floatRegFileReads 119572386 # Number of Reads from FP Register File
+system.cpu.regfile_manager.intRegFileAccesses 440154301 # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.floatRegFileReads 119907697 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File
-system.cpu.regfile_manager.floatRegFileAccesses 219768867 # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 100597400 # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens 168369236 # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect 14604498 # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect 601765 # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted 15206263 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted 29381288 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct 34.104279 # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions 205417549 # Number of Instructions Executed.
-system.cpu.mult_div_unit.multiplies 2124324 # Number of Multipy Operations Executed
+system.cpu.regfile_manager.floatRegFileAccesses 220104178 # Total Accesses (Read+Write) to the FP Register File
+system.cpu.regfile_manager.regForwards 100457644 # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens 168700458 # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect 14475221 # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect 1561329 # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted 16036550 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted 28551001 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct 35.966429 # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions 205750873 # Number of Instructions Executed.
+system.cpu.mult_div_unit.multiplies 2124330 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
-system.cpu.stage0.idleCycles 78021134 # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles 201969094 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 72.134337 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 107567321 # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 172422907 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 61.581759 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 102759298 # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles 177230930 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 63.298970 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 181219893 # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles 98770335 # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 35.276351 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 90498113 # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles 189492115 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 67.678117 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.icache.replacements 1970 # number of replacements
-system.cpu.icache.tagsinuse 1829.847469 # Cycle average of tags in use
-system.cpu.icache.total_refs 48855472 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 3897 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 12536.687708 # Average number of references to valid blocks.
+system.cpu.stage0.idleCycles 78536322 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles 203813938 # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization 72.184788 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 108863639 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 173486621 # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization 61.443762 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 104640873 # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles 177709387 # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization 62.939339 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 183568799 # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles 98781461 # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization 34.985433 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 92657665 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 189692595 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization 67.183432 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.icache.replacements 1974 # number of replacements
+system.cpu.icache.tagsinuse 1829.918694 # Cycle average of tags in use
+system.cpu.icache.total_refs 49107469 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 3901 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 12588.430915 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1829.847469 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.893480 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.893480 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 48855472 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 48855472 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 48855472 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 48855472 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 48855472 # number of overall hits
-system.cpu.icache.overall_hits::total 48855472 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 4376 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 4376 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 4376 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 4376 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 4376 # number of overall misses
-system.cpu.icache.overall_misses::total 4376 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 214318500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 214318500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 214318500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 214318500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 214318500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 214318500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 48859848 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 48859848 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 48859848 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 48859848 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 48859848 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 48859848 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000090 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000090 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000090 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48975.891225 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 48975.891225 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 48975.891225 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1829.918694 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.893515 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.893515 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 49107469 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 49107469 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 49107469 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 49107469 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 49107469 # number of overall hits
+system.cpu.icache.overall_hits::total 49107469 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 4380 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 4380 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 4380 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 4380 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 4380 # number of overall misses
+system.cpu.icache.overall_misses::total 4380 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 214309000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 214309000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 214309000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 214309000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 214309000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 214309000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 49111849 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 49111849 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 49111849 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 49111849 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 49111849 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 49111849 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000089 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000089 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000089 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48928.995434 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 48928.995434 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 48928.995434 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 45000 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -174,34 +174,34 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 479
system.cpu.icache.demand_mshr_hits::total 479 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 479 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 479 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3897 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 3897 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 3897 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 3897 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 3897 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 3897 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 185285000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 185285000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 185285000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 185285000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 185285000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 185285000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses
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@@ -238,16 +238,16 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000013
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@@ -368,42 +368,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
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system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3145 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 3145 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 3356 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3353 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 3975 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 7331 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 3356 # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 7328 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3353 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 3975 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 7331 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134709500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33517000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 168226500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126764000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126764000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134709500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160281000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 294990500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134709500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160281000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 294990500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.861175 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134591000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33517500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 168108500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126757500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126757500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134591000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160275000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 294866000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134591000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160275000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 294866000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876452 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.861175 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.861175 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40139.898689 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40381.927711 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40306.518283 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40139.898689 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40322.264151 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40139.898689 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40322.264151 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.471220 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40382.530120 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40304.451510 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.471220 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40320.754717 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.471220 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40320.754717 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
index d3938f090..39c5315c7 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
@@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 11 2012 13:05:17
-gem5 started Feb 11 2012 13:10:45
+gem5 compiled Feb 12 2012 17:15:14
+gem5 started Feb 12 2012 17:34:05
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
@@ -10,5 +10,5 @@ info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
-OO-style eon Time= 0.083333
-Exiting @ tick 89480174500 because target called exit()
+OO-style eon Time= 0.066667
+Exiting @ tick 80257421500 because target called exit()
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index e5ff3033e..54f4ab1b0 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,45 +1,45 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.089480 # Number of seconds simulated
-sim_ticks 89480174500 # Number of ticks simulated
-final_tick 89480174500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.080257 # Number of seconds simulated
+sim_ticks 80257421500 # Number of ticks simulated
+final_tick 80257421500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 246728 # Simulator instruction rate (inst/s)
-host_op_rate 246728 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 58782597 # Simulator tick rate (ticks/s)
-host_mem_usage 216860 # Number of bytes of host memory used
-host_seconds 1522.22 # Real time elapsed on the host
-sim_insts 375574794 # Number of instructions simulated
-sim_ops 375574794 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 475840 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 219968 # Number of instructions bytes read from this memory
+host_inst_rate 261701 # Simulator instruction rate (inst/s)
+host_op_rate 261701 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 55923550 # Simulator tick rate (ticks/s)
+host_mem_usage 217092 # Number of bytes of host memory used
+host_seconds 1435.13 # Real time elapsed on the host
+sim_insts 375574808 # Number of instructions simulated
+sim_ops 375574808 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read 478528 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 222720 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
-system.physmem.num_reads 7435 # Number of read requests responded to by this memory
+system.physmem.num_reads 7477 # Number of read requests responded to by this memory
system.physmem.num_writes 0 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 5317826 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 2458288 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total 5317826 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read 5962414 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 2775070 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 5962414 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 105444914 # DTB read hits
-system.cpu.dtb.read_misses 94699 # DTB read misses
-system.cpu.dtb.read_acv 48617 # DTB read access violations
-system.cpu.dtb.read_accesses 105539613 # DTB read accesses
-system.cpu.dtb.write_hits 79763652 # DTB write hits
-system.cpu.dtb.write_misses 1536 # DTB write misses
-system.cpu.dtb.write_acv 1 # DTB write access violations
-system.cpu.dtb.write_accesses 79765188 # DTB write accesses
-system.cpu.dtb.data_hits 185208566 # DTB hits
-system.cpu.dtb.data_misses 96235 # DTB misses
-system.cpu.dtb.data_acv 48618 # DTB access violations
-system.cpu.dtb.data_accesses 185304801 # DTB accesses
-system.cpu.itb.fetch_hits 57904086 # ITB hits
-system.cpu.itb.fetch_misses 346 # ITB misses
+system.cpu.dtb.read_hits 103368572 # DTB read hits
+system.cpu.dtb.read_misses 88956 # DTB read misses
+system.cpu.dtb.read_acv 48603 # DTB read access violations
+system.cpu.dtb.read_accesses 103457528 # DTB read accesses
+system.cpu.dtb.write_hits 78975243 # DTB write hits
+system.cpu.dtb.write_misses 1664 # DTB write misses
+system.cpu.dtb.write_acv 3 # DTB write access violations
+system.cpu.dtb.write_accesses 78976907 # DTB write accesses
+system.cpu.dtb.data_hits 182343815 # DTB hits
+system.cpu.dtb.data_misses 90620 # DTB misses
+system.cpu.dtb.data_acv 48606 # DTB access violations
+system.cpu.dtb.data_accesses 182434435 # DTB accesses
+system.cpu.itb.fetch_hits 52487109 # ITB hits
+system.cpu.itb.fetch_misses 461 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 57904432 # ITB accesses
+system.cpu.itb.fetch_accesses 52487570 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -53,315 +53,315 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
-system.cpu.numCycles 178960351 # number of cpu cycles simulated
+system.cpu.numCycles 160514845 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 56765606 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 33143039 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 3552012 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 40427205 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 32022628 # Number of BTB hits
+system.cpu.BPredUnit.lookups 52017212 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 30261257 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 1593315 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 28494887 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 24272738 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 10686505 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 1330 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 59866357 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 502938652 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 56765606 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 42709133 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 93526616 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 12701088 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 16326839 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 180 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 7643 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 57904086 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1110763 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 178838548 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.812250 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.245901 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 9355488 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 4145 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 53524792 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 462212886 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 52017212 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 33628226 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 81457148 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 7754706 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 19283001 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 185 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 7777 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 52487109 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 628108 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 160395311 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.881711 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.314748 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 85311932 47.70% 47.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 8035871 4.49% 52.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 9868460 5.52% 57.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 6372149 3.56% 61.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 13508487 7.55% 68.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 9517347 5.32% 74.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 5905302 3.30% 77.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 3555081 1.99% 79.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 36763919 20.56% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 78938163 49.21% 49.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 4375676 2.73% 51.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 7263628 4.53% 56.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 5613511 3.50% 59.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 12408314 7.74% 67.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 8080182 5.04% 72.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 5692573 3.55% 76.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1906295 1.19% 77.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 36116969 22.52% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 178838548 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.317197 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.810336 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 65738845 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 12641259 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 87702735 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3649079 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 9106630 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 10252982 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 4580 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 491283130 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 12139 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 9106630 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 70077435 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 4396073 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 392991 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 87026850 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 7838569 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 478183111 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 34338 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 6474620 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 310467420 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 626927534 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 331115388 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 295812146 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 259532319 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 50935101 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 38371 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 296 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 21811876 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 110641644 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 85552281 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 8662202 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 5906832 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 433013718 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 258 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 418626838 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 2003473 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 56038444 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 32198216 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 43 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 178838548 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.340809 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.008173 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 160395311 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.324065 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.879565 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 59060129 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 14738019 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 76660368 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 3818816 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 6117979 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 9735972 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 4512 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 456714619 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 12671 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 6117979 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 62341788 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 4786215 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 392111 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 77312738 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 9444480 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 451064099 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 26210 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 7820126 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 294805500 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 593185508 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 313931497 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 279254011 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 35273171 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 38670 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 424 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 27284397 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 106956708 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 81779793 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 8927292 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 6395845 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 416292628 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 359 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 407676624 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1078526 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 40464590 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 19834312 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 144 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 160395311 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.541699 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.006909 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 44336411 24.79% 24.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 29007268 16.22% 41.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 27775406 15.53% 56.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 26238037 14.67% 71.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 22251353 12.44% 83.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 15664112 8.76% 92.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 8263195 4.62% 97.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 3972623 2.22% 99.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1330143 0.74% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 31984575 19.94% 19.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 26488225 16.51% 36.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 26058764 16.25% 52.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 24758572 15.44% 68.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 21531957 13.42% 81.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 15472386 9.65% 91.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 8703569 5.43% 96.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 4094121 2.55% 99.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1303142 0.81% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 178838548 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 160395311 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 135690 1.14% 1.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 41926 0.35% 1.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 2442 0.02% 1.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 8992 0.08% 1.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 1877041 15.76% 17.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 1762283 14.79% 32.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 5120089 42.98% 75.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 2964035 24.88% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 35479 0.30% 0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 74583 0.63% 0.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 5020 0.04% 0.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 3238 0.03% 1.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 1852472 15.62% 16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 1780365 15.01% 31.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 31.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 31.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 5090382 42.92% 74.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 3018331 25.45% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 164031789 39.18% 39.19% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 2126165 0.51% 39.70% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 33716465 8.05% 47.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 7893369 1.89% 49.64% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 2899949 0.69% 50.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 16711518 3.99% 54.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 1573138 0.38% 54.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.70% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 108174365 25.84% 80.54% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 81466499 19.46% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 157965890 38.75% 38.76% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 2126519 0.52% 39.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 33457651 8.21% 47.48% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 7841942 1.92% 49.41% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 2840834 0.70% 50.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 16563363 4.06% 54.17% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 1591033 0.39% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 105252822 25.82% 80.38% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 80002989 19.62% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 418626838 # Type of FU issued
-system.cpu.iq.rate 2.339216 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 11912498 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.028456 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 681277012 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 289109429 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 241633599 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 348731183 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 199993522 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 164553982 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 252486483 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 178019272 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 13980098 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 407676624 # Type of FU issued
+system.cpu.iq.rate 2.539806 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 11859870 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.029091 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 647408174 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 269506276 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 237627844 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 341278781 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 187302066 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 162920489 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 245219921 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 174282992 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 14797631 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 15887158 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 143607 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 50570 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 12031553 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 12202221 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 124163 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 50788 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 8259064 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 233419 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 260903 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 9106630 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 2382208 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 372749 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 458676643 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 2278358 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 110641644 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 85552281 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 258 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 129 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 14 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 50570 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 3441219 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 544657 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 3985876 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 409944817 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 105588265 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 8682021 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 6117979 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 2500869 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 370633 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 441236152 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 174981 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 106956708 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 81779793 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 359 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 125 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 18 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 50788 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 1245732 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 559417 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1805149 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 403162552 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 103506235 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 4514072 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
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system.cpu.commit.function_calls 8007752 # Number of function calls committed.
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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-system.cpu.idleCycles 121803 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 375574794 # Number of Instructions Simulated
-system.cpu.committedOps 375574794 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 375574794 # Number of Instructions Simulated
-system.cpu.cpi 0.476497 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.476497 # CPI: Total CPI of All Threads
-system.cpu.ipc 2.098648 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 2.098648 # IPC: Total IPC of All Threads
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+system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated
+system.cpu.cpi 0.427384 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.427384 # CPI: Total CPI of All Threads
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+system.cpu.ipc_total 2.339814 # IPC: Total IPC of All Threads
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system.cpu.misc_regfile_reads 350572 # number of misc regfile reads
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -370,202 +370,202 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 119653000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30088500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 149741500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 108341500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 108341500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 119653000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 138430000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 258083000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 119653000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 138430000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 258083000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 4164 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1003 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 5167 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 682 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 682 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 3202 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 3202 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 4164 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 4205 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 8369 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 4164 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 4205 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 8369 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.835735 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.867398 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.976577 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.835735 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.950535 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.835735 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.950535 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34383.045977 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34584.482759 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34647.105852 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34383.045977 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34633.475106 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34383.045977 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34633.475106 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -574,42 +574,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3437 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 868 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 4305 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3130 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 3130 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 3437 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 3998 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 7435 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 3437 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 3998 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 7435 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 107040000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27274000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 134314000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98534000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98534000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 107040000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 125808000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 232848000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 107040000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 125808000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 232848000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.851375 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869739 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.979656 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.851375 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.953494 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.851375 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.953494 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31143.439046 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31421.658986 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31480.511182 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31143.439046 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31467.733867 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31143.439046 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31467.733867 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3480 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 870 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 4350 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3127 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 3127 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3480 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 3997 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 7477 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3480 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 3997 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 7477 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 108421000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27340000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 135761000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98470000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98470000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 108421000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 125810000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 234231000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 108421000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 125810000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 234231000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.835735 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867398 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.976577 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.835735 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.950535 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.835735 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.950535 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31155.459770 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31425.287356 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31490.246242 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31155.459770 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31476.107080 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31155.459770 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31476.107080 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
index 347d30ac0..6a43cd1d6 100755
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
@@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 11 2012 13:10:40
-gem5 started Feb 11 2012 15:57:28
+gem5 compiled Feb 12 2012 17:19:56
+gem5 started Feb 12 2012 20:20:40
gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
@@ -13,4 +13,4 @@ info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
OO-style eon Time= 0.100000
-Exiting @ tick 104492506500 because target called exit()
+Exiting @ tick 106128099500 because target called exit()
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
index 242cca723..47e84b8b4 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -1,25 +1,25 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.104493 # Number of seconds simulated
-sim_ticks 104492506500 # Number of ticks simulated
-final_tick 104492506500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.106128 # Number of seconds simulated
+sim_ticks 106128099500 # Number of ticks simulated
+final_tick 106128099500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 158423 # Simulator instruction rate (inst/s)
-host_op_rate 202536 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 60628822 # Simulator tick rate (ticks/s)
-host_mem_usage 231676 # Number of bytes of host memory used
-host_seconds 1723.48 # Real time elapsed on the host
-sim_insts 273038258 # Number of instructions simulated
-sim_ops 349066034 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 464000 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 192512 # Number of instructions bytes read from this memory
+host_inst_rate 157297 # Simulator instruction rate (inst/s)
+host_op_rate 201096 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 61140107 # Simulator tick rate (ticks/s)
+host_mem_usage 232128 # Number of bytes of host memory used
+host_seconds 1735.82 # Real time elapsed on the host
+sim_insts 273038358 # Number of instructions simulated
+sim_ops 349066134 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read 467776 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 196608 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
-system.physmem.num_reads 7250 # Number of read requests responded to by this memory
+system.physmem.num_reads 7309 # Number of read requests responded to by this memory
system.physmem.num_writes 0 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 4440510 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 1842352 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total 4440510 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read 4407655 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 1852554 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 4407655 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -63,105 +63,105 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
-system.cpu.numCycles 208985014 # number of cpu cycles simulated
+system.cpu.numCycles 212256200 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 38314474 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 21092938 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 3256966 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 27298627 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 21213565 # Number of BTB hits
+system.cpu.BPredUnit.lookups 38600701 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 20829729 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 3463171 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 24539034 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 19977747 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 7683795 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 61136 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 43642080 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 338343690 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 38314474 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 28897360 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 78995706 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 10989579 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 78549841 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 92 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 41237520 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 904571 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 208872334 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.119807 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.192773 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 7676103 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 50709 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 45583571 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 349929862 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 38600701 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 27653850 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 79742933 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 11999643 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 78327340 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 3689 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 43047745 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 991560 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 212145839 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.131606 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.210594 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 130527843 62.49% 62.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 9429667 4.51% 67.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 6020154 2.88% 69.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 6750748 3.23% 73.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 5430125 2.60% 75.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 4858478 2.33% 78.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 3783272 1.81% 79.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 4242115 2.03% 81.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 37829932 18.11% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 133058921 62.72% 62.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 9120644 4.30% 67.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 5867847 2.77% 69.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 6815573 3.21% 73.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 5485208 2.59% 75.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 4655113 2.19% 77.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 3623686 1.71% 79.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 4201022 1.98% 81.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 39317825 18.53% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 208872334 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.183336 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.618985 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 51215510 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 73658589 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 72565491 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3819053 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 7613691 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 7463255 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 71181 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 431647720 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 198442 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 7613691 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 58863443 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 1188654 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 57607169 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 68932187 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 14667190 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 416637973 # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents 21102 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 8032684 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 88 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 455385433 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 2446563589 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1351891912 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1094671677 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 384568599 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 70816834 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 3986585 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 4043449 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 48232782 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 108804127 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 93109820 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 3374999 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2307513 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 394258042 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 3864226 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 379117437 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1806866 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 46393196 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 143558304 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 308585 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 208872334 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.815068 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.996247 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 212145839 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.181859 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.648620 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 53244552 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 73538238 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 73218017 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 3725881 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 8419151 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 7680933 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 69313 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 439362017 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 203984 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 8419151 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 60748190 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 1237136 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 57632287 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 69638027 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 14471048 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 424701352 # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents 42052 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 7943055 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 65 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 460812549 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 2479929544 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1407452570 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1072476974 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 384568759 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 76243790 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 3964610 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 4028744 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 48494722 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 109274429 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 96208348 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 3462613 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2507488 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 400084611 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 3851975 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 382840510 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1563616 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 52114616 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 153570381 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 296314 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 212145839 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.804610 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.994995 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 82047947 39.28% 39.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 34785806 16.65% 55.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 24508634 11.73% 67.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 18508923 8.86% 76.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 21724585 10.40% 86.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 15318663 7.33% 94.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 8418302 4.03% 98.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 2689665 1.29% 99.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 869809 0.42% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 84176099 39.68% 39.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 34982222 16.49% 56.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 24755932 11.67% 67.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 18634598 8.78% 76.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 22073169 10.40% 87.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 15324157 7.22% 94.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 8735583 4.12% 98.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 2596961 1.22% 99.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 867118 0.41% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 208872334 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 212145839 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 2261 0.01% 0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 2806 0.02% 0.02% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 5043 0.03% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.04% # attempts to use FU when none available
@@ -181,197 +181,197 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.04% # at
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 10246 0.06% 0.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 2469 0.01% 0.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 378 0.00% 0.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 64552 0.37% 0.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 790 0.00% 0.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 177361 1.02% 1.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 9662090 55.64% 57.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 7440153 42.84% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 40388 0.23% 0.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 3425 0.02% 0.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 360 0.00% 0.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 70580 0.40% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 658 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 165111 0.94% 1.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 9772061 55.35% 56.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 7595169 43.02% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 129612173 34.19% 34.19% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 2147283 0.57% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 15 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 6745842 1.78% 36.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 8678031 2.29% 38.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 3497767 0.92% 39.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 1584514 0.42% 40.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 21146877 5.58% 45.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 7187357 1.90% 47.64% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 7146686 1.89% 49.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.57% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 103748568 27.37% 76.93% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 87447038 23.07% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 132056726 34.49% 34.49% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 2147658 0.56% 35.05% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 35.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 35.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 35.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 35.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 35.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 35.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 35.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 35.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 35.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 35.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 2 0.00% 35.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 35.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 35.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 35.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 35.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 35.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 35.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 35.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 6773802 1.77% 36.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 8676385 2.27% 39.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 3409492 0.89% 39.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 1588042 0.41% 40.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 21173468 5.53% 45.93% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 7175134 1.87% 47.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 7113298 1.86% 49.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 175289 0.05% 49.70% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 104144752 27.20% 76.91% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 88406462 23.09% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 379117437 # Type of FU issued
-system.cpu.iq.rate 1.814089 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 17365346 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.045805 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 735356252 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 310675933 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 251537712 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 250923168 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 133847541 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 118277096 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 267613476 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 128869307 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 7295740 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 382840510 # Type of FU issued
+system.cpu.iq.rate 1.803672 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 17655604 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.046117 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 748490100 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 326330004 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 254739452 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 248555979 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 129729375 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 118008670 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 272729101 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 127767013 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 7377796 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 14155127 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 112471 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 8340 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 10733989 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 14625409 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 156782 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 8434 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 13832497 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 274 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 117 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 260 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 161 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 7613691 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 19337 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 437 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 398169516 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 2638152 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 108804127 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 93109820 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 3853005 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 34 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 205 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 8340 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 3192687 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 308539 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 3501226 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 373035381 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 102118243 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 6082056 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 8419151 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 18839 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 495 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 403985333 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 2312327 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 109274429 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 96208348 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 3840849 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 111 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 202 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 8434 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 3230502 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 526451 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 3756953 # Number of branch mispredicts detected at execute
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system.cpu.iew.exec_swp 0 # number of swp insts executed
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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-system.cpu.commit.committed_per_cycle::5 7589820 3.77% 90.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 3505620 1.74% 92.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3424037 1.70% 94.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 11613199 5.77% 100.00% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.membars 11033 # Number of memory barriers committed
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system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
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system.cpu.commit.function_calls 6225114 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 11613199 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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-system.cpu.idleCycles 112680 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 273038258 # Number of Instructions Simulated
-system.cpu.committedOps 349066034 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 273038258 # Number of Instructions Simulated
-system.cpu.cpi 0.765406 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.765406 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.306497 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.306497 # IPC: Total IPC of All Threads
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+system.cpu.rob.rob_reads 595920425 # The number of ROB reads
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+system.cpu.idleCycles 110361 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 273038358 # Number of Instructions Simulated
+system.cpu.committedOps 349066134 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 273038358 # Number of Instructions Simulated
+system.cpu.cpi 0.777386 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.777386 # CPI: Total CPI of All Threads
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+system.cpu.ipc_total 1.286362 # IPC: Total IPC of All Threads
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.icache.overall_avg_miss_latency::cpu.inst 12075.024027 # average overall miss latency
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 12350.772074 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -380,219 +380,219 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8655.241682 # average overall mshr miss latency
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -601,57 +601,57 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------