diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-11-01 11:56:34 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-11-01 11:56:34 -0400 |
| commit | ccfdc533b9d679f1596d43d647a093885d5e74ab (patch) | |
| tree | 4c785a5e7a7e2d7244fbdbb0a316405898f99e75 /tests/long/se/30.eon/ref | |
| parent | 460cc77d6db46eef34b14a458816084bf6097b32 (diff) | |
| download | gem5-ccfdc533b9d679f1596d43d647a093885d5e74ab.tar.xz | |
stats: Bump stats to match DRAM controller changes
This patch encompasses all the stats updates needed to reflect the
changes to the DRAM controller.
Diffstat (limited to 'tests/long/se/30.eon/ref')
| -rw-r--r-- | tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt | 757 | ||||
| -rw-r--r-- | tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt | 1395 | ||||
| -rw-r--r-- | tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt | 1395 |
3 files changed, 1774 insertions, 1773 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index e5b6926d1..0feb1e331 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.139916 # Number of seconds simulated -sim_ticks 139916242500 # Number of ticks simulated -final_tick 139916242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.139926 # Number of seconds simulated +sim_ticks 139926186500 # Number of ticks simulated +final_tick 139926186500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 80792 # Simulator instruction rate (inst/s) -host_op_rate 80792 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28354866 # Simulator tick rate (ticks/s) -host_mem_usage 231004 # Number of bytes of host memory used -host_seconds 4934.47 # Real time elapsed on the host +host_inst_rate 122800 # Simulator instruction rate (inst/s) +host_op_rate 122800 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43101138 # Simulator tick rate (ticks/s) +host_mem_usage 261428 # Number of bytes of host memory used +host_seconds 3246.46 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory @@ -19,78 +19,80 @@ system.physmem.bytes_inst_read::total 214976 # Nu system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1536462 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1815486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3351948 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1536462 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1536462 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1536462 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1815486 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3351948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7328 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 7328 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 468992 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 468992 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 507 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 643 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 444 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 597 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 448 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 451 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 505 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 513 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 423 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 395 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 336 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 304 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 416 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 534 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 441 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 371 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 139916169000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7328 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1857 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 186 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 1536353 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1815357 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3351710 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1536353 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1536353 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1536353 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1815357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3351710 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7328 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 7328 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 468992 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 468992 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 507 # Per bank write bursts +system.physmem.perBankRdBursts::1 643 # Per bank write bursts +system.physmem.perBankRdBursts::2 444 # Per bank write bursts +system.physmem.perBankRdBursts::3 597 # Per bank write bursts +system.physmem.perBankRdBursts::4 448 # Per bank write bursts +system.physmem.perBankRdBursts::5 451 # Per bank write bursts +system.physmem.perBankRdBursts::6 505 # Per bank write bursts +system.physmem.perBankRdBursts::7 513 # Per bank write bursts +system.physmem.perBankRdBursts::8 423 # Per bank write bursts +system.physmem.perBankRdBursts::9 395 # Per bank write bursts +system.physmem.perBankRdBursts::10 336 # Per bank write bursts +system.physmem.perBankRdBursts::11 304 # Per bank write bursts +system.physmem.perBankRdBursts::12 416 # Per bank write bursts +system.physmem.perBankRdBursts::13 534 # Per bank write bursts +system.physmem.perBankRdBursts::14 441 # Per bank write bursts +system.physmem.perBankRdBursts::15 371 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 139926113000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 7328 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 4635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1820 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 581 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 229 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 62 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -150,98 +152,97 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 702 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 659.145299 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 261.737271 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1246.496021 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 193 27.49% 27.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 99 14.10% 41.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 67 9.54% 51.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 56 7.98% 59.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 35 4.99% 64.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 20 2.85% 66.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 23 3.28% 70.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 21 2.99% 73.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 15 2.14% 75.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 12 1.71% 77.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 9 1.28% 78.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 4 0.57% 78.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 12 1.71% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 8 1.14% 81.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 4 0.57% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 5 0.71% 83.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 15 2.14% 85.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 5 0.71% 85.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 6 0.85% 86.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 1 0.14% 86.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 4 0.57% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 4 0.57% 88.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 4 0.57% 88.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 3 0.43% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 6 0.85% 89.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 6 0.85% 90.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 2 0.28% 91.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 3 0.43% 91.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 2 0.28% 91.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.14% 91.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 3 0.43% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 2 0.28% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 4 0.57% 93.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 2 0.28% 93.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 2 0.28% 93.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.14% 93.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 2 0.28% 94.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 3 0.43% 94.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 2 0.28% 94.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 3 0.43% 95.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.14% 95.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.14% 95.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 1 0.14% 95.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.14% 95.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.14% 96.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 2 0.28% 96.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.14% 96.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.14% 96.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.28% 96.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 1 0.14% 97.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.14% 97.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 1 0.14% 97.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.14% 97.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.14% 97.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.14% 97.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.14% 97.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 1 0.14% 98.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.14% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 1 0.14% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 1 0.14% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.14% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.14% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 1 0.14% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 1 0.14% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 7 1.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 702 # Bytes accessed per row activation -system.physmem.totQLat 39772250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 175041000 # Sum of mem lat for all requests -system.physmem.totBusLat 36640000 # Total cycles spent in databus access -system.physmem.totBankLat 98628750 # Total cycles spent in bank access -system.physmem.avgQLat 5427.44 # Average queueing delay per request -system.physmem.avgBankLat 13459.16 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23886.60 # Average memory access latency -system.physmem.avgRdBW 3.35 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.35 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 1198 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 387.899833 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 185.568922 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 772.018563 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 419 34.97% 34.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 201 16.78% 51.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 128 10.68% 62.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 91 7.60% 70.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 61 5.09% 75.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 40 3.34% 78.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 30 2.50% 80.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 22 1.84% 82.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 25 2.09% 84.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 18 1.50% 86.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 20 1.67% 88.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 8 0.67% 88.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 17 1.42% 90.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 10 0.83% 90.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 8 0.67% 91.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 6 0.50% 92.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 10 0.83% 92.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 7 0.58% 93.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 7 0.58% 94.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 1 0.08% 94.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 4 0.33% 94.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 4 0.33% 94.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 2 0.17% 95.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 5 0.42% 95.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 5 0.42% 95.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 4 0.33% 96.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 1 0.08% 96.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 2 0.17% 96.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 1 0.08% 96.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 2 0.17% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 1 0.08% 96.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 2 0.17% 96.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.08% 97.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 2 0.17% 97.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.08% 97.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.08% 97.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 4 0.33% 97.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 2 0.17% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.08% 98.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 2 0.17% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.08% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.08% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 1 0.08% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 2 0.17% 98.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 1 0.08% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.08% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.08% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.08% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.08% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 1 0.08% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 1 0.08% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 1 0.08% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 1 0.08% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 1 0.08% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 1 0.08% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 1 0.08% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 1 0.08% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 1 0.08% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 2 0.17% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1198 # Bytes accessed per row activation +system.physmem.totQLat 59880500 # Total ticks spent queuing +system.physmem.totMemAccLat 197624250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36640000 # Total ticks spent in databus transfers +system.physmem.totBankLat 101103750 # Total ticks spent accessing banks +system.physmem.avgQLat 8171.47 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13796.91 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26968.37 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.35 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.35 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6626 # Number of row buffer hits during reads +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 6130 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.42 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.65 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19093363.67 # Average gap between requests -system.membus.throughput 3351948 # Throughput (bytes/s) +system.physmem.avgGap 19094720.66 # Average gap between requests +system.physmem.pageHitRate 83.65 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.42 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 3351710 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 4183 # Transaction distribution system.membus.trans_dist::ReadResp 4183 # Transaction distribution system.membus.trans_dist::ReadExReq 3145 # Transaction distribution @@ -252,39 +253,39 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 468992 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 468992 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8796500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8743500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 68414000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 68145750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 53489675 # Number of BP lookups +system.cpu.branchPred.lookups 53489673 # Number of BP lookups system.cpu.branchPred.condPredicted 30685396 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 15149659 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 32882352 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15212540 # Number of BTB hits +system.cpu.branchPred.BTBLookups 32882350 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15212538 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 46.263540 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 46.263537 # BTB Hit Percentage system.cpu.branchPred.usedRAS 8007516 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 20 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 94754653 # DTB read hits +system.cpu.dtb.read_hits 94754637 # DTB read hits system.cpu.dtb.read_misses 21 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 94754674 # DTB read accesses -system.cpu.dtb.write_hits 73521120 # DTB write hits +system.cpu.dtb.read_accesses 94754658 # DTB read accesses +system.cpu.dtb.write_hits 73521124 # DTB write hits system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73521155 # DTB write accesses -system.cpu.dtb.data_hits 168275773 # DTB hits +system.cpu.dtb.write_accesses 73521159 # DTB write accesses +system.cpu.dtb.data_hits 168275761 # DTB hits system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168275829 # DTB accesses -system.cpu.itb.fetch_hits 48611327 # ITB hits +system.cpu.dtb.data_accesses 168275817 # DTB accesses +system.cpu.itb.fetch_hits 48611324 # ITB hits system.cpu.itb.fetch_misses 44520 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 48655847 # ITB accesses +system.cpu.itb.fetch_accesses 48655844 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -298,18 +299,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 279832486 # number of cpu cycles simulated +system.cpu.numCycles 279852374 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 29230507 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedTaken 29230505 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 24259168 # Number of Branches Predicted As Not Taken (False). system.cpu.regfile_manager.intRegFileReads 280386579 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File system.cpu.regfile_manager.intRegFileAccesses 439722438 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 119631954 # Number of Reads from FP Register File +system.cpu.regfile_manager.floatRegFileReads 119631950 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 219828435 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100484570 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.floatRegFileAccesses 219828431 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 100484574 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 168485322 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken). @@ -320,12 +321,12 @@ system.cpu.execution_unit.executions 205475782 # Nu system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 279400467 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 279400617 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7142 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13525828 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 266306658 # Number of cycles cpu stages are processed. -system.cpu.activity 95.166455 # Percentage of cycles cpu is active +system.cpu.timesIdled 7206 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13545708 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 266306666 # Number of cycles cpu stages are processed. +system.cpu.activity 95.159695 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -337,72 +338,72 @@ system.cpu.committedInsts 398664595 # Nu system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) -system.cpu.cpi 0.701925 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.701974 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.701925 # CPI: Total CPI of All Threads -system.cpu.ipc 1.424654 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.701974 # CPI: Total CPI of All Threads +system.cpu.ipc 1.424553 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.424654 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 78084810 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 201747676 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 72.095874 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 107180757 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 172651729 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.698244 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 102617259 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 177215227 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 63.329040 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 181087860 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 98744626 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 35.287049 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 90364523 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 189467963 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.707637 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.424553 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 78104700 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 201747674 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 72.090750 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 107200641 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 172651733 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 61.693860 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 102637143 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 177215231 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 63.324541 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 181107759 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 98744615 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 35.284537 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 90384394 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 189467980 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 67.702831 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 1975 # number of replacements -system.cpu.icache.tags.tagsinuse 1830.971183 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 48606795 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1830.939408 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 48606790 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3903 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12453.700999 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 12453.699718 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1830.971183 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.894029 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.894029 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 48606795 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 48606795 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 48606795 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 48606795 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 48606795 # number of overall hits -system.cpu.icache.overall_hits::total 48606795 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4532 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4532 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4532 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4532 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4532 # number of overall misses -system.cpu.icache.overall_misses::total 4532 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 272220250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 272220250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 272220250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 272220250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 272220250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 272220250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 48611327 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 48611327 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 48611327 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 48611327 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 48611327 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 48611327 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1830.939408 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894013 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894013 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 48606790 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 48606790 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 48606790 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 48606790 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 48606790 # number of overall hits +system.cpu.icache.overall_hits::total 48606790 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4534 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4534 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4534 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4534 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4534 # number of overall misses +system.cpu.icache.overall_misses::total 4534 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 280061250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 280061250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 280061250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 280061250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 280061250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 280061250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 48611324 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 48611324 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 48611324 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 48611324 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 48611324 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 48611324 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60066.251103 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 60066.251103 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 60066.251103 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 60066.251103 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 60066.251103 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 60066.251103 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61769.133216 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61769.133216 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61769.133216 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61769.133216 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61769.133216 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61769.133216 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 330 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -411,38 +412,38 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 110 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 629 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 629 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 629 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 629 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 629 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 629 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 631 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 631 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 631 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 631 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 631 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 631 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3903 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 3903 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 3903 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 3903 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3903 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3903 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 236384250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 236384250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 236384250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 236384250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 236384250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 236384250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 244179750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 244179750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 244179750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 244179750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 244179750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 244179750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60564.757879 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60564.757879 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60564.757879 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60564.757879 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60564.757879 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60564.757879 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62562.067640 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62562.067640 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62562.067640 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 62562.067640 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62562.067640 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 62562.067640 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 3981353 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 3981070 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 4850 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 4850 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution @@ -458,23 +459,23 @@ system.cpu.toL2Bus.data_through_bus 557056 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 5001000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6540750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6459750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6779999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6671999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3906.944649 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3906.845611 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 753 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4717 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.159635 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 370.550028 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.807922 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 627.586699 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 370.534640 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.739390 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 627.571581 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088770 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088768 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.019152 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.119230 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.119227 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 544 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 667 # number of ReadReq hits @@ -499,17 +500,17 @@ system.cpu.l2cache.demand_misses::total 7328 # nu system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7328 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 226995250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 59463500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 286458750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 214640250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 214640250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 226995250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 274103750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 501099000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 226995250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 274103750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 501099000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 234790750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 62080250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 296871000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 227075250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 227075250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 234790750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 289155500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 523946250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 234790750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 289155500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 523946250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3903 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4850 # number of ReadReq accesses(hits+misses) @@ -534,17 +535,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.909745 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.860620 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.909745 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67578.222685 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72164.441748 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68481.651924 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68248.092210 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68248.092210 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67578.222685 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69061.161502 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68381.413755 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67578.222685 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69061.161502 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68381.413755 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69899.002679 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75340.109223 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70970.834329 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72201.987281 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72201.987281 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69899.002679 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72853.489544 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71499.215338 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69899.002679 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72853.489544 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71499.215338 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -564,17 +565,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7328 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 184726250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 49135000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 233861250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 175601750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 175601750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 184726250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 224736750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 409463000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 184726250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 224736750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 409463000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 192686250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 51812250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 244498500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 188269250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 188269250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192686250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 240081500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 432767750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192686250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 240081500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 432767750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses @@ -586,51 +587,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54994.417982 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59629.854369 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55907.542434 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55835.214626 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55835.214626 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54994.417982 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56623.015873 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55876.501092 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54994.417982 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56623.015873 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55876.501092 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57364.170884 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62878.944175 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58450.513985 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59863.036566 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59863.036566 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57364.170884 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60489.166037 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59056.734443 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57364.170884 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60489.166037 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59056.734443 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 764 # number of replacements -system.cpu.dcache.tags.tagsinuse 3284.967259 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168254256 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3284.890275 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168254255 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40523.664740 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40523.664499 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3284.967259 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.801994 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.801994 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3284.890275 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.801975 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.801975 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94753181 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753181 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501075 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501075 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168254256 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168254256 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168254256 # number of overall hits -system.cpu.dcache.overall_hits::total 168254256 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501074 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501074 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168254255 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168254255 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168254255 # number of overall hits +system.cpu.dcache.overall_hits::total 168254255 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1308 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1308 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19654 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19654 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 20962 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20962 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 20962 # number of overall misses -system.cpu.dcache.overall_misses::total 20962 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 85220999 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 85220999 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1076127000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1076127000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1161347999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1161347999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1161347999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1161347999 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 19655 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19655 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 20963 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20963 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 20963 # number of overall misses +system.cpu.dcache.overall_misses::total 20963 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88453749 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88453749 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1129220750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1129220750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1217674499 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1217674499 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1217674499 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1217674499 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -647,19 +648,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000125 system.cpu.dcache.demand_miss_rate::total 0.000125 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000125 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000125 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65153.668960 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 65153.668960 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54753.587056 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54753.587056 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55402.537878 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55402.537878 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55402.537878 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55402.537878 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29647 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67625.190367 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67625.190367 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57452.085983 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57452.085983 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 58086.843438 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 58086.843438 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 58086.843438 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 58086.843438 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33688 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 596 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 584 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.743289 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.684932 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -667,12 +668,12 @@ system.cpu.dcache.writebacks::writebacks 649 # nu system.cpu.dcache.writebacks::total 649 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 358 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 358 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16452 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16452 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 16810 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 16810 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 16810 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 16810 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16453 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16453 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16811 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16811 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16811 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16811 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses @@ -681,14 +682,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 61946751 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 61946751 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 218347750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 218347750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 280294501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 280294501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 280294501 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 280294501 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 64535001 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 64535001 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 230815000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 230815000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 295350001 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 295350001 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 295350001 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 295350001 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -697,14 +698,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65207.106316 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65207.106316 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68191.052467 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68191.052467 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67508.309489 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67508.309489 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67508.309489 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67508.309489 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67931.580000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67931.580000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72084.634603 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72084.634603 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71134.393304 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71134.393304 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71134.393304 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71134.393304 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index e492ac5d0..c079ee28b 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,96 +1,98 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.077522 # Number of seconds simulated -sim_ticks 77521581000 # Number of ticks simulated -final_tick 77521581000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.077516 # Number of seconds simulated +sim_ticks 77516381000 # Number of ticks simulated +final_tick 77516381000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 201802 # Simulator instruction rate (inst/s) -host_op_rate 201802 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41653613 # Simulator tick rate (ticks/s) -host_mem_usage 236024 # Number of bytes of host memory used -host_seconds 1861.10 # Real time elapsed on the host +host_inst_rate 185827 # Simulator instruction rate (inst/s) +host_op_rate 185827 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38353496 # Simulator tick rate (ticks/s) +host_mem_usage 262456 # Number of bytes of host memory used +host_seconds 2021.10 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 220992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255296 # Number of bytes read from this memory -system.physmem.bytes_read::total 476288 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 220992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 220992 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3453 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3989 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7442 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2850716 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3293225 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6143941 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2850716 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2850716 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2850716 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3293225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6143941 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7442 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 7442 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 476288 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 476288 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 527 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 653 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 447 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 600 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 447 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 455 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 517 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 524 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 436 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 405 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 337 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 305 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 414 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 542 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 454 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 379 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 77521491500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7442 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2027 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 699 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 221184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255424 # Number of bytes read from this memory +system.physmem.bytes_read::total 476608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221184 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3456 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3991 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7447 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2853384 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3295097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6148481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2853384 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2853384 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2853384 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3295097 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6148481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7447 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 7447 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 476608 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 476608 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 524 # Per bank write bursts +system.physmem.perBankRdBursts::1 653 # Per bank write bursts +system.physmem.perBankRdBursts::2 449 # Per bank write bursts +system.physmem.perBankRdBursts::3 600 # Per bank write bursts +system.physmem.perBankRdBursts::4 447 # Per bank write bursts +system.physmem.perBankRdBursts::5 455 # Per bank write bursts +system.physmem.perBankRdBursts::6 515 # Per bank write bursts +system.physmem.perBankRdBursts::7 524 # Per bank write bursts +system.physmem.perBankRdBursts::8 439 # Per bank write bursts +system.physmem.perBankRdBursts::9 407 # Per bank write bursts +system.physmem.perBankRdBursts::10 340 # Per bank write bursts +system.physmem.perBankRdBursts::11 306 # Per bank write bursts +system.physmem.perBankRdBursts::12 414 # Per bank write bursts +system.physmem.perBankRdBursts::13 542 # Per bank write bursts +system.physmem.perBankRdBursts::14 453 # Per bank write bursts +system.physmem.perBankRdBursts::15 379 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 77516291500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 7447 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 4394 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2044 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 706 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 246 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 55 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -150,138 +152,133 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 756 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 621.460317 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 241.668493 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1200.727367 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 238 31.48% 31.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 108 14.29% 45.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 62 8.20% 53.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 57 7.54% 61.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 33 4.37% 65.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 22 2.91% 68.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 21 2.78% 71.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 18 2.38% 73.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 13 1.72% 75.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 16 2.12% 77.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 6 0.79% 78.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 12 1.59% 80.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 9 1.19% 81.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 9 1.19% 82.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 5 0.66% 83.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 6 0.79% 83.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 17 2.25% 86.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 4 0.53% 86.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 4 0.53% 87.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 2 0.26% 87.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 3 0.40% 87.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 7 0.93% 88.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 4 0.53% 89.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 4 0.53% 89.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.40% 90.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 6 0.79% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 7 0.93% 92.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 1 0.13% 92.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 4 0.53% 92.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 3 0.40% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 1 0.13% 93.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 4 0.53% 93.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 3 0.40% 94.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 2 0.26% 94.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 2 0.26% 94.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.13% 94.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 1 0.13% 94.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 1 0.13% 95.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.13% 95.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 2 0.26% 95.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 3 0.40% 95.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 2 0.26% 96.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.13% 96.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 2 0.26% 96.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.13% 96.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.13% 96.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.13% 96.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.26% 97.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 1 0.13% 97.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.13% 97.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 2 0.26% 97.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.13% 97.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.13% 98.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.13% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.13% 98.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 1 0.13% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 1 0.13% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.13% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.13% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 1 0.13% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 1 0.13% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 7 0.93% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 756 # Bytes accessed per row activation -system.physmem.totQLat 42048500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 179991000 # Sum of mem lat for all requests -system.physmem.totBusLat 37210000 # Total cycles spent in databus access -system.physmem.totBankLat 100732500 # Total cycles spent in bank access -system.physmem.avgQLat 5650.16 # Average queueing delay per request -system.physmem.avgBankLat 13535.68 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24185.84 # Average memory access latency -system.physmem.avgRdBW 6.14 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 6.14 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 1164 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 404.618557 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.969320 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 801.678722 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 417 35.82% 35.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 184 15.81% 51.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 111 9.54% 61.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 97 8.33% 69.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 49 4.21% 73.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 38 3.26% 76.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 28 2.41% 79.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 28 2.41% 81.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 22 1.89% 83.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 22 1.89% 85.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 9 0.77% 86.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 13 1.12% 87.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 15 1.29% 88.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 15 1.29% 90.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 6 0.52% 90.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 7 0.60% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 16 1.37% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 3 0.26% 92.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 5 0.43% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 2 0.17% 93.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 3 0.26% 93.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 11 0.95% 94.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 4 0.34% 94.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 6 0.52% 95.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.26% 95.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 4 0.34% 96.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 3 0.26% 96.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 3 0.26% 96.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 3 0.26% 96.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 3 0.26% 97.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 2 0.17% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 5 0.43% 97.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.09% 97.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.09% 97.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 2 0.17% 98.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.09% 98.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.09% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 1 0.09% 98.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 2 0.17% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 2 0.17% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.09% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 1 0.09% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 1 0.09% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 2 0.17% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 1 0.09% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 1 0.09% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 1 0.09% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 1 0.09% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.09% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.09% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 1 0.09% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.09% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 3 0.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1164 # Bytes accessed per row activation +system.physmem.totQLat 59913750 # Total ticks spent queuing +system.physmem.totMemAccLat 199861250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37235000 # Total ticks spent in databus transfers +system.physmem.totBankLat 102712500 # Total ticks spent accessing banks +system.physmem.avgQLat 8045.35 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13792.47 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26837.82 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.15 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.15 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6686 # Number of row buffer hits during reads +system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 6283 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.84 # Row buffer hit rate for reads +system.physmem.readRowHitRate 84.37 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 10416755.11 # Average gap between requests -system.membus.throughput 6143941 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4310 # Transaction distribution -system.membus.trans_dist::ReadResp 4310 # Transaction distribution -system.membus.trans_dist::ReadExReq 3132 # Transaction distribution -system.membus.trans_dist::ReadExResp 3132 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14884 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14884 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476288 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 476288 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 476288 # Total data (bytes) +system.physmem.avgGap 10409062.91 # Average gap between requests +system.physmem.pageHitRate 84.37 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.56 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 6148481 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4317 # Transaction distribution +system.membus.trans_dist::ReadResp 4317 # Transaction distribution +system.membus.trans_dist::ReadExReq 3130 # Transaction distribution +system.membus.trans_dist::ReadExResp 3130 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14894 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476608 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 476608 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 476608 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 9304000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9290500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 69668500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 69563000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.branchPred.lookups 50329141 # Number of BP lookups -system.cpu.branchPred.condPredicted 29286929 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1209855 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26570475 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23288927 # Number of BTB hits +system.cpu.branchPred.lookups 50307165 # Number of BP lookups +system.cpu.branchPred.condPredicted 29267262 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1212205 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 26317362 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23268236 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.649645 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9008918 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1078 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 88.414014 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9019862 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1049 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 101805775 # DTB read hits -system.cpu.dtb.read_misses 78244 # DTB read misses -system.cpu.dtb.read_acv 48603 # DTB read access violations -system.cpu.dtb.read_accesses 101884019 # DTB read accesses -system.cpu.dtb.write_hits 78424815 # DTB write hits -system.cpu.dtb.write_misses 1501 # DTB write misses -system.cpu.dtb.write_acv 3 # DTB write access violations -system.cpu.dtb.write_accesses 78426316 # DTB write accesses -system.cpu.dtb.data_hits 180230590 # DTB hits -system.cpu.dtb.data_misses 79745 # DTB misses -system.cpu.dtb.data_acv 48606 # DTB access violations -system.cpu.dtb.data_accesses 180310335 # DTB accesses -system.cpu.itb.fetch_hits 50278510 # ITB hits -system.cpu.itb.fetch_misses 355 # ITB misses +system.cpu.dtb.read_hits 101828804 # DTB read hits +system.cpu.dtb.read_misses 77910 # DTB read misses +system.cpu.dtb.read_acv 48604 # DTB read access violations +system.cpu.dtb.read_accesses 101906714 # DTB read accesses +system.cpu.dtb.write_hits 78465960 # DTB write hits +system.cpu.dtb.write_misses 1494 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 78467454 # DTB write accesses +system.cpu.dtb.data_hits 180294764 # DTB hits +system.cpu.dtb.data_misses 79404 # DTB misses +system.cpu.dtb.data_acv 48608 # DTB access violations +system.cpu.dtb.data_accesses 180374168 # DTB accesses +system.cpu.itb.fetch_hits 50297233 # ITB hits +system.cpu.itb.fetch_misses 369 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 50278865 # ITB accesses +system.cpu.itb.fetch_accesses 50297602 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -295,139 +292,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 155043164 # number of cpu cycles simulated +system.cpu.numCycles 155032764 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 51171798 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 449189873 # Number of instructions fetch has processed -system.cpu.fetch.Branches 50329141 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 32297845 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 78873322 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6177793 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19775166 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 51194246 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 449183514 # Number of instructions fetch has processed +system.cpu.fetch.Branches 50307165 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 32288098 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 78871438 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6172162 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19742012 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 181 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 10164 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 10560 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 50278510 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 413807 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 154759425 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.902504 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.324797 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 50297233 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 412893 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 154739148 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.902843 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.324835 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 75886103 49.03% 49.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4289159 2.77% 51.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6884479 4.45% 56.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5373987 3.47% 59.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11775541 7.61% 67.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 7819980 5.05% 72.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5600753 3.62% 76.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1832171 1.18% 77.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35297252 22.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 75867710 49.03% 49.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4287409 2.77% 51.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6889018 4.45% 56.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5374428 3.47% 59.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11763624 7.60% 67.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 7816659 5.05% 72.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5616009 3.63% 76.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1833388 1.18% 77.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35290903 22.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154759425 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.324614 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.897192 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 56546720 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 15105326 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74238970 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3943829 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4924580 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9495837 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4282 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 445245835 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12211 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4924580 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 59688043 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4892244 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 416020 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 75141817 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9696721 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 440741300 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 165 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 25268 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8017940 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 287478957 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 579418122 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 413955402 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 165462719 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 154739148 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.324494 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.897346 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 56553427 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 15088868 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74238964 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3941388 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4916501 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9487391 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4280 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 445247205 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12161 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4916501 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 59699524 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4890372 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 419538 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 75126102 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9687111 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 440708166 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 170 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 18989 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8005915 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 287519835 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 579387338 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 414037453 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 165349884 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27946628 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 36876 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 265 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 27780890 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104697675 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80623147 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8951892 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6419862 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 408420930 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 258 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 401925039 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 976126 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32712161 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15467708 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 43 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154759425 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.597096 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.996071 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 27987506 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 36934 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 290 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 27862892 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104720393 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80633883 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8938676 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6410471 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 408405086 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 279 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 401961013 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 974296 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32695397 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15321619 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 64 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154739148 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.597669 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.996651 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 28451061 18.38% 18.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 25861408 16.71% 35.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25614965 16.55% 51.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 24252162 15.67% 67.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21259746 13.74% 81.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15502795 10.02% 91.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8516760 5.50% 96.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3980528 2.57% 99.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1320000 0.85% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 28425453 18.37% 18.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 25900888 16.74% 35.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25580332 16.53% 51.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24228882 15.66% 67.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21279906 13.75% 81.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15505584 10.02% 91.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8490760 5.49% 96.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3998033 2.58% 99.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1329310 0.86% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154759425 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154739148 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 34116 0.29% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 33873 0.29% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 59668 0.50% 0.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 5432 0.05% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 5299 0.04% 0.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1955339 16.54% 17.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1744150 14.75% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5075259 42.92% 75.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2944520 24.90% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 57850 0.49% 0.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 5381 0.05% 0.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 5383 0.05% 0.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1948507 16.46% 17.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1748153 14.77% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5077907 42.90% 74.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2960216 25.01% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 155814394 38.77% 38.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126224 0.53% 39.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32839124 8.17% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7506811 1.87% 49.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2794214 0.70% 50.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16556558 4.12% 54.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1581320 0.39% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 155836210 38.77% 38.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126206 0.53% 39.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32826139 8.17% 47.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7503461 1.87% 49.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2792900 0.69% 50.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16557877 4.12% 54.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1579224 0.39% 54.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.55% # Type of FU issued @@ -449,84 +446,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.55% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103393269 25.72% 80.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 79279544 19.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103415840 25.73% 80.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 79289575 19.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 401925039 # Type of FU issued -system.cpu.iq.rate 2.592343 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11823783 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.029418 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 634356878 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 260386455 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 234772610 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 337052534 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 180795959 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 161415506 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 241485172 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 172230069 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 15009534 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 401961013 # Type of FU issued +system.cpu.iq.rate 2.592749 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11837270 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.029449 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 634505765 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 260497209 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 234812476 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 336966975 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 180652533 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 161419314 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 241576218 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172188484 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 15052407 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 9943188 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 112068 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 49084 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7102418 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 9965906 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 111384 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 48996 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7113154 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 260799 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3689 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 260897 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3921 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4924580 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2516499 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 372884 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 433248692 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 121349 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104697675 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80623147 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 258 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 99 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 81 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 49084 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 956530 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 406825 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1363355 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 398354690 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101932663 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3570349 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4916501 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2514816 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 370985 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 433209224 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 130314 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104720393 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80633883 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 279 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 90 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 76 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 48996 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 956631 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 408580 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1365211 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 398393230 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101955347 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3567783 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24827504 # number of nop insts executed -system.cpu.iew.exec_refs 180359006 # number of memory reference insts executed -system.cpu.iew.exec_branches 46573877 # Number of branches executed -system.cpu.iew.exec_stores 78426343 # Number of stores executed -system.cpu.iew.exec_rate 2.569315 # Inst execution rate -system.cpu.iew.wb_sent 396825960 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 396188116 # cumulative count of insts written-back -system.cpu.iew.wb_producers 193569295 # num instructions producing a value -system.cpu.iew.wb_consumers 271188688 # num instructions consuming a value +system.cpu.iew.exec_nop 24803859 # number of nop insts executed +system.cpu.iew.exec_refs 180422830 # number of memory reference insts executed +system.cpu.iew.exec_branches 46575028 # Number of branches executed +system.cpu.iew.exec_stores 78467483 # Number of stores executed +system.cpu.iew.exec_rate 2.569736 # Inst execution rate +system.cpu.iew.wb_sent 396861812 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 396231790 # cumulative count of insts written-back +system.cpu.iew.wb_producers 193564450 # num instructions producing a value +system.cpu.iew.wb_consumers 271143007 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.555341 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.713781 # average fanout of values written-back +system.cpu.iew.wb_rate 2.555794 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.713883 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 34614887 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 34575269 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1205659 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149834845 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.660693 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.995613 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1208013 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149822647 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.660910 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.995203 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 55453685 37.01% 37.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 22592497 15.08% 52.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13053957 8.71% 60.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11447163 7.64% 68.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8190236 5.47% 73.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5440968 3.63% 77.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5148789 3.44% 80.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3296235 2.20% 83.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 25211315 16.83% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 55444792 37.01% 37.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22572343 15.07% 52.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13039784 8.70% 60.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11474023 7.66% 68.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8200661 5.47% 73.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5438800 3.63% 77.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5171862 3.45% 80.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3280269 2.19% 83.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 25200113 16.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149834845 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 149822647 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -537,212 +534,212 @@ system.cpu.commit.branches 44587533 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 25211315 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 25200113 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 557900023 # The number of ROB reads -system.cpu.rob.rob_writes 871491746 # The number of ROB writes -system.cpu.timesIdled 3551 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 283739 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 557859409 # The number of ROB reads +system.cpu.rob.rob_writes 871404727 # The number of ROB writes +system.cpu.timesIdled 3579 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 293616 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated -system.cpu.cpi 0.412816 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.412816 # CPI: Total CPI of All Threads -system.cpu.ipc 2.422389 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.422389 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 398140602 # number of integer regfile reads -system.cpu.int_regfile_writes 170166273 # number of integer regfile writes -system.cpu.fp_regfile_reads 156587084 # number of floating regfile reads -system.cpu.fp_regfile_writes 104079306 # number of floating regfile writes +system.cpu.cpi 0.412788 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.412788 # CPI: Total CPI of All Threads +system.cpu.ipc 2.422551 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.422551 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 398219851 # number of integer regfile reads +system.cpu.int_regfile_writes 170183529 # number of integer regfile writes +system.cpu.fp_regfile_reads 156589680 # number of floating regfile reads +system.cpu.fp_regfile_writes 104065109 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 7370748 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 5062 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5062 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 666 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3200 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3200 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8148 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9042 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 17190 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 571392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 571392 # Total data (bytes) +system.cpu.toL2Bus.throughput 7356381 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 5061 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5061 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 659 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3190 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8138 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9023 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 17161 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 570240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 570240 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 5130000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 5114000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6844000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6775000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6767250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6675000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 2147 # number of replacements -system.cpu.icache.tags.tagsinuse 1831.618681 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 50272888 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4074 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12339.933235 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2141 # number of replacements +system.cpu.icache.tags.tagsinuse 1831.580097 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 50291613 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4069 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12359.698452 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1831.618681 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.894345 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.894345 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 50272888 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 50272888 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 50272888 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 50272888 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 50272888 # number of overall hits -system.cpu.icache.overall_hits::total 50272888 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5622 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5622 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5622 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5622 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5622 # number of overall misses -system.cpu.icache.overall_misses::total 5622 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 322487500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 322487500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 322487500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 322487500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 322487500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 322487500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 50278510 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 50278510 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 50278510 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 50278510 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 50278510 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 50278510 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1831.580097 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894326 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894326 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 50291613 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 50291613 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 50291613 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 50291613 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 50291613 # number of overall hits +system.cpu.icache.overall_hits::total 50291613 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5620 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5620 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5620 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5620 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5620 # number of overall misses +system.cpu.icache.overall_misses::total 5620 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 330576500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 330576500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 330576500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 330576500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 330576500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 330576500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 50297233 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 50297233 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 50297233 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 50297233 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 50297233 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 50297233 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000112 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000112 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000112 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000112 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000112 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000112 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 57361.704020 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 57361.704020 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 57361.704020 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 57361.704020 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 57361.704020 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 57361.704020 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 272 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58821.441281 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 58821.441281 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 58821.441281 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 58821.441281 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 58821.441281 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 58821.441281 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 892 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 68 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 148.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1548 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1548 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1548 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1548 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1548 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1548 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4074 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4074 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4074 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4074 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4074 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4074 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 242677000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 242677000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 242677000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 242677000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 242677000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 242677000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1551 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1551 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1551 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1551 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1551 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1551 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4069 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4069 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4069 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4069 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4069 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4069 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249127500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 249127500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249127500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 249127500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249127500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 249127500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000081 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000081 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59567.255768 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59567.255768 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59567.255768 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 59567.255768 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59567.255768 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 59567.255768 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61225.731138 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61225.731138 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61225.731138 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61225.731138 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61225.731138 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61225.731138 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4008.519135 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 851 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4844 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.175681 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 4006.698259 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 830 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4855 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.170958 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 371.365398 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2979.019245 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 658.134493 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011333 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.090912 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.020085 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.122330 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 621 # number of ReadReq hits +system.cpu.l2cache.tags.occ_blocks::writebacks 372.314002 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2972.989124 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 661.395133 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011362 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.090728 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.020184 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.122275 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 613 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 131 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 752 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 666 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 666 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 68 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 68 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 621 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 199 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 820 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 621 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 199 # number of overall hits -system.cpu.l2cache.overall_hits::total 820 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3453 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 857 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4310 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 3132 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 3132 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3453 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3989 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7442 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3453 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3989 # number of overall misses -system.cpu.l2cache.overall_misses::total 7442 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 232383750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 65132000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 297515750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 214217750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 214217750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 232383750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 279349750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 511733500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 232383750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 279349750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 511733500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 4074 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 988 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5062 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 666 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 666 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 3200 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 3200 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4074 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 4188 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 8262 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4074 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4188 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 8262 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.847570 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.867409 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.851442 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.978750 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.978750 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.847570 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.952483 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.900750 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.847570 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.952483 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.900750 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67299.087750 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69029.176334 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68396.471903 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68396.471903 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67299.087750 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70030.020055 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68762.899758 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67299.087750 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70030.020055 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68762.899758 # average overall miss latency +system.cpu.l2cache.ReadReq_hits::total 744 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 659 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 659 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 613 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 191 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 804 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 613 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 191 # number of overall hits +system.cpu.l2cache.overall_hits::total 804 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3456 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 861 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4317 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 3130 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 3130 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3456 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3991 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7447 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3456 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3991 # number of overall misses +system.cpu.l2cache.overall_misses::total 7447 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 238916500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 66414500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 305331000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 225828500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 225828500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 238916500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 292243000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 531159500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 238916500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 292243000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 531159500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4069 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5061 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 659 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 659 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 3190 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 3190 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4069 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4182 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8251 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4069 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4182 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 8251 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.849349 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.867944 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.852993 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981191 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.981191 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.849349 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.954328 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.902557 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.849349 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.954328 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.902557 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69130.931713 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77136.469222 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70727.588603 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72149.680511 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72149.680511 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69130.931713 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73225.507392 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71325.298778 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69130.931713 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73225.507392 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71325.298778 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -751,162 +748,162 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3453 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 857 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4310 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3132 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3132 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3453 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3989 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7442 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3453 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3989 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7442 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 188417250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54498500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 242915750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 175604250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 175604250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 188417250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 230102750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 418520000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 188417250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 230102750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 418520000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.847570 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867409 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.851442 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.978750 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.978750 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.847570 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.952483 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.900750 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.847570 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.952483 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.900750 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54566.246742 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63592.182030 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56360.962877 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56067.768199 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56067.768199 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54566.246742 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57684.319378 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56237.570546 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54566.246742 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57684.319378 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56237.570546 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3456 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 861 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4317 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3130 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3130 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3456 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3991 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7447 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3456 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3991 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7447 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 195042500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55799500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 250842000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 187339500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 187339500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195042500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 243139000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 438181500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195042500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 243139000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 438181500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.849349 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867944 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.852993 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981191 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981191 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.849349 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.954328 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.902557 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.849349 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.954328 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.902557 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56435.908565 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64807.781649 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58105.628909 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59852.875399 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59852.875399 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56435.908565 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60921.824104 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58840.002686 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56435.908565 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60921.824104 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58840.002686 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 788 # number of replacements -system.cpu.dcache.tags.tagsinuse 3294.798817 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 160031202 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4188 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 38211.843840 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 780 # number of replacements +system.cpu.dcache.tags.tagsinuse 3295.992263 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 160011153 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4182 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 38261.873027 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3294.798817 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.804394 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.804394 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 86530434 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86530434 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73500763 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73500763 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 160031197 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 160031197 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 160031197 # number of overall hits -system.cpu.dcache.overall_hits::total 160031197 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1798 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1798 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19966 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19966 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21764 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21764 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21764 # number of overall misses -system.cpu.dcache.overall_misses::total 21764 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 114434250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 114434250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1039316587 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1039316587 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1153750837 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1153750837 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1153750837 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1153750837 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86532232 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86532232 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 3295.992263 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.804686 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.804686 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 86510267 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86510267 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73500882 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73500882 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 160011149 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 160011149 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 160011149 # number of overall hits +system.cpu.dcache.overall_hits::total 160011149 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1786 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1786 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19847 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19847 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21633 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21633 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21633 # number of overall misses +system.cpu.dcache.overall_misses::total 21633 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 114228250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 114228250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1085833087 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1085833087 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1200061337 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1200061337 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1200061337 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1200061337 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86512053 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86512053 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 160052961 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 160052961 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 160052961 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 160052961 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 160032782 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 160032782 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 160032782 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 160032782 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000272 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000272 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000136 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000136 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000136 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000136 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63645.300334 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63645.300334 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52054.321697 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 52054.321697 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53011.892897 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53011.892897 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53011.892897 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53011.892897 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 38531 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000270 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000270 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000135 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000135 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000135 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000135 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63957.586786 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63957.586786 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54710.187283 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54710.187283 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55473.643831 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55473.643831 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55473.643831 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55473.643831 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 40366 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 654 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 653 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 58.915902 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 61.816233 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 666 # number of writebacks -system.cpu.dcache.writebacks::total 666 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 810 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 810 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16766 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16766 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17576 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17576 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17576 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17576 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 988 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 988 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3200 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3200 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4188 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4188 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4188 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4188 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67480500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 67480500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 218199250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 218199250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 285679750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 285679750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 285679750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 285679750 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 659 # number of writebacks +system.cpu.dcache.writebacks::total 659 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 794 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 794 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16657 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16657 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17451 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17451 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17451 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17451 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 992 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 992 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3190 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3190 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4182 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4182 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4182 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4182 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 68767000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 68767000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 229720000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 229720000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298487000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 298487000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298487000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 298487000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68300.101215 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68300.101215 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68187.265625 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68187.265625 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68213.884909 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68213.884909 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68213.884909 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68213.884909 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69321.572581 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69321.572581 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72012.539185 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72012.539185 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71374.222860 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71374.222860 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71374.222860 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71374.222860 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 8bc1d638d..93aa60ef6 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,97 +1,99 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068375 # Number of seconds simulated -sim_ticks 68375005500 # Number of ticks simulated -final_tick 68375005500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.068515 # Number of seconds simulated +sim_ticks 68515366500 # Number of ticks simulated +final_tick 68515366500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 143200 # Simulator instruction rate (inst/s) -host_op_rate 183074 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35860683 # Simulator tick rate (ticks/s) -host_mem_usage 256516 # Number of bytes of host memory used -host_seconds 1906.68 # Real time elapsed on the host +host_inst_rate 128186 # Simulator instruction rate (inst/s) +host_op_rate 163879 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32166693 # Simulator tick rate (ticks/s) +host_mem_usage 283052 # Number of bytes of host memory used +host_seconds 2130.01 # Real time elapsed on the host sim_insts 273036725 # Number of instructions simulated sim_ops 349064449 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 194176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 194304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272128 # Number of bytes read from this memory system.physmem.bytes_read::total 466432 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 194176 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 194176 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3034 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4254 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 194304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 194304 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3036 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4252 # Number of read requests responded to by this memory system.physmem.num_reads::total 7288 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2839868 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3981806 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6821674 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2839868 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2839868 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2839868 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3981806 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6821674 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7288 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 7288 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 466432 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 466432 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 5 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 605 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 802 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 608 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 526 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 442 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 353 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 163 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 219 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 208 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 288 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 323 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 416 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 529 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 688 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 612 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 506 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 68374814000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7288 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4427 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2050 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 578 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 65 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 2835919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3971781 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6807699 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2835919 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2835919 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2835919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3971781 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6807699 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7289 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 7289 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 466496 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 466496 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 607 # Per bank write bursts +system.physmem.perBankRdBursts::1 801 # Per bank write bursts +system.physmem.perBankRdBursts::2 608 # Per bank write bursts +system.physmem.perBankRdBursts::3 526 # Per bank write bursts +system.physmem.perBankRdBursts::4 443 # Per bank write bursts +system.physmem.perBankRdBursts::5 353 # Per bank write bursts +system.physmem.perBankRdBursts::6 161 # Per bank write bursts +system.physmem.perBankRdBursts::7 217 # Per bank write bursts +system.physmem.perBankRdBursts::8 207 # Per bank write bursts +system.physmem.perBankRdBursts::9 294 # Per bank write bursts +system.physmem.perBankRdBursts::10 325 # Per bank write bursts +system.physmem.perBankRdBursts::11 416 # Per bank write bursts +system.physmem.perBankRdBursts::12 529 # Per bank write bursts +system.physmem.perBankRdBursts::13 687 # Per bank write bursts +system.physmem.perBankRdBursts::14 611 # Per bank write bursts +system.physmem.perBankRdBursts::15 504 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 68515346000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 7289 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 4373 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 569 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 177 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -150,119 +152,120 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 718 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 639.554318 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 239.565124 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1324.415379 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 223 31.06% 31.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 101 14.07% 45.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 63 8.77% 53.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 56 7.80% 61.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 31 4.32% 66.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 32 4.46% 70.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 16 2.23% 72.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 24 3.34% 76.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 9 1.25% 77.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 16 2.23% 79.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 9 1.25% 80.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 12 1.67% 82.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 5 0.70% 83.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 9 1.25% 84.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 7 0.97% 85.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 6 0.84% 86.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 4 0.56% 86.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 3 0.42% 87.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 5 0.70% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 4 0.56% 88.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 3 0.42% 88.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 3 0.42% 89.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 4 0.56% 89.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 5 0.70% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 4 0.56% 91.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 3 0.42% 91.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 2 0.28% 91.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 3 0.42% 92.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.14% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 2 0.28% 92.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 2 0.28% 92.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 3 0.42% 93.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 3 0.42% 93.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 2 0.28% 94.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.14% 94.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.14% 94.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.14% 94.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 1 0.14% 94.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.14% 94.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 2 0.28% 94.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 2 0.28% 95.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 1 0.14% 95.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 3 0.42% 95.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.14% 95.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.14% 96.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 1 0.14% 96.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.14% 96.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 1 0.14% 96.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.14% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.14% 96.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 1 0.14% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.14% 97.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 1 0.14% 97.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 2 0.28% 97.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 1 0.14% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 1 0.14% 97.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 1 0.14% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 1 0.14% 98.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 2 0.28% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 2 0.28% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 10 1.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 718 # Bytes accessed per row activation -system.physmem.totQLat 36604250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 168483000 # Sum of mem lat for all requests -system.physmem.totBusLat 36440000 # Total cycles spent in databus access -system.physmem.totBankLat 95438750 # Total cycles spent in bank access -system.physmem.avgQLat 5022.54 # Average queueing delay per request -system.physmem.avgBankLat 13095.33 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23117.86 # Average memory access latency -system.physmem.avgRdBW 6.82 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 6.82 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 1271 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 365.973249 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 166.155512 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 760.469459 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 520 40.91% 40.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 218 17.15% 58.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 133 10.46% 68.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 73 5.74% 74.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 41 3.23% 77.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 37 2.91% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 29 2.28% 82.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 36 2.83% 85.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 15 1.18% 86.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 25 1.97% 88.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 5 0.39% 89.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 14 1.10% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 4 0.31% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 8 0.63% 91.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 5 0.39% 91.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 8 0.63% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 8 0.63% 92.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 6 0.47% 93.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 5 0.39% 93.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 7 0.55% 94.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 2 0.16% 94.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 5 0.39% 94.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 5 0.39% 95.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 2 0.16% 95.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.24% 95.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 3 0.24% 95.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 3 0.24% 95.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 2 0.16% 96.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 2 0.16% 96.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 4 0.31% 96.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 4 0.31% 96.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 3 0.24% 97.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.08% 97.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 2 0.16% 97.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.08% 97.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 2 0.16% 97.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.08% 97.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.08% 97.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.08% 97.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 2 0.16% 98.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.08% 98.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 2 0.16% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 1 0.08% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 2 0.16% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.08% 98.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 2 0.16% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.08% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 2 0.16% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.08% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 1 0.08% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 3 0.24% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 1 0.08% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.08% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 1 0.08% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.08% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 1 0.08% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 2 0.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1271 # Bytes accessed per row activation +system.physmem.totQLat 60705750 # Total ticks spent queuing +system.physmem.totMemAccLat 196384500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36445000 # Total ticks spent in databus transfers +system.physmem.totBankLat 99233750 # Total ticks spent accessing banks +system.physmem.avgQLat 8328.41 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13614.18 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26942.58 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.81 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6570 # Number of row buffer hits during reads +system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 6018 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.15 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.56 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9381835.07 # Average gap between requests -system.membus.throughput 6821674 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4467 # Transaction distribution -system.membus.trans_dist::ReadResp 4467 # Transaction distribution -system.membus.trans_dist::UpgradeReq 5 # Transaction distribution -system.membus.trans_dist::UpgradeResp 5 # Transaction distribution -system.membus.trans_dist::ReadExReq 2821 # Transaction distribution -system.membus.trans_dist::ReadExResp 2821 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14586 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14586 # Packet count per connected master and slave (bytes) +system.physmem.avgGap 9399827.96 # Average gap between requests +system.physmem.pageHitRate 82.56 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.15 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 6807699 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4464 # Transaction distribution +system.membus.trans_dist::ReadResp 4463 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 2825 # Transaction distribution +system.membus.trans_dist::ReadExResp 2825 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14581 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14581 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466432 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 466432 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 466432 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8910500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8930000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 68010245 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 67824498 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.branchPred.lookups 35388733 # Number of BP lookups -system.cpu.branchPred.condPredicted 21200896 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1644934 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19122518 # Number of BTB lookups -system.cpu.branchPred.BTBHits 16795427 # Number of BTB hits +system.cpu.branchPred.lookups 35429100 # Number of BP lookups +system.cpu.branchPred.condPredicted 21225812 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1661684 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19625450 # Number of BTB lookups +system.cpu.branchPred.BTBHits 16825398 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.830625 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6785564 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 8441 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 85.732546 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6780528 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 8438 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -306,100 +309,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 136750012 # number of cpu cycles simulated +system.cpu.numCycles 137030734 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 38949353 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 317676023 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35388733 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23580991 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70834954 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6803690 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 21493719 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1383 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 54 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37560816 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 509146 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 136426737 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.984407 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.454366 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 39012994 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 318080298 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35429100 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23605926 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70957862 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6891670 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 21493708 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 111 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1614 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 61 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 37614130 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 516506 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 136684696 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.983709 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.454255 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66221739 48.54% 48.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6780898 4.97% 53.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5694782 4.17% 57.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6088849 4.46% 62.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4909575 3.60% 65.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4088004 3.00% 68.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3182942 2.33% 71.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4139594 3.03% 74.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35320354 25.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66359879 48.55% 48.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6789497 4.97% 53.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5708838 4.18% 57.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6107274 4.47% 62.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4922167 3.60% 65.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4085695 2.99% 68.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3186230 2.33% 71.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4137086 3.03% 74.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35388030 25.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 136426737 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258784 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.323042 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45449120 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16657240 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 66693516 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2548377 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5078484 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7335953 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 69077 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401163284 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 211870 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5078484 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50979253 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1928009 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 329001 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 63651330 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14460660 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 393604020 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 59 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1657735 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10191603 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1124 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 432142984 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2330358431 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1572902779 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 200313916 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 136684696 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258549 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.321233 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45532866 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16645865 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 66825856 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2530463 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5149646 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7344267 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69062 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401846627 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 213953 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5149646 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 51082336 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1907734 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 332489 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 63745566 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14466925 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 394259426 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 53 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1660076 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10182958 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1156 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 432806895 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2333828888 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1575589736 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 200458039 # Number of floating rename lookups system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 47576791 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11831 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11830 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 36438205 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 103461367 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 91301104 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4273842 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5281559 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 384115412 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 48240702 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11816 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11815 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 36507596 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 103616420 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 91395607 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4296163 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5310753 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 384620101 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 22788 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 373986631 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1200950 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 34324808 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 86133615 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 374263749 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1212133 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 34826495 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 87778881 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 668 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 136426737 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.741300 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.023490 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 136684696 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.738154 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.024883 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24929928 18.27% 18.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19932793 14.61% 32.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20578448 15.08% 47.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18152288 13.31% 61.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24038629 17.62% 78.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15699021 11.51% 90.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8799073 6.45% 96.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3376437 2.47% 99.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 920120 0.67% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 25139035 18.39% 18.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19926957 14.58% 32.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20565636 15.05% 48.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18170176 13.29% 61.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 24039516 17.59% 78.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15735356 11.51% 90.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8814568 6.45% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3374876 2.47% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 918576 0.67% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 136426737 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 136684696 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8934 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4692 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8700 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4687 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -418,127 +421,127 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 46301 0.26% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 46352 0.26% 0.34% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7704 0.04% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 463 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7624 0.04% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 437 0.00% 0.38% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 190616 1.07% 1.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 3949 0.02% 1.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 241166 1.36% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9286471 52.35% 55.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7950501 44.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 190912 1.08% 1.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 4399 0.02% 1.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241386 1.36% 2.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9273710 52.31% 55.15% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7950548 44.85% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 126356667 33.79% 33.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2175742 0.58% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 2 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6779199 1.81% 36.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8471128 2.27% 38.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3427474 0.92% 39.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1595849 0.43% 39.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20859409 5.58% 45.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7172834 1.92% 47.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7127502 1.91% 49.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 126477598 33.79% 33.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2175809 0.58% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 3 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6782032 1.81% 36.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8476848 2.26% 38.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3430270 0.92% 39.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1595622 0.43% 39.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20869694 5.58% 45.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7174273 1.92% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7130259 1.91% 49.19% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101548323 27.15% 76.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88297215 23.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101673859 27.17% 76.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88302195 23.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 373986631 # Type of FU issued -system.cpu.iq.rate 2.734820 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17740799 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047437 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 653979183 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 288208067 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 249975124 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 249362565 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 130269118 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118046236 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 263130568 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 128596862 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11091317 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 374263749 # Type of FU issued +system.cpu.iq.rate 2.731239 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17728757 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047370 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654715892 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 289089659 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 250133425 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249437192 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 130393861 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118075733 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 263363212 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128629294 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11082647 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 8812619 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 109039 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14268 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8925521 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8967672 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 108753 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14263 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9020024 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 177200 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1779 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 174668 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1902 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5078484 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 284505 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 35417 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 384139745 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 871852 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 103461367 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 91301104 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 5149646 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 272927 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 35696 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 384644450 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 871710 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 103616420 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 91395607 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 11754 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 311 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 371 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14268 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1284870 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 366093 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1650963 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 370046005 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100262370 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3940626 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 342 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 365 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14263 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1301323 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 370771 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1672094 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 370296137 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100380791 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3967612 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1545 # number of nop insts executed -system.cpu.iew.exec_refs 187486507 # number of memory reference insts executed -system.cpu.iew.exec_branches 32007235 # Number of branches executed -system.cpu.iew.exec_stores 87224137 # Number of stores executed -system.cpu.iew.exec_rate 2.706003 # Inst execution rate -system.cpu.iew.wb_sent 368676629 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 368021360 # cumulative count of insts written-back -system.cpu.iew.wb_producers 182960102 # num instructions producing a value -system.cpu.iew.wb_consumers 363631500 # num instructions consuming a value +system.cpu.iew.exec_nop 1561 # number of nop insts executed +system.cpu.iew.exec_refs 187597519 # number of memory reference insts executed +system.cpu.iew.exec_branches 32011770 # Number of branches executed +system.cpu.iew.exec_stores 87216728 # Number of stores executed +system.cpu.iew.exec_rate 2.702285 # Inst execution rate +system.cpu.iew.wb_sent 368879898 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 368209158 # cumulative count of insts written-back +system.cpu.iew.wb_producers 183085663 # num instructions producing a value +system.cpu.iew.wb_consumers 363859128 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.691198 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.503147 # average fanout of values written-back +system.cpu.iew.wb_rate 2.687055 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.503177 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 35074746 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 35579507 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1576251 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 131348253 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.657554 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.659541 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1592984 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 131535050 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.653780 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.659242 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 34568937 26.32% 26.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 28443468 21.66% 47.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13309150 10.13% 58.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11454276 8.72% 66.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13766870 10.48% 77.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7405227 5.64% 82.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3876233 2.95% 85.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3903284 2.97% 88.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14620808 11.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34731076 26.40% 26.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 28455457 21.63% 48.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13342482 10.14% 58.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11433888 8.69% 66.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13770355 10.47% 77.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7412668 5.64% 82.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3873056 2.94% 85.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3888664 2.96% 88.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14627404 11.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 131348253 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 131535050 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037337 # Number of instructions committed system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -549,220 +552,220 @@ system.cpu.commit.branches 30563497 # Nu system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14620808 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14627404 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 500864729 # The number of ROB reads -system.cpu.rob.rob_writes 773362160 # The number of ROB writes -system.cpu.timesIdled 6666 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 323275 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 501549691 # The number of ROB reads +system.cpu.rob.rob_writes 774443009 # The number of ROB writes +system.cpu.timesIdled 6642 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 346038 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273036725 # Number of Instructions Simulated system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated -system.cpu.cpi 0.500848 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.500848 # CPI: Total CPI of All Threads -system.cpu.ipc 1.996612 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.996612 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1768925077 # number of integer regfile reads -system.cpu.int_regfile_writes 232843327 # number of integer regfile writes -system.cpu.fp_regfile_reads 188113453 # number of floating regfile reads -system.cpu.fp_regfile_writes 132483580 # number of floating regfile writes -system.cpu.misc_regfile_reads 566770577 # number of misc regfile reads +system.cpu.cpi 0.501877 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.501877 # CPI: Total CPI of All Threads +system.cpu.ipc 1.992522 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.992522 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1770065591 # number of integer regfile reads +system.cpu.int_regfile_writes 233053939 # number of integer regfile writes +system.cpu.fp_regfile_reads 188169392 # number of floating regfile reads +system.cpu.fp_regfile_writes 132536105 # number of floating regfile writes +system.cpu.misc_regfile_reads 566956802 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.toL2Bus.throughput 20110273 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 17610 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 17610 # Transaction distribution +system.cpu.toL2Bus.throughput 20102702 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 17643 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 17642 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1037 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2838 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2838 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31674 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10263 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 41937 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1013376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2842 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2842 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31749 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10257 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 42006 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1015808 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 1374656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 1374656 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 384 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 11782000 # Layer occupancy (ticks) +system.cpu.toL2Bus.tot_pkt_size::total 1377088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 1377088 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 11799000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24379238 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24347988 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7509966 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7401462 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 13946 # number of replacements -system.cpu.icache.tags.tagsinuse 1848.498389 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 37543488 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15836 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 2370.768376 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 13986 # number of replacements +system.cpu.icache.tags.tagsinuse 1848.638823 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 37596770 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15875 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2368.300472 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1848.498389 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.902587 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.902587 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 37543488 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37543488 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37543488 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37543488 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37543488 # number of overall hits -system.cpu.icache.overall_hits::total 37543488 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17326 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17326 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17326 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17326 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17326 # number of overall misses -system.cpu.icache.overall_misses::total 17326 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 439962484 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 439962484 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 439962484 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 439962484 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 439962484 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 439962484 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37560814 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37560814 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37560814 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37560814 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37560814 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37560814 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1848.638823 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.902656 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.902656 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37596770 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37596770 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37596770 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37596770 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37596770 # number of overall hits +system.cpu.icache.overall_hits::total 37596770 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17358 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17358 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17358 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17358 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17358 # number of overall misses +system.cpu.icache.overall_misses::total 17358 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 450239984 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 450239984 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 450239984 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 450239984 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 450239984 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 450239984 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37614128 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37614128 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37614128 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37614128 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37614128 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37614128 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000461 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000461 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000461 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000461 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000461 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000461 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25393.194275 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25393.194275 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25393.194275 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25393.194275 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25393.194275 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25393.194275 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 913 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25938.471252 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25938.471252 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25938.471252 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25938.471252 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25938.471252 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25938.471252 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2006 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 41.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 87.217391 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1486 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1486 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1486 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1486 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1486 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1486 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15840 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15840 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15840 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15840 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15840 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15840 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 349391259 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 349391259 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 349391259 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 349391259 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 349391259 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 349391259 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1481 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1481 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1481 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1481 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1481 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1481 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15877 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15877 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15877 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15877 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15877 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15877 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 359424009 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 359424009 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 359424009 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 359424009 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 359424009 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 359424009 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000422 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000422 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000422 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22057.528977 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22057.528977 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22057.528977 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22057.528977 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22057.528977 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22057.528977 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22638.030421 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22638.030421 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22638.030421 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22638.030421 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22638.030421 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22638.030421 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3937.726706 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 13182 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5389 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.446094 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3939.771440 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 13217 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5387 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.453499 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 375.051576 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2781.709770 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 780.965360 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011446 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084891 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.023833 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.120170 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 12788 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 298 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13086 # number of ReadReq hits +system.cpu.l2cache.tags.occ_blocks::writebacks 378.229398 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2786.621740 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 774.920301 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011543 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.085041 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.023649 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.120232 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 12824 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 299 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 13123 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 1037 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 1037 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 17 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 17 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12788 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 315 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13103 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12788 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 315 # number of overall hits -system.cpu.l2cache.overall_hits::total 13103 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3046 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1472 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4518 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 2821 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2821 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3046 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 4293 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7339 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3046 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 4293 # number of overall misses -system.cpu.l2cache.overall_misses::total 7339 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 205637750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 101578250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 307216000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 188534250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 188534250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 205637750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 290112500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 495750250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 205637750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 290112500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 495750250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 15834 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1770 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 17604 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_hits::cpu.inst 12824 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 316 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13140 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 12824 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 316 # number of overall hits +system.cpu.l2cache.overall_hits::total 13140 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3049 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1467 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4516 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 2825 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2825 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3049 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 4292 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7341 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3049 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 4292 # number of overall misses +system.cpu.l2cache.overall_misses::total 7341 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 215269250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 108631000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 323900250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 199625500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 199625500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 215269250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 308256500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 523525750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 215269250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 308256500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 523525750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 15873 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1766 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 17639 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 1037 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 1037 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2838 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2838 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 15834 # number of demand (read+write) accesses +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2842 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2842 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 15873 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4608 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 20442 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 15834 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 20481 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 15873 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4608 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 20442 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192371 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.831638 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.256646 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 20481 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192087 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.830691 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.256024 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994010 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.994010 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192371 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.931641 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.359016 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192371 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.931641 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.359016 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67510.751806 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69006.963315 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67998.229305 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66832.417582 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66832.417582 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67510.751806 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67578.034009 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67550.109007 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67510.751806 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67578.034009 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67550.109007 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994018 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.994018 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192087 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.931424 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.358430 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192087 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.931424 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.358430 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70603.230567 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74049.761418 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71722.818866 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70663.893805 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70663.893805 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70603.230567 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71821.178938 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71315.318077 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70603.230567 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71821.178938 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71315.318077 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -772,176 +775,176 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 39 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 39 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 51 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 40 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 39 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 51 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3034 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1433 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4467 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2821 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 2821 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3034 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 4254 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7288 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3034 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 4254 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7288 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 166700500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 81208500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 247909000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 51005 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 51005 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 153520750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 153520750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 166700500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 234729250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 401429750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 166700500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 234729250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 401429750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191613 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.809605 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253749 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_hits::cpu.data 40 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 52 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3037 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1427 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4464 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2825 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 2825 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3037 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4252 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7289 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3037 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 4252 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7289 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 176465000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 88132000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 264597000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 164645000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 164645000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176465000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 252777000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 429242000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176465000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 252777000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 429242000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191331 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.808041 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253076 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994010 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994010 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191613 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923177 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.356521 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191613 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923177 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.356521 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54944.133158 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56670.272156 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55497.873293 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10201 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10201 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54420.684155 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54420.684155 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54944.133158 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55178.479079 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55080.920692 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54944.133158 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55178.479079 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55080.920692 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994018 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994018 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191331 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922743 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.355891 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191331 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922743 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.355891 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58105.037866 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61760.336370 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59273.521505 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58281.415929 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58281.415929 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58105.037866 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59448.965193 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58889.010838 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58105.037866 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59448.965193 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58889.010838 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 1414 # number of replacements -system.cpu.dcache.tags.tagsinuse 3101.863625 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 170862922 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3101.535581 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 170993874 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4608 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37079.627170 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37108.045573 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3101.863625 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.757291 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.757291 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88809743 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88809743 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82031242 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82031242 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11022 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11022 # number of LoadLockedReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 3101.535581 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.757211 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.757211 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 88940583 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88940583 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82031381 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82031381 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11003 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11003 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 170840985 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 170840985 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 170840985 # number of overall hits -system.cpu.dcache.overall_hits::total 170840985 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3962 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3962 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 21423 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 21423 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 170971964 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 170971964 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 170971964 # number of overall hits +system.cpu.dcache.overall_hits::total 170971964 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3947 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3947 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 21284 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 21284 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25385 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25385 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25385 # number of overall misses -system.cpu.dcache.overall_misses::total 25385 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 221925207 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 221925207 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1196433403 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1196433403 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 157000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 157000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1418358610 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1418358610 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1418358610 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1418358610 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88813705 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88813705 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 25231 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25231 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25231 # number of overall misses +system.cpu.dcache.overall_misses::total 25231 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 233964205 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 233964205 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1259611139 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1259611139 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 170250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1493575344 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1493575344 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1493575344 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1493575344 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88944530 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88944530 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11024 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11024 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11005 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11005 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 170866370 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 170866370 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 170866370 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 170866370 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000261 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000261 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000181 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000181 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000149 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000149 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000149 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000149 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56013.429329 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56013.429329 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55848.079307 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55848.079307 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 78500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55873.886547 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55873.886547 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55873.886547 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55873.886547 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 25209 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1225 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 407 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 170997195 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 170997195 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 170997195 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 170997195 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000044 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000259 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000259 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000182 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000182 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000148 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000148 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000148 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000148 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59276.464403 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59276.464403 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59181.128500 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59181.128500 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59196.042329 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59196.042329 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59196.042329 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59196.042329 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 28298 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1224 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 410 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 61.938575 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 102.083333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.019512 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 102 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1037 # number of writebacks system.cpu.dcache.writebacks::total 1037 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2191 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2191 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18581 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18581 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2179 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2179 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18442 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18442 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20772 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20772 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20772 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20772 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1771 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1771 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 20621 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20621 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20621 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20621 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1768 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1768 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2842 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 2842 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4613 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4613 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4613 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4613 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 106433039 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 106433039 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 191658495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 191658495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298091534 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 298091534 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298091534 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 298091534 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 4610 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4610 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4610 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4610 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 113556540 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 113556540 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 202620998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 202620998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 316177538 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 316177538 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 316177538 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 316177538 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -950,14 +953,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60097.706945 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60097.706945 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67437.894089 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67437.894089 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64619.885974 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 64619.885974 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64619.885974 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 64619.885974 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64228.812217 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64228.812217 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71295.213934 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71295.213934 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68585.149241 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68585.149241 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68585.149241 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68585.149241 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |