diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-03-17 10:30:58 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-03-17 10:30:58 -0700 |
| commit | 4fc69db8f89049a881a5f4aa68545840818b124c (patch) | |
| tree | 7388f5b2755f6f4937b7ce9b8ba889f0d48bc403 /tests/long/se/30.eon/ref | |
| parent | dbad391a9b4e861fd3d660069ed448db85144e17 (diff) | |
| download | gem5-4fc69db8f89049a881a5f4aa68545840818b124c.tar.xz | |
stats: update stats for mmap changes
Diffstat (limited to 'tests/long/se/30.eon/ref')
4 files changed, 377 insertions, 362 deletions
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini index 892e458ed..2a5bb3732 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -24,6 +25,7 @@ mem_mode=timing mem_ranges= memories=system.physmem mmap_using_noreserve=false +multi_thread=false num_work_ids=16 readfile= symbolfile= @@ -85,9 +87,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -101,6 +103,7 @@ system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -161,9 +164,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 @@ -177,6 +180,7 @@ system=system tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=true cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -196,6 +200,7 @@ eventq_index=0 [system.cpu.isa] type=ArmISA +decoderFlavour=Generic eventq_index=0 fpsid=1090793632 id_aa64afr0_el1=0 @@ -271,9 +276,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -287,6 +292,7 @@ system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] @@ -302,12 +308,14 @@ size=2097152 [system.cpu.toL2Bus] type=CoherentXBar +children=snoop_filter clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 -snoop_filter=Null +snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false @@ -315,6 +323,13 @@ width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + [system.cpu.tracer] type=ExeTracer eventq_index=0 @@ -329,7 +344,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon +executable=/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin kvmInSE=false @@ -364,6 +379,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr index a25196116..7e050de51 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr @@ -1,4 +1,3 @@ -warn: Sockets disabled, not accepting gdb connections getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout index d5cd58d2c..7ed803ee9 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 14 2015 23:29:19 -gem5 started Sep 15 2015 03:56:42 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing +gem5 compiled Mar 16 2016 15:51:04 +gem5 started Mar 16 2016 17:19:39 +gem5 executing on dinar2c11, pid 17050 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -16,4 +16,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.510000 -Exiting @ tick 517235407500 because target called exit() +Exiting @ tick 517287152500 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 42b8a5c86..7d459034e 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.517291 # Number of seconds simulated -sim_ticks 517291025500 # Number of ticks simulated -final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.517287 # Number of seconds simulated +sim_ticks 517287152500 # Number of ticks simulated +final_tick 517287152500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 634406 # Simulator instruction rate (inst/s) -host_op_rate 761628 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1203245454 # Simulator tick rate (ticks/s) -host_mem_usage 324572 # Number of bytes of host memory used -host_seconds 429.91 # Real time elapsed on the host -sim_insts 272739286 # Number of instructions simulated -sim_ops 327433744 # Number of ops (including micro ops) simulated +host_inst_rate 131506 # Simulator instruction rate (inst/s) +host_op_rate 157879 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 249419657 # Simulator tick rate (ticks/s) +host_mem_usage 307088 # Number of bytes of host memory used +host_seconds 2073.96 # Real time elapsed on the host +sim_insts 272737951 # Number of instructions simulated +sim_ops 327435116 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory -system.physmem.bytes_read::total 437248 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 166912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 166912 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 322666 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 522599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 845265 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 322666 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 322666 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 269696 # Number of bytes read from this memory +system.physmem.bytes_read::total 436672 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 166976 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4214 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6823 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 322792 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 521366 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 844158 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 322792 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 322792 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 322792 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 521366 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 844158 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -147,33 +147,33 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 1034582051 # number of cpu cycles simulated +system.cpu.numCycles 1034574305 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 272739286 # Number of instructions committed -system.cpu.committedOps 327433744 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses +system.cpu.committedInsts 272737951 # Number of instructions committed +system.cpu.committedOps 327435116 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 258332236 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses -system.cpu.num_func_calls 12448615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls -system.cpu.num_int_insts 258331537 # number of integer instructions +system.cpu.num_func_calls 12449970 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15800021 # number of instructions that are conditional controls +system.cpu.num_int_insts 258332236 # number of integer instructions system.cpu.num_fp_insts 114216705 # number of float instructions -system.cpu.num_int_register_reads 1215888421 # number of times the integer registers were read -system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written +system.cpu.num_int_register_reads 1215886434 # number of times the integer registers were read +system.cpu.num_int_register_writes 162499715 # number of times the integer registers were written system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written -system.cpu.num_cc_register_reads 1242915503 # number of times the CC registers were read -system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written -system.cpu.num_mem_refs 168107847 # number of memory refs -system.cpu.num_load_insts 85732248 # Number of load instructions -system.cpu.num_store_insts 82375599 # Number of store instructions +system.cpu.num_cc_register_reads 1242911540 # number of times the CC registers were read +system.cpu.num_cc_register_writes 76355719 # number of times the CC registers were written +system.cpu.num_mem_refs 168105830 # number of memory refs +system.cpu.num_load_insts 85730232 # Number of load instructions +system.cpu.num_store_insts 82375598 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1034582050.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1034574304.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 30563503 # Number of branches fetched +system.cpu.Branches 30566209 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 104312544 31.82% 31.82% # Class of executed instruction +system.cpu.op_class::IntAlu 104315933 31.82% 31.82% # Class of executed instruction system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction @@ -198,79 +198,79 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Cl system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 19652356 5.99% 44.33% # Class of executed instruction system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.67% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction -system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction -system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 85730232 26.15% 74.87% # Class of executed instruction +system.cpu.op_class::MemWrite 82375598 25.13% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 327812214 # Class of executed instruction -system.cpu.dcache.tags.replacements 1332 # number of replacements -system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. +system.cpu.op_class::total 327813586 # Class of executed instruction +system.cpu.dcache.tags.replacements 1326 # number of replacements +system.cpu.dcache.tags.tagsinuse 3078.339297 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168357609 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4469 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37672.322443 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3078.335714 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.751547 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.751547 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 3078.339297 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.751548 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.751548 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3143 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits +system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 678 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2434 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.767334 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 336728627 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336728627 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86231946 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86231946 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82049814 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82049814 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits -system.cpu.dcache.overall_hits::total 168337827 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 168281760 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168281760 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168335819 # number of overall hits +system.cpu.dcache.overall_hits::total 168335819 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1605 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1605 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2862 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2862 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses -system.cpu.dcache.overall_misses::total 4479 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88052000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88052000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 177422500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 177422500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 265474500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 265474500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 265474500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 265474500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 4467 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4467 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4470 # number of overall misses +system.cpu.dcache.overall_misses::total 4470 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88066000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88066000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 176802500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 176802500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 264868500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 264868500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 264868500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 264868500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86233551 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86233551 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 82052676 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 82052676 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168286227 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168286227 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168340289 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168340289 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses @@ -281,14 +281,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54895.261845 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54895.261845 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61776.636490 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61776.636490 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59310.656836 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59310.656836 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59270.931011 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59270.931011 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54869.781931 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54869.781931 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61775.856045 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61775.856045 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59294.492948 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59294.492948 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59254.697987 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59254.697987 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -297,34 +297,34 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 998 # number of writebacks -system.cpu.dcache.writebacks::total 998 # number of writebacks +system.cpu.dcache.writebacks::writebacks 997 # number of writebacks +system.cpu.dcache.writebacks::total 997 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1604 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1604 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2862 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2862 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86402000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 86402000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 174550500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 174550500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 4466 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4466 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4469 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4469 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86415000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 86415000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 173940500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 173940500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 183000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 183000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260952500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 260952500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 261135500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 261135500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260355500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 260355500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260538500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 260538500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -335,71 +335,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53900.187149 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53900.187149 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53874.688279 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53874.688279 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60775.856045 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60775.856045 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58297.245858 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 58297.245858 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58299.060192 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 58299.060192 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 13796 # number of replacements -system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 13798 # number of replacements +system.cpu.icache.tags.tagsinuse 1765.947853 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 348643415 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15605 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22341.776033 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1765.947853 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 163 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1522 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses -system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 348644750 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 348644750 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 348644750 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 348644750 # number of overall hits -system.cpu.icache.overall_hits::total 348644750 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses -system.cpu.icache.overall_misses::total 15603 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 338446000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 338446000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 338446000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 338446000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 338446000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 338446000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 348660353 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 348660353 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 348660353 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 697333645 # Number of tag accesses +system.cpu.icache.tags.data_accesses 697333645 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 348643415 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 348643415 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 348643415 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 348643415 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 348643415 # number of overall hits +system.cpu.icache.overall_hits::total 348643415 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 15605 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 15605 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 15605 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 15605 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 15605 # number of overall misses +system.cpu.icache.overall_misses::total 15605 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 338522000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 338522000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 338522000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 338522000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 338522000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 338522000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 348659020 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 348659020 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 348659020 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 348659020 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 348659020 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 348659020 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21691.085048 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21691.085048 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21691.085048 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21691.085048 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21693.175264 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21693.175264 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21693.175264 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21693.175264 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21693.175264 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21693.175264 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -408,42 +408,42 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 13796 # number of writebacks -system.cpu.icache.writebacks::total 13796 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322843000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 322843000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322843000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 322843000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322843000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 322843000 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 13798 # number of writebacks +system.cpu.icache.writebacks::total 13798 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15605 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15605 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15605 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15605 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15605 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15605 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322917000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 322917000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322917000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 322917000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322917000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 322917000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20693.175264 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20693.175264 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20693.175264 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20693.175264 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20693.175264 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20693.175264 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3487.616981 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 341.605293 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 738.688437 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 341.600605 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.332701 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 738.683674 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073466 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.022543 # Average percentage of cache occupancy @@ -451,92 +451,92 @@ system.cpu.l2cache.tags.occ_percent::total 0.106434 # system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1233 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 6212 # number of WritebackClean hits +system.cpu.l2cache.tags.tag_accesses 228016 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 228016 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 997 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 997 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 6213 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 6213 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12995 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 12995 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 238 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 238 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12995 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 254 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13249 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12995 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 254 # number of overall hits -system.cpu.l2cache.overall_hits::total 13249 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2608 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2608 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12996 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 12996 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 239 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 239 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 12996 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 255 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13251 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 12996 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 255 # number of overall hits +system.cpu.l2cache.overall_hits::total 13251 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 2846 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2846 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2609 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2609 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1368 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 1368 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2608 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 4224 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2608 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 4224 # number of overall misses -system.cpu.l2cache.overall_misses::total 6832 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 170070500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 170070500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155292000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 155292000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.demand_misses::cpu.inst 2609 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 4214 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 6823 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2609 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 4214 # number of overall misses +system.cpu.l2cache.overall_misses::total 6823 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 169475500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 169475500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155351500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 155351500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 81591000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 81591000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 155292000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 251661500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 406953500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 155292000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 251661500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 406953500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 998 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 998 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 6212 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 6212 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15603 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 15603 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1606 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1606 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167147 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167147 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.851806 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.851806 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167147 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.943278 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167147 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.943278 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.494398 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.494398 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.478528 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.478528 # average ReadCleanReq miss latency +system.cpu.l2cache.demand_miss_latency::cpu.inst 155351500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 251066500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 406418000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 155351500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 251066500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 406418000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 997 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 997 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 6213 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 6213 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2862 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2862 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15605 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 15605 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1607 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1607 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 15605 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4469 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 20074 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 15605 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4469 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 20074 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994410 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.994410 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167190 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167190 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.851276 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.851276 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167190 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.942940 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.339892 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167190 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.942940 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.339892 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.664793 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.664793 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.461479 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.461479 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59642.543860 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59642.543860 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59565.793326 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59565.793326 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.461479 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59579.140959 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59565.880111 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.461479 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59579.140959 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59565.880111 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -545,115 +545,115 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2608 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2608 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2846 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 2846 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2609 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2609 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1368 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1368 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2608 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 4224 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2608 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 4224 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141510500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141510500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129212000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129212000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2609 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4214 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 6823 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 4214 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 6823 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141015500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141015500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129261500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129261500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 67911000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 67911000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129212000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 209421500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 338633500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129212000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 209421500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 338633500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167147 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851806 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851806 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.494398 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.494398 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.478528 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.478528 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129261500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 208926500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 338188000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129261500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 208926500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 338188000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994410 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994410 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167190 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167190 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851276 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851276 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167190 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942940 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.339892 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167190 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942940 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.339892 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.664793 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.664793 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.461479 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.461479 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.461479 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49579.140959 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.880111 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.461479 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49579.140959 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.880111 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 35198 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 15220 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7664 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 334 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45002 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10288 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 55290 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2232000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadResp 17212 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 997 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13798 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 329 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2862 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2862 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15605 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1607 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45008 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10264 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 55272 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 349824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2231616 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 20081 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.386335 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.486921 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 20074 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.386570 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.486976 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 12323 61.37% 61.37% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 7758 38.63% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 12314 61.34% 61.34% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 7760 38.66% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 20081 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 32398500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 20074 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 32394000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 23407500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6703500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3976 # Transaction distribution -system.membus.trans_dist::ReadExReq 2856 # Transaction distribution -system.membus.trans_dist::ReadExResp 2856 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3976 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 3977 # Transaction distribution +system.membus.trans_dist::ReadExReq 2846 # Transaction distribution +system.membus.trans_dist::ReadExResp 2846 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3977 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13646 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13646 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 436672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 436672 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 6833 # Request fanout histogram +system.membus.snoop_fanout::samples 6824 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 6824 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6833 # Request fanout histogram -system.membus.reqLayer0.occupancy 7281500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 6824 # Request fanout histogram +system.membus.reqLayer0.occupancy 7272500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 34160000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 34115000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |