diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
| commit | fda338f8d3ba6f6cb271e2c10cb880ff064edb61 (patch) | |
| tree | 20a91f6acacb2cb40967ce56a539d8444b744b9e /tests/long/se/30.eon/ref | |
| parent | b265d9925c123f0df50db98cf56dab6a3596b54b (diff) | |
| download | gem5-fda338f8d3ba6f6cb271e2c10cb880ff064edb61.tar.xz | |
Stats: Updates due to bus changes
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
Diffstat (limited to 'tests/long/se/30.eon/ref')
15 files changed, 1513 insertions, 1517 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini index fd38a6ce1..d73c26c02 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini @@ -181,7 +181,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -213,7 +213,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout index 8d1e02107..f78d992b7 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:10:46 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:12:34 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second @@ -11,4 +11,4 @@ info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.133333 -Exiting @ tick 141174877500 because target called exit() +Exiting @ tick 141187061500 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index 63af08cbf..c000798eb 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.141175 # Number of seconds simulated -sim_ticks 141174877500 # Number of ticks simulated -final_tick 141174877500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.141187 # Number of seconds simulated +sim_ticks 141187061500 # Number of ticks simulated +final_tick 141187061500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165783 # Simulator instruction rate (inst/s) -host_op_rate 165783 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58706881 # Simulator tick rate (ticks/s) -host_mem_usage 225068 # Number of bytes of host memory used -host_seconds 2404.74 # Real time elapsed on the host +host_inst_rate 158597 # Simulator instruction rate (inst/s) +host_op_rate 158597 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56167220 # Simulator tick rate (ticks/s) +host_mem_usage 225028 # Number of bytes of host memory used +host_seconds 2513.69 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 214592 # Number of bytes read from this memory @@ -19,34 +19,34 @@ system.physmem.bytes_inst_read::total 214592 # Nu system.physmem.num_reads::cpu.inst 3353 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7322 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1520044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1799300 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3319344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1520044 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1520044 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1520044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1799300 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3319344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1519913 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1799145 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3319058 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1519913 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1519913 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1519913 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1799145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3319058 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 94755013 # DTB read hits +system.cpu.dtb.read_hits 94755019 # DTB read hits system.cpu.dtb.read_misses 21 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 94755034 # DTB read accesses -system.cpu.dtb.write_hits 73522045 # DTB write hits +system.cpu.dtb.read_accesses 94755040 # DTB read accesses +system.cpu.dtb.write_hits 73522100 # DTB write hits system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73522080 # DTB write accesses -system.cpu.dtb.data_hits 168277058 # DTB hits +system.cpu.dtb.write_accesses 73522135 # DTB write accesses +system.cpu.dtb.data_hits 168277119 # DTB hits system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168277114 # DTB accesses -system.cpu.itb.fetch_hits 49111850 # ITB hits -system.cpu.itb.fetch_misses 88782 # ITB misses +system.cpu.dtb.data_accesses 168277175 # DTB accesses +system.cpu.itb.fetch_hits 49112134 # ITB hits +system.cpu.itb.fetch_misses 88783 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 49200632 # ITB accesses +system.cpu.itb.fetch_accesses 49200917 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,42 +60,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 282349756 # number of cpu cycles simulated +system.cpu.numCycles 282374124 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 53870351 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 30921654 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 16037209 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 33426940 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 15653987 # Number of BTB hits +system.cpu.branch_predictor.lookups 53870034 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 30921446 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 16037248 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 33426490 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 15653868 # Number of BTB hits system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 18 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 46.830452 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 29683846 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 24186505 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 280818442 # Number of Reads from Int. Register File +system.cpu.branch_predictor.RASInCorrect 19 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 46.830726 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 29683710 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 24186324 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 280818505 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 440154301 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 119907697 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 440154364 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 119907678 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 220104178 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100457644 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 168700458 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 14475221 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 1561329 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 16036550 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 28551001 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 35.966429 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 205750873 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 2124330 # Number of Multipy Operations Executed +system.cpu.regfile_manager.floatRegFileAccesses 220104159 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 100457715 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 168700471 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 14475138 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 1561451 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 16036589 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 28550962 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 35.966517 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 205751085 # Number of Instructions Executed. +system.cpu.mult_div_unit.multiplies 2124334 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 281921224 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 281932231 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 6799 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13475470 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 268874286 # Number of cycles cpu stages are processed. -system.cpu.activity 95.227384 # Percentage of cycles cpu is active +system.cpu.timesIdled 9236 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13499283 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 268874841 # Number of cycles cpu stages are processed. +system.cpu.activity 95.219363 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -107,72 +107,72 @@ system.cpu.committedInsts 398664595 # Nu system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) -system.cpu.cpi 0.708239 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.708300 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.708239 # CPI: Total CPI of All Threads -system.cpu.ipc 1.411953 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.708300 # CPI: Total CPI of All Threads +system.cpu.ipc 1.411831 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.411953 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 78535818 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 203813938 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 72.184917 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 108863135 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 173486621 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.443871 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 104640369 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 177709387 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.939451 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 183568295 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 98781461 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 34.985495 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 92657161 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 189692595 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.183552 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 1974 # number of replacements -system.cpu.icache.tagsinuse 1829.918683 # Cycle average of tags in use -system.cpu.icache.total_refs 49107469 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3901 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12588.430915 # Average number of references to valid blocks. +system.cpu.ipc_total 1.411831 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 78560366 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 203813758 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 72.178624 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 108887705 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 173486419 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 61.438497 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 104664774 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 177709350 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 62.934007 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 183592728 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 98781396 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 34.982453 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 92681683 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 189692441 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 67.177700 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 1973 # number of replacements +system.cpu.icache.tagsinuse 1829.856986 # Cycle average of tags in use +system.cpu.icache.total_refs 49107743 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 3900 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12591.728974 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1829.918683 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.893515 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.893515 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 49107469 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 49107469 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 49107469 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 49107469 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 49107469 # number of overall hits -system.cpu.icache.overall_hits::total 49107469 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4380 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4380 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4380 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4380 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4380 # number of overall misses -system.cpu.icache.overall_misses::total 4380 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 214309000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 214309000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 214309000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 214309000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 214309000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 214309000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 49111849 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 49111849 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 49111849 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 49111849 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 49111849 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 49111849 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1829.856986 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.893485 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.893485 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 49107743 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 49107743 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 49107743 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 49107743 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 49107743 # number of overall hits +system.cpu.icache.overall_hits::total 49107743 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4390 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4390 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4390 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4390 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4390 # number of overall misses +system.cpu.icache.overall_misses::total 4390 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 220305000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 220305000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 220305000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 220305000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 220305000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 220305000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 49112133 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 49112133 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 49112133 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 49112133 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 49112133 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 49112133 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000089 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000089 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000089 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000089 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000089 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000089 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48928.995434 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48928.995434 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48928.995434 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48928.995434 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48928.995434 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48928.995434 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50183.371298 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 50183.371298 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 50183.371298 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 50183.371298 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 50183.371298 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 50183.371298 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 45000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -181,70 +181,70 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets 45000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 479 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 479 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 479 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 479 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 479 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 479 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3901 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 3901 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 3901 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 3901 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 3901 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 3901 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 185222000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 185222000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 185222000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 185222000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 185222000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 185222000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 490 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 490 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 490 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 490 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 490 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 490 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3900 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 3900 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 3900 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 3900 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 3900 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 3900 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 190927000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 190927000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 190927000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 190927000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 190927000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 190927000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47480.645988 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47480.645988 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47480.645988 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 47480.645988 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47480.645988 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 47480.645988 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48955.641026 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48955.641026 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48955.641026 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48955.641026 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48955.641026 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48955.641026 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3284.843876 # Cycle average of tags in use -system.cpu.dcache.total_refs 168261959 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3284.708505 # Cycle average of tags in use +system.cpu.dcache.total_refs 168261813 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 40525.519990 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 40525.484827 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3284.843876 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.801964 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.801964 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 94753265 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94753265 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73508694 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73508694 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168261959 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168261959 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168261959 # number of overall hits -system.cpu.dcache.overall_hits::total 168261959 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1224 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1224 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 12035 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 12035 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 13259 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 13259 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 13259 # number of overall misses -system.cpu.dcache.overall_misses::total 13259 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 63567000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 63567000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 626556000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 626556000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 690123000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 690123000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 690123000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 690123000 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 3284.708505 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.801931 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.801931 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 94753261 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94753261 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73508552 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73508552 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168261813 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168261813 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168261813 # number of overall hits +system.cpu.dcache.overall_hits::total 168261813 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1228 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1228 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 12177 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 12177 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 13405 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 13405 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 13405 # number of overall misses +system.cpu.dcache.overall_misses::total 13405 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 68612500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 68612500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 712613500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 712613500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 781226000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 781226000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 781226000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 781226000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -255,38 +255,38 @@ system.cpu.dcache.overall_accesses::cpu.data 168275218 system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000013 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000013 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000164 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000164 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000079 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000079 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000079 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000079 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51933.823529 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51933.823529 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52061.154965 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 52061.154965 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52049.400407 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52049.400407 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52049.400407 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52049.400407 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000166 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000166 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000080 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000080 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000080 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000080 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55873.371336 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55873.371336 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58521.269607 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 58521.269607 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 58278.701977 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 58278.701977 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 58278.701977 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 58278.701977 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 82410500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 86009500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1848 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1905 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 44594.426407 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 45149.343832 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 649 # number of writebacks system.cpu.dcache.writebacks::total 649 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 274 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 274 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8833 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 8833 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 9107 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 9107 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 9107 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 9107 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 278 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 278 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8975 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 8975 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 9253 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 9253 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 9253 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 9253 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses @@ -295,14 +295,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45925000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 45925000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 169537000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 169537000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215462000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 215462000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215462000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 215462000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48743500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 48743500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 176149500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 176149500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 224893000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 224893000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 224893000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 224893000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -311,41 +311,41 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48342.105263 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48342.105263 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52947.220487 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52947.220487 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51893.545279 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51893.545279 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51893.545279 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51893.545279 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51308.947368 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51308.947368 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55012.336040 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55012.336040 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54164.980732 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 54164.980732 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54164.980732 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 54164.980732 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3900.421280 # Cycle average of tags in use -system.cpu.l2cache.total_refs 754 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3900.249221 # Cycle average of tags in use +system.cpu.l2cache.total_refs 753 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 4711 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.160051 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.159839 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 370.518684 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2902.345910 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 627.556686 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 370.495467 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2902.223601 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 627.530153 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.011307 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.088573 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019152 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.119031 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 548 # number of ReadReq hits +system.cpu.l2cache.occ_percent::cpu.inst 0.088569 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019151 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.119026 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 547 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 671 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 670 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 548 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 547 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 731 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 548 # number of overall hits +system.cpu.l2cache.demand_hits::total 730 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 547 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits -system.cpu.l2cache.overall_hits::total 731 # number of overall hits +system.cpu.l2cache.overall_hits::total 730 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 3353 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 824 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 4177 # number of ReadReq misses @@ -357,52 +357,52 @@ system.cpu.l2cache.demand_misses::total 7322 # nu system.cpu.l2cache.overall_misses::cpu.inst 3353 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7322 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 175438000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43307500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 218745500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 164970500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 164970500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 175438000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 208278000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 383716000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 175438000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 208278000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 383716000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 180755000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45853500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 226608500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 171775500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 171775500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 180755000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 217629000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 398384000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 180755000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 217629000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 398384000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 3900 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 4848 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 4847 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 3205 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 3205 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 3901 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 3900 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 8053 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 3901 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8052 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 3900 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 8053 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.859523 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 8052 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.859744 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870116 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.861592 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.861770 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981279 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.981279 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.859523 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.859744 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.909226 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859523 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.909339 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859744 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.909226 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52322.696093 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52557.645631 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52369.044769 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52454.848967 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52454.848967 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52322.696093 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52476.190476 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52405.900027 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52322.696093 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52476.190476 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52405.900027 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.909339 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53908.440203 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55647.451456 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 54251.496289 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54618.600954 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54618.600954 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53908.440203 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54832.199546 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54409.177820 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53908.440203 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54832.199546 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54409.177820 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,39 +422,39 @@ system.cpu.l2cache.demand_mshr_misses::total 7322 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3353 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7322 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134591000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33277500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 167868500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126757500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126757500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134591000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160035000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 294626000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134591000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160035000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 294626000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 139951500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 35886500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 175838000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133424000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133424000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139951500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 169310500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 309262000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139951500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 169310500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 309262000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859744 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.861592 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.861770 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981279 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859744 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.909226 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.909339 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859744 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.909226 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.471220 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40385.315534 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40188.771846 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40304.451510 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40304.451510 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.471220 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40321.239607 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40238.459437 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.471220 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40321.239607 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40238.459437 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.909339 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41739.188786 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43551.577670 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42096.720134 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42424.165342 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42424.165342 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41739.188786 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42658.226253 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42237.366840 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41739.188786 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42658.226253 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42237.366840 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini index 11313b921..50694257d 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -479,7 +479,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -511,7 +511,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout index 0f3bb3f65..cf6e41473 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:10:52 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:15:17 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second @@ -11,4 +11,4 @@ info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.066667 -Exiting @ tick 80278875500 because target called exit() +Exiting @ tick 80362284000 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index c7cbab894..cd4c1620b 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.080279 # Number of seconds simulated -sim_ticks 80278875500 # Number of ticks simulated -final_tick 80278875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.080362 # Number of seconds simulated +sim_ticks 80362284000 # Number of ticks simulated +final_tick 80362284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 279986 # Simulator instruction rate (inst/s) -host_op_rate 279986 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59846889 # Simulator tick rate (ticks/s) -host_mem_usage 226092 # Number of bytes of host memory used -host_seconds 1341.40 # Real time elapsed on the host +host_inst_rate 277812 # Simulator instruction rate (inst/s) +host_op_rate 277812 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59443930 # Simulator tick rate (ticks/s) +host_mem_usage 226052 # Number of bytes of host memory used +host_seconds 1351.90 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 222592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 222528 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 255296 # Number of bytes read from this memory -system.physmem.bytes_read::total 477888 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 222592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 222592 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3478 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 477824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 222528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 222528 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3477 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3989 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7467 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2772734 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3180114 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5952849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2772734 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2772734 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2772734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3180114 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5952849 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 7466 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2769060 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3176814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 5945874 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2769060 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2769060 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2769060 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3176814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5945874 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 103395556 # DTB read hits -system.cpu.dtb.read_misses 88623 # DTB read misses +system.cpu.dtb.read_hits 103417276 # DTB read hits +system.cpu.dtb.read_misses 89602 # DTB read misses system.cpu.dtb.read_acv 48603 # DTB read access violations -system.cpu.dtb.read_accesses 103484179 # DTB read accesses -system.cpu.dtb.write_hits 78997481 # DTB write hits -system.cpu.dtb.write_misses 1612 # DTB write misses -system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 78999093 # DTB write accesses -system.cpu.dtb.data_hits 182393037 # DTB hits -system.cpu.dtb.data_misses 90235 # DTB misses -system.cpu.dtb.data_acv 48607 # DTB access violations -system.cpu.dtb.data_accesses 182483272 # DTB accesses -system.cpu.itb.fetch_hits 52516361 # ITB hits -system.cpu.itb.fetch_misses 462 # ITB misses +system.cpu.dtb.read_accesses 103506878 # DTB read accesses +system.cpu.dtb.write_hits 79004376 # DTB write hits +system.cpu.dtb.write_misses 1630 # DTB write misses +system.cpu.dtb.write_acv 2 # DTB write access violations +system.cpu.dtb.write_accesses 79006006 # DTB write accesses +system.cpu.dtb.data_hits 182421652 # DTB hits +system.cpu.dtb.data_misses 91232 # DTB misses +system.cpu.dtb.data_acv 48605 # DTB access violations +system.cpu.dtb.data_accesses 182512884 # DTB accesses +system.cpu.itb.fetch_hits 52579177 # ITB hits +system.cpu.itb.fetch_misses 445 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 52516823 # ITB accesses +system.cpu.itb.fetch_accesses 52579622 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,112 +60,112 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 160557753 # number of cpu cycles simulated +system.cpu.numCycles 160724570 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 52050833 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 30287644 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1599078 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 29208422 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 24276895 # Number of BTB hits +system.cpu.BPredUnit.lookups 52097236 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 30296765 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1606699 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 28205553 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 24320024 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 9365187 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1064 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 53558689 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 462299559 # Number of instructions fetch has processed -system.cpu.fetch.Branches 52050833 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33642082 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 81488062 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 7763373 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19255908 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 8203 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 52516361 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 627395 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 160436815 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.881505 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.314292 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 9390300 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1099 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 53639869 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 462587639 # Number of instructions fetch has processed +system.cpu.fetch.Branches 52097236 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33710324 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 81534889 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 7793517 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19277229 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 188 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9332 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 52579177 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 630275 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 160609062 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.880209 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.314061 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 78948753 49.21% 49.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4374209 2.73% 51.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 7277181 4.54% 56.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5613096 3.50% 59.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 12419261 7.74% 67.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 8092340 5.04% 72.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5700245 3.55% 76.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1902354 1.19% 77.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36109376 22.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 79074173 49.23% 49.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4377828 2.73% 51.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 7270092 4.53% 56.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5630004 3.51% 59.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 12402470 7.72% 67.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 8106533 5.05% 72.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5708692 3.55% 76.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1929242 1.20% 77.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 36110028 22.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 160436815 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.324188 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.879335 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 59087459 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 14718957 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 76680946 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3827925 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6121528 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9736129 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4314 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 456834278 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12214 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6121528 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 62371527 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4787903 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 394179 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 77332259 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9429419 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 451139499 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 22898 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 7804449 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 294872724 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 593300368 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 314087845 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 279212523 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 160609062 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.324140 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.878139 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 59173788 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 14742505 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 76724469 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3825000 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6143300 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9747252 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4329 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 457055568 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12267 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6143300 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 62453650 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4799000 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 401905 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 77381021 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9430186 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 451385457 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 27 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 23697 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7813364 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 295061939 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 593486774 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 314314250 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 279172524 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 35340395 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 38267 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 351 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 27285549 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 106973750 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 81779740 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8912420 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6388901 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 416336746 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 335 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 407746724 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1079648 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 40502587 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 19766308 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 120 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 160436815 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.541479 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.007779 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 35529610 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 38241 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 341 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 27266716 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 107002651 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 81768344 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8923759 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6384538 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 416452671 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 325 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 407888910 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1078553 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 40628099 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 19685259 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 110 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 160609062 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.539638 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.007756 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 32040952 19.97% 19.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 26498917 16.52% 36.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25974021 16.19% 52.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 24801870 15.46% 68.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21558468 13.44% 81.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15451278 9.63% 91.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8686999 5.41% 96.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4112581 2.56% 99.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1311729 0.82% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 32138937 20.01% 20.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 26538030 16.52% 36.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25997150 16.19% 52.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24815453 15.45% 68.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21510440 13.39% 81.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15487887 9.64% 91.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8719479 5.43% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4101336 2.55% 99.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1300350 0.81% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 160436815 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 160609062 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35223 0.30% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35567 0.30% 0.30% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.30% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 74176 0.62% 0.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 4373 0.04% 0.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 3034 0.03% 0.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1856115 15.64% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1782113 15.01% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 73106 0.62% 0.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 5073 0.04% 0.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 3115 0.03% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1847413 15.60% 16.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1780061 15.04% 31.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.63% # attempts to use FU when none available @@ -187,120 +187,120 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.63% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5098643 42.95% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3017744 25.42% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5074453 42.86% 74.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3020406 25.51% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 158007223 38.75% 38.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126531 0.52% 39.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 33463416 8.21% 47.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7846184 1.92% 49.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2836368 0.70% 50.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16562414 4.06% 54.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1592681 0.39% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 105279650 25.82% 80.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 79998676 19.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 158124852 38.77% 38.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126520 0.52% 39.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 33455961 8.20% 47.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7846153 1.92% 49.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2842255 0.70% 50.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16560349 4.06% 54.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1591354 0.39% 54.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 105304781 25.82% 80.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 80003104 19.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 407746724 # Type of FU issued -system.cpu.iq.rate 2.539564 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11871421 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.029115 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 647615644 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 269617595 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237690414 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 341265688 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 187272317 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 162935841 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 245304560 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 174280004 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 14820631 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 407888910 # Type of FU issued +system.cpu.iq.rate 2.537813 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11839194 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.029026 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 648060515 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 269929713 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237794597 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 341244114 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 187202465 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 162943481 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 245434368 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 174260155 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 14844596 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 12219263 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 125114 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 50286 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8259011 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12248164 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 129765 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 51115 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8247615 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 260829 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 260830 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6121528 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2498871 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 366274 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 441262786 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 203691 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 106973750 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 81779740 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 335 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 126 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 50286 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1245920 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 565907 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1811827 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 403241961 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 103532839 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4504763 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6143300 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2503230 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 370145 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 441398780 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 177151 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 107002651 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 81768344 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 325 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 147 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 68 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 51115 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1257944 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 570703 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1828647 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 403351252 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 103555560 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4537658 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24925705 # number of nop insts executed -system.cpu.iew.exec_refs 182531964 # number of memory reference insts executed -system.cpu.iew.exec_branches 47208062 # Number of branches executed -system.cpu.iew.exec_stores 78999125 # Number of stores executed -system.cpu.iew.exec_rate 2.511507 # Inst execution rate -system.cpu.iew.wb_sent 401471936 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 400626255 # cumulative count of insts written-back -system.cpu.iew.wb_producers 195236823 # num instructions producing a value -system.cpu.iew.wb_consumers 273330928 # num instructions consuming a value +system.cpu.iew.exec_nop 24945784 # number of nop insts executed +system.cpu.iew.exec_refs 182561595 # number of memory reference insts executed +system.cpu.iew.exec_branches 47229945 # Number of branches executed +system.cpu.iew.exec_stores 79006035 # Number of stores executed +system.cpu.iew.exec_rate 2.509581 # Inst execution rate +system.cpu.iew.wb_sent 401565360 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 400738078 # cumulative count of insts written-back +system.cpu.iew.wb_producers 195225884 # num instructions producing a value +system.cpu.iew.wb_consumers 273294717 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.495216 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.714287 # average fanout of values written-back +system.cpu.iew.wb_rate 2.493322 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.714342 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 398664583 # The number of committed instructions system.cpu.commit.commitCommittedOps 398664583 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 42637745 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 42764408 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1594835 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 154315287 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.583442 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.967476 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1602444 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 154465762 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.580925 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.966951 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58825621 38.12% 38.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 23339762 15.12% 53.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13270606 8.60% 61.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11657566 7.55% 69.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8455456 5.48% 74.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5496217 3.56% 78.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5141868 3.33% 81.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3368734 2.18% 83.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 24759457 16.04% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58951255 38.16% 38.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 23354970 15.12% 53.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13285334 8.60% 61.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11679330 7.56% 69.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8439151 5.46% 74.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5483127 3.55% 78.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5136953 3.33% 81.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3378138 2.19% 83.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 24757504 16.03% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 154315287 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 154465762 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -311,70 +311,70 @@ system.cpu.commit.branches 44587533 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 24759457 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 24757504 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 570855181 # The number of ROB reads -system.cpu.rob.rob_writes 888739971 # The number of ROB writes -system.cpu.timesIdled 2694 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 120938 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 571134272 # The number of ROB reads +system.cpu.rob.rob_writes 889015019 # The number of ROB writes +system.cpu.timesIdled 3240 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 115508 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated -system.cpu.cpi 0.427499 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.427499 # CPI: Total CPI of All Threads -system.cpu.ipc 2.339188 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.339188 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 402766119 # number of integer regfile reads -system.cpu.int_regfile_writes 172550874 # number of integer regfile writes -system.cpu.fp_regfile_reads 158333530 # number of floating regfile reads -system.cpu.fp_regfile_writes 105213831 # number of floating regfile writes +system.cpu.cpi 0.427943 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.427943 # CPI: Total CPI of All Threads +system.cpu.ipc 2.336760 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.336760 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 402895481 # number of integer regfile reads +system.cpu.int_regfile_writes 172638002 # number of integer regfile writes +system.cpu.fp_regfile_reads 158340215 # number of floating regfile reads +system.cpu.fp_regfile_writes 105188641 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 2221 # number of replacements -system.cpu.icache.tagsinuse 1836.833971 # Cycle average of tags in use -system.cpu.icache.total_refs 52510942 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4151 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12650.190797 # Average number of references to valid blocks. +system.cpu.icache.replacements 2209 # number of replacements +system.cpu.icache.tagsinuse 1834.486163 # Cycle average of tags in use +system.cpu.icache.total_refs 52573796 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4140 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12698.984541 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1836.833971 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.896892 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.896892 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 52510942 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 52510942 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 52510942 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 52510942 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 52510942 # number of overall hits -system.cpu.icache.overall_hits::total 52510942 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5419 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5419 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5419 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5419 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5419 # number of overall misses -system.cpu.icache.overall_misses::total 5419 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 170335500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 170335500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 170335500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 170335500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 170335500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 170335500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 52516361 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 52516361 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 52516361 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 52516361 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 52516361 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 52516361 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000103 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000103 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000103 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000103 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000103 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000103 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31433.013471 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 31433.013471 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 31433.013471 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 31433.013471 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 31433.013471 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 31433.013471 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1834.486163 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.895745 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.895745 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 52573796 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 52573796 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 52573796 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 52573796 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 52573796 # number of overall hits +system.cpu.icache.overall_hits::total 52573796 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5381 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5381 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5381 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5381 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5381 # number of overall misses +system.cpu.icache.overall_misses::total 5381 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 173584500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 173584500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 173584500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 173584500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 173584500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 173584500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 52579177 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 52579177 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 52579177 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 52579177 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 52579177 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 52579177 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000102 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000102 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000102 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000102 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000102 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000102 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 32258.780896 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 32258.780896 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 32258.780896 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 32258.780896 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 32258.780896 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 32258.780896 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -383,284 +383,284 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1268 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1268 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1268 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1268 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1268 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1268 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4151 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4151 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4151 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4151 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4151 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4151 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 125070500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 125070500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 125070500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 125070500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 125070500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 125070500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1241 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1241 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1241 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1241 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1241 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1241 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4140 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4140 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4140 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4140 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4140 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4140 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130333500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 130333500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130333500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 130333500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130333500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 130333500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30130.209588 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 30130.209588 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30130.209588 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 30130.209588 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30130.209588 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 30130.209588 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 31481.521739 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 31481.521739 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 31481.521739 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 31481.521739 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 31481.521739 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 31481.521739 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 783 # number of replacements -system.cpu.dcache.tagsinuse 3297.903545 # Cycle average of tags in use -system.cpu.dcache.total_refs 161813696 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4184 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 38674.401530 # Average number of references to valid blocks. +system.cpu.dcache.replacements 796 # number of replacements +system.cpu.dcache.tagsinuse 3296.720309 # Cycle average of tags in use +system.cpu.dcache.total_refs 161811337 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4197 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 38554.047415 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3297.903545 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.805152 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.805152 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88312425 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88312425 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501253 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501253 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 18 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 18 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 161813678 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 161813678 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 161813678 # number of overall hits -system.cpu.dcache.overall_hits::total 161813678 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1653 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1653 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19476 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19476 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21129 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21129 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21129 # number of overall misses -system.cpu.dcache.overall_misses::total 21129 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 55208500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 55208500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 570020000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 570020000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 625228500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 625228500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 625228500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 625228500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88314078 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88314078 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 3296.720309 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.804863 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.804863 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 88310042 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88310042 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501280 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501280 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 161811322 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 161811322 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 161811322 # number of overall hits +system.cpu.dcache.overall_hits::total 161811322 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1790 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1790 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19449 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19449 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21239 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21239 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21239 # number of overall misses +system.cpu.dcache.overall_misses::total 21239 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 68481500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 68481500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 731423000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 731423000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 799904500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 799904500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 799904500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 799904500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88311832 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88311832 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 18 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 18 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 161834807 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 161834807 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 161834807 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 161834807 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 161832561 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 161832561 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 161832561 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 161832561 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000265 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000265 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000131 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000131 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000131 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000131 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33398.971567 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33398.971567 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29267.816800 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29267.816800 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29591.012353 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29591.012353 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29591.012353 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29591.012353 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38257.821229 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38257.821229 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37607.229163 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37607.229163 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37662.060361 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37662.060361 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37662.060361 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37662.060361 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7500 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 661 # number of writebacks -system.cpu.dcache.writebacks::total 661 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 664 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 664 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16281 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16281 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 16945 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 16945 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 16945 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 16945 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 989 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 989 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3195 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3195 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4184 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4184 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4184 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4184 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31319000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 31319000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 113198500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 113198500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 144517500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 144517500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 144517500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 144517500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 676 # number of writebacks +system.cpu.dcache.writebacks::total 676 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 798 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 798 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16244 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16244 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17042 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17042 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17042 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17042 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 992 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 992 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3205 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3205 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4197 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4197 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4197 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4197 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36143000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36143000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 129182000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 129182000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165325000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 165325000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 165325000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 165325000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31667.340748 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31667.340748 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35429.890454 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35429.890454 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34540.511472 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34540.511472 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34540.511472 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34540.511472 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36434.475806 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36434.475806 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40306.396256 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40306.396256 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 39391.231832 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 39391.231832 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 39391.231832 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 39391.231832 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 4030.550390 # Cycle average of tags in use -system.cpu.l2cache.total_refs 892 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4871 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.183125 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 4031.271945 # Cycle average of tags in use +system.cpu.l2cache.total_refs 894 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 4870 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.183573 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 372.758053 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2998.208675 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 659.583662 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011376 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.091498 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.020129 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.123003 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 673 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 131 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 804 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 661 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 661 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 64 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 64 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 673 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 195 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 868 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 673 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 195 # number of overall hits -system.cpu.l2cache.overall_hits::total 868 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3478 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::writebacks 372.726773 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 3000.006522 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 658.538650 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011375 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.091553 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.020097 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.123025 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 663 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 134 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 797 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 676 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 676 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 74 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 74 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 663 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 208 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 871 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 663 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 208 # number of overall hits +system.cpu.l2cache.overall_hits::total 871 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3477 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 858 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4336 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4335 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 3131 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 3131 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3478 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 3477 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 3989 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7467 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3478 # number of overall misses +system.cpu.l2cache.demand_misses::total 7466 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3477 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3989 # number of overall misses -system.cpu.l2cache.overall_misses::total 7467 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 119555000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29668000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 149223000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 108422000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 108422000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 119555000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 138090000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 257645000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 119555000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 138090000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 257645000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 4151 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 989 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5140 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 661 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 661 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 3195 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 3195 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4151 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 4184 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 8335 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4151 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4184 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 8335 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.837870 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.867543 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.843580 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.979969 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.979969 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.837870 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.953394 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.895861 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.837870 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.953394 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.895861 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34374.640598 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34578.088578 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34414.898524 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34628.553178 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34628.553178 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34374.640598 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34617.698671 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34504.486407 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34374.640598 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34617.698671 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34504.486407 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.overall_misses::total 7466 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 124004000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 34532500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 158536500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 124919000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 124919000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 124004000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 159451500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 283455500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 124004000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 159451500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 283455500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4140 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5132 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 676 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 676 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 3205 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 3205 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4140 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4197 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8337 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4140 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4197 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 8337 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.839855 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.864919 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.844700 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.976911 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.976911 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.839855 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.950441 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.895526 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.839855 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.950441 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.895526 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35664.078228 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40247.668998 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36571.280277 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39897.476844 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39897.476844 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35664.078228 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39972.800201 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37966.180016 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35664.078228 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39972.800201 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37966.180016 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 3000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3478 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3477 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 858 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4336 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4335 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3131 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 3131 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3478 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3477 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 3989 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7467 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3478 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7466 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3477 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3989 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7467 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 108320000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26958500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 135278500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98537000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98537000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 108320000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 125495500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 233815500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 108320000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 125495500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 233815500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.837870 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867543 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.843580 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.979969 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.979969 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.837870 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.953394 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.895861 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.837870 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.953394 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.895861 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31144.335825 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31420.163170 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31198.916052 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31471.414883 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31471.414883 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31144.335825 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31460.391075 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31313.177983 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31144.335825 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31460.391075 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31313.177983 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::total 7466 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112721000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 31878000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 144599000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115138500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115138500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112721000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 147016500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 259737500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112721000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 147016500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 259737500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.839855 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.864919 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.844700 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.976911 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.976911 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.839855 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.950441 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.895526 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.839855 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.950441 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.895526 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32419.039402 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37153.846154 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33356.170704 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36773.714468 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36773.714468 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32419.039402 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36855.477563 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34789.378516 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32419.039402 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36855.477563 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34789.378516 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini index b7b2de2d4..d4c58b08d 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -148,7 +148,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -180,7 +180,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout index 535f9cae3..d468809f0 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:12:10 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:39:35 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second @@ -11,4 +11,4 @@ info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.566667 -Exiting @ tick 567342918000 because target called exit() +Exiting @ tick 567365869000 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 049129481..df4992494 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.567343 # Number of seconds simulated -sim_ticks 567342918000 # Number of ticks simulated -final_tick 567342918000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.567366 # Number of seconds simulated +sim_ticks 567365869000 # Number of ticks simulated +final_tick 567365869000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2055836 # Simulator instruction rate (inst/s) -host_op_rate 2055836 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2925676505 # Simulator tick rate (ticks/s) -host_mem_usage 224040 # Number of bytes of host memory used -host_seconds 193.92 # Real time elapsed on the host +host_inst_rate 2066411 # Simulator instruction rate (inst/s) +host_op_rate 2066411 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2940844836 # Simulator tick rate (ticks/s) +host_mem_usage 224004 # Number of bytes of host memory used +host_seconds 192.93 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 205120 # Nu system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7174 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 361545 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 447729 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 809274 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 361545 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 361545 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 361545 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 447729 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 809274 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 361530 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 447711 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 809241 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 361530 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 361530 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 361530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 447711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 809241 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 1134685836 # number of cpu cycles simulated +system.cpu.numCycles 1134731738 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664609 # Number of instructions committed @@ -79,18 +79,18 @@ system.cpu.num_mem_refs 168275276 # nu system.cpu.num_load_insts 94754511 # Number of load instructions system.cpu.num_store_insts 73520765 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1134685836 # Number of busy cycles +system.cpu.num_busy_cycles 1134731738 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1769 # number of replacements -system.cpu.icache.tagsinuse 1795.131072 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1795.107538 # Cycle average of tags in use system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1795.131072 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.876529 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.876529 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1795.107538 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.876517 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.876517 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits @@ -103,12 +103,12 @@ system.cpu.icache.demand_misses::cpu.inst 3673 # n system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses system.cpu.icache.overall_misses::total 3673 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 186032000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 186032000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 186032000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 186032000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 186032000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 186032000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 186108000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 186108000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 186108000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 186108000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 186108000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 186108000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses @@ -121,12 +121,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50648.516199 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 50648.516199 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 50648.516199 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 50648.516199 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 50648.516199 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 50648.516199 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50669.207732 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 50669.207732 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 50669.207732 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 50669.207732 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 50669.207732 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 50669.207732 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -141,34 +141,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3673 system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175013000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 175013000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175013000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 175013000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175013000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 175013000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175089000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 175089000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175089000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 175089000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175089000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 175089000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47648.516199 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47648.516199 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47669.207732 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47669.207732 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47669.207732 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 47669.207732 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47669.207732 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 47669.207732 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3288.912595 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3288.859436 # Cycle average of tags in use system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3288.912595 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.802957 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.802957 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 3288.859436 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.802944 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.802944 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits @@ -185,14 +185,14 @@ system.cpu.dcache.demand_misses::cpu.data 4152 # n system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses system.cpu.dcache.overall_misses::total 4152 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 48034000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 48034000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 176792000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 176792000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 224826000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 224826000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 224826000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 224826000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 48094000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 48094000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 176797000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 176797000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 224891000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 224891000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 224891000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 224891000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) @@ -209,14 +209,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50562.105263 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50562.105263 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55212.991880 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55212.991880 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54148.843931 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54148.843931 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54148.843931 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54148.843931 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50625.263158 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50625.263158 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55214.553404 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55214.553404 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54164.499037 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54164.499037 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54164.499037 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54164.499037 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -235,14 +235,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45184000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 45184000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167186000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 167186000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212370000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 212370000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212370000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 212370000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45244000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 45244000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167191000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 167191000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212435000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 212435000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212435000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 212435000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -251,28 +251,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47562.105263 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47562.105263 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52212.991880 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52212.991880 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47625.263158 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47625.263158 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52214.553404 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52214.553404 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51164.499037 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51164.499037 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51164.499037 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51164.499037 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3772.462815 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3772.396394 # Cycle average of tags in use system.cpu.l2cache.total_refs 674 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 4566 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.147613 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 371.536806 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2770.454477 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 630.471532 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 371.526936 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2770.408528 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 630.460931 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.011338 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.084546 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.019240 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.115126 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.115124 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 468 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 591 # number of ReadReq hits diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index 27728d570..e98d14637 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -497,7 +497,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -529,7 +529,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index e6faeb5f0..7d2acfcbb 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:48:53 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 15:48:29 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -13,4 +13,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.070000 -Exiting @ tick 71244143500 because target called exit() +Exiting @ tick 71229334000 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index e982040ed..48ec2839e 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.071244 # Number of seconds simulated -sim_ticks 71244143500 # Number of ticks simulated -final_tick 71244143500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.071229 # Number of seconds simulated +sim_ticks 71229334000 # Number of ticks simulated +final_tick 71229334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 187993 # Simulator instruction rate (inst/s) -host_op_rate 240337 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49051248 # Simulator tick rate (ticks/s) -host_mem_usage 243200 # Number of bytes of host memory used -host_seconds 1452.44 # Real time elapsed on the host -sim_insts 273048446 # Number of instructions simulated -sim_ops 349076170 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 195520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 273792 # Number of bytes read from this memory -system.physmem.bytes_read::total 469312 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 195520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 195520 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3055 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4278 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7333 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2744366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3843011 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6587377 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2744366 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2744366 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2744366 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3843011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6587377 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 127900 # Simulator instruction rate (inst/s) +host_op_rate 163512 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33364795 # Simulator tick rate (ticks/s) +host_mem_usage 243124 # Number of bytes of host memory used +host_seconds 2134.87 # Real time elapsed on the host +sim_insts 273048466 # Number of instructions simulated +sim_ops 349076190 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 195712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 273280 # Number of bytes read from this memory +system.physmem.bytes_read::total 468992 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 195712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 195712 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3058 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4270 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2747632 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3836622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6584254 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2747632 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2747632 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2747632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3836622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6584254 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,107 +70,107 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 142488288 # number of cpu cycles simulated +system.cpu.numCycles 142458669 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 36834655 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 22011992 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2128141 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 21111775 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 17921807 # Number of BTB hits +system.cpu.BPredUnit.lookups 36827289 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 22021149 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2124112 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 21185272 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 17907212 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 7049660 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 9673 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 41170537 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 330092344 # Number of instructions fetch has processed -system.cpu.fetch.Branches 36834655 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24971467 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 74065448 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8653461 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 20659218 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 3712 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 39589827 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 662584 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 142371733 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.982100 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.456260 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 7048127 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 9776 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 41164597 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 330015965 # Number of instructions fetch has processed +system.cpu.fetch.Branches 36827289 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24955339 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 74037174 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8640903 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 20677414 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 46 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 3984 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 39570950 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 662120 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 142347473 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.981638 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.456068 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68999572 48.46% 48.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 7443838 5.23% 53.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5890912 4.14% 57.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6290109 4.42% 62.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 5018667 3.53% 65.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4222472 2.97% 68.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3222890 2.26% 71.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4319860 3.03% 74.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36963413 25.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 69001909 48.47% 48.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 7430233 5.22% 53.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5888428 4.14% 57.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6296154 4.42% 62.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5019761 3.53% 65.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4223315 2.97% 68.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3223904 2.26% 71.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4316057 3.03% 74.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 36947712 25.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 142371733 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258510 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.316628 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 47920905 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 15947714 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 69670851 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2428941 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6403322 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7589257 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 69989 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 416841547 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 209997 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6403322 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 53735690 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1551358 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 361067 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 66219864 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14100432 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 406248964 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 31 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1649610 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10115480 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 773 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 445265070 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2397426033 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1310073571 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1087352462 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 384584954 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 60680116 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 19505 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 19502 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 35831958 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 105842469 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 93258241 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4666139 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5699487 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 393022623 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 30465 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 378573033 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1364119 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 42964941 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 113697743 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 5987 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 142371733 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.659046 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.045030 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 142347473 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258512 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.316573 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 47914284 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 15959399 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 69656008 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2423234 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6394548 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7585679 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 70199 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 416758303 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 209359 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6394548 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 53729037 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1556343 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 362126 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 66198989 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14106430 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 406180848 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 80 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1648620 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10123493 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1169 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 445266108 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2397137405 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1309627482 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1087509923 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 384584986 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 60681122 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 19329 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 19327 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 35836582 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 105837544 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 93231927 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4645950 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5672170 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 392964645 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 30275 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 378555721 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1363581 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 42910046 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 113514871 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 5793 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 142347473 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.659378 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.045296 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 29238426 20.54% 20.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 20559915 14.44% 34.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20888687 14.67% 49.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18235605 12.81% 62.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24142271 16.96% 79.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16046767 11.27% 90.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9027765 6.34% 97.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3298956 2.32% 99.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 933341 0.66% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 29227228 20.53% 20.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20574959 14.45% 34.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20845821 14.64% 49.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18255784 12.82% 62.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 24133952 16.95% 79.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16055098 11.28% 90.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9008550 6.33% 97.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3309478 2.32% 99.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 936603 0.66% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 142371733 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 142347473 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9050 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4700 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9705 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4696 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -189,22 +189,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 48305 0.27% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 48154 0.27% 0.35% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7771 0.04% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 390 0.00% 0.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7801 0.04% 0.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 391 0.00% 0.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 194430 1.08% 1.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 4896 0.03% 1.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 241266 1.34% 2.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 194497 1.08% 1.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 4577 0.03% 1.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241305 1.34% 2.85% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9438470 52.59% 55.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7998776 44.57% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9433836 52.57% 55.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7998969 44.58% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 128705433 34.00% 34.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2178586 0.58% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 128679498 33.99% 33.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2178469 0.58% 34.57% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.57% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.57% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.57% # Type of FU issued @@ -215,7 +215,7 @@ system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.57% # Ty system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.57% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.57% # Type of FU issued system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 5 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 3 0.00% 34.57% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.57% # Type of FU issued system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.57% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.57% # Type of FU issued @@ -223,169 +223,169 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.57% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.57% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.57% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6839771 1.81% 36.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8697995 2.30% 38.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3451888 0.91% 39.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1605167 0.42% 40.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21254253 5.61% 45.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7183697 1.90% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7136969 1.89% 49.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 102677998 27.12% 76.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88665985 23.42% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6838580 1.81% 36.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8699925 2.30% 38.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3453303 0.91% 39.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1605459 0.42% 40.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 21250786 5.61% 45.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7183426 1.90% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7137674 1.89% 49.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.45% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 102689873 27.13% 76.58% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88663438 23.42% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 378573033 # Type of FU issued -system.cpu.iq.rate 2.656871 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17948057 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047410 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 668230837 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 303627249 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 252741444 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 250599138 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 132404625 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118730959 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 267327381 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 129193709 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 10789214 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 378555721 # Type of FU issued +system.cpu.iq.rate 2.657302 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17943934 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047401 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 668132849 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 303460922 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 252722845 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 250633581 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 132457901 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118739342 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 267290872 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 129208783 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 10791540 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 11191376 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 112013 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13979 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10880305 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 11186447 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 112704 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14184 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10853987 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7857 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 112 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 9836 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 124 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6403322 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 34047 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1473 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 393102382 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1223414 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 105842469 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 93258241 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 19294 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 195 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 174 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13979 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1692038 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 558009 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2250047 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 373788733 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101161202 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4784300 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6394548 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 40816 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2257 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 393044352 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1233465 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 105837544 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 93231927 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 19117 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 279 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 239 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14184 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1686736 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 558131 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2244867 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 373775544 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101165584 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4780177 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 49294 # number of nop insts executed -system.cpu.iew.exec_refs 188542226 # number of memory reference insts executed -system.cpu.iew.exec_branches 32415827 # Number of branches executed -system.cpu.iew.exec_stores 87381024 # Number of stores executed -system.cpu.iew.exec_rate 2.623294 # Inst execution rate -system.cpu.iew.wb_sent 372275263 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 371472403 # cumulative count of insts written-back -system.cpu.iew.wb_producers 184833323 # num instructions producing a value -system.cpu.iew.wb_consumers 367854017 # num instructions consuming a value +system.cpu.iew.exec_nop 49432 # number of nop insts executed +system.cpu.iew.exec_refs 188551589 # number of memory reference insts executed +system.cpu.iew.exec_branches 32411941 # Number of branches executed +system.cpu.iew.exec_stores 87386005 # Number of stores executed +system.cpu.iew.exec_rate 2.623747 # Inst execution rate +system.cpu.iew.wb_sent 372264339 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 371462187 # cumulative count of insts written-back +system.cpu.iew.wb_producers 184812981 # num instructions producing a value +system.cpu.iew.wb_consumers 367833213 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.607038 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.502464 # average fanout of values written-back +system.cpu.iew.wb_rate 2.607508 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.502437 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 273049058 # The number of committed instructions -system.cpu.commit.commitCommittedOps 349076782 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 44025608 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 24478 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2100754 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 135968412 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.567337 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.653672 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 273049078 # The number of committed instructions +system.cpu.commit.commitCommittedOps 349076802 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 43967644 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 24482 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2096481 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 135952926 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.567630 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.653370 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 38641813 28.42% 28.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 29058445 21.37% 49.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13534255 9.95% 59.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11222379 8.25% 68.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13789944 10.14% 78.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7224545 5.31% 83.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4032637 2.97% 86.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3910785 2.88% 89.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14553609 10.70% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 38639864 28.42% 28.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 29020043 21.35% 49.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13541053 9.96% 59.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11234412 8.26% 67.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13804382 10.15% 78.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7226420 5.32% 83.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 4033022 2.97% 86.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3906183 2.87% 89.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14547547 10.70% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 135968412 # Number of insts commited each cycle -system.cpu.commit.committedInsts 273049058 # Number of instructions committed -system.cpu.commit.committedOps 349076782 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 135952926 # Number of insts commited each cycle +system.cpu.commit.committedInsts 273049078 # Number of instructions committed +system.cpu.commit.committedOps 349076802 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 177029029 # Number of memory references committed -system.cpu.commit.loads 94651093 # Number of loads committed +system.cpu.commit.refs 177029037 # Number of memory references committed +system.cpu.commit.loads 94651097 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 30523988 # Number of branches committed +system.cpu.commit.branches 30523992 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 279593987 # Number of committed integer instructions. +system.cpu.commit.int_insts 279594003 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14553609 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14547547 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 514514670 # The number of ROB reads -system.cpu.rob.rob_writes 792612920 # The number of ROB writes -system.cpu.timesIdled 2826 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 116555 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 273048446 # Number of Instructions Simulated -system.cpu.committedOps 349076170 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 273048446 # Number of Instructions Simulated -system.cpu.cpi 0.521843 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.521843 # CPI: Total CPI of All Threads -system.cpu.ipc 1.916287 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.916287 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1784947411 # number of integer regfile reads -system.cpu.int_regfile_writes 236351279 # number of integer regfile writes -system.cpu.fp_regfile_reads 189697788 # number of floating regfile reads -system.cpu.fp_regfile_writes 133433924 # number of floating regfile writes -system.cpu.misc_regfile_reads 991980863 # number of misc regfile reads -system.cpu.misc_regfile_writes 34426471 # number of misc regfile writes -system.cpu.icache.replacements 14091 # number of replacements -system.cpu.icache.tagsinuse 1855.139503 # Cycle average of tags in use -system.cpu.icache.total_refs 39573076 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15985 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2475.638161 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 514447302 # The number of ROB reads +system.cpu.rob.rob_writes 792488332 # The number of ROB writes +system.cpu.timesIdled 3380 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 111196 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 273048466 # Number of Instructions Simulated +system.cpu.committedOps 349076190 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 273048466 # Number of Instructions Simulated +system.cpu.cpi 0.521734 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.521734 # CPI: Total CPI of All Threads +system.cpu.ipc 1.916686 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.916686 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1784924885 # number of integer regfile reads +system.cpu.int_regfile_writes 236340288 # number of integer regfile writes +system.cpu.fp_regfile_reads 189697402 # number of floating regfile reads +system.cpu.fp_regfile_writes 133438574 # number of floating regfile writes +system.cpu.misc_regfile_reads 991950959 # number of misc regfile reads +system.cpu.misc_regfile_writes 34426479 # number of misc regfile writes +system.cpu.icache.replacements 14092 # number of replacements +system.cpu.icache.tagsinuse 1857.122291 # Cycle average of tags in use +system.cpu.icache.total_refs 39554212 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 15988 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2473.993745 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1855.139503 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.905830 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.905830 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 39573076 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 39573076 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 39573076 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 39573076 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 39573076 # number of overall hits -system.cpu.icache.overall_hits::total 39573076 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 16751 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 16751 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 16751 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 16751 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 16751 # number of overall misses -system.cpu.icache.overall_misses::total 16751 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 205369500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 205369500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 205369500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 205369500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 205369500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 205369500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 39589827 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 39589827 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 39589827 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 39589827 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 39589827 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 39589827 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1857.122291 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.906798 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.906798 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 39554212 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 39554212 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 39554212 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 39554212 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 39554212 # number of overall hits +system.cpu.icache.overall_hits::total 39554212 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 16738 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 16738 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 16738 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 16738 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 16738 # number of overall misses +system.cpu.icache.overall_misses::total 16738 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 211077500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 211077500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 211077500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 211077500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 211077500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 211077500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 39570950 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 39570950 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 39570950 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 39570950 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 39570950 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 39570950 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000423 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000423 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000423 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000423 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000423 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000423 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12260.133723 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 12260.133723 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 12260.133723 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 12260.133723 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 12260.133723 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 12260.133723 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12610.676305 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 12610.676305 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 12610.676305 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 12610.676305 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 12610.676305 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 12610.676305 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -394,146 +394,146 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 765 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 765 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 765 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 765 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 765 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 765 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15986 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15986 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15986 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15986 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15986 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15986 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 137471000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 137471000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 137471000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 137471000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 137471000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 137471000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 750 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 750 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 750 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 750 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 750 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 750 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15988 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15988 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15988 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15988 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15988 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15988 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 140340000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 140340000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 140340000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 140340000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 140340000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 140340000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000404 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000404 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000404 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000404 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000404 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000404 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8599.462029 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8599.462029 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8599.462029 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 8599.462029 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8599.462029 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 8599.462029 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8777.833375 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8777.833375 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8777.833375 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 8777.833375 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8777.833375 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 8777.833375 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1422 # number of replacements -system.cpu.dcache.tagsinuse 3120.754345 # Cycle average of tags in use -system.cpu.dcache.total_refs 172231049 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4634 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37166.821105 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1419 # number of replacements +system.cpu.dcache.tagsinuse 3123.008839 # Cycle average of tags in use +system.cpu.dcache.total_refs 172229353 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4629 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37206.600346 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3120.754345 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.761903 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.761903 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 90171406 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 90171406 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82032842 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82032842 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 13547 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 13547 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 13253 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 13253 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 172204248 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 172204248 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 172204248 # number of overall hits -system.cpu.dcache.overall_hits::total 172204248 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3698 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3698 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19818 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19818 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 3123.008839 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.762453 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.762453 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 90171250 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 90171250 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82031303 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82031303 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 13543 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 13543 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 13257 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 13257 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 172202553 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 172202553 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 172202553 # number of overall hits +system.cpu.dcache.overall_hits::total 172202553 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3872 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3872 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 21357 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 21357 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 23516 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 23516 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 23516 # number of overall misses -system.cpu.dcache.overall_misses::total 23516 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 118442000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 118442000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 655611500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 655611500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 25229 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25229 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25229 # number of overall misses +system.cpu.dcache.overall_misses::total 25229 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 139932500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 139932500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 828692500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 828692500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 76000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 774053500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 774053500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 774053500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 774053500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 90175104 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 90175104 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 968625000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 968625000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 968625000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 968625000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 90175122 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 90175122 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052660 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052660 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13549 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13549 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 13253 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 13253 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 172227764 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 172227764 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 172227764 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 172227764 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000041 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000242 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000242 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13545 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 13545 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 13257 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 13257 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 172227782 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 172227782 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 172227782 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 172227782 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000043 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000043 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000260 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000260 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000137 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000137 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000137 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000137 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32028.664143 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32028.664143 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33081.617721 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33081.617721 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.000146 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000146 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000146 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000146 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36139.591942 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36139.591942 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38801.915063 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38801.915063 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32916.035890 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32916.035890 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32916.035890 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32916.035890 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38393.317214 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38393.317214 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38393.317214 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38393.317214 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 307000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 334500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 27909.090909 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 27875 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1041 # number of writebacks -system.cpu.dcache.writebacks::total 1041 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1882 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1882 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16999 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16999 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1036 # number of writebacks +system.cpu.dcache.writebacks::total 1036 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2060 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2060 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18540 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18540 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 18881 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 18881 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 18881 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 18881 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1816 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1816 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2819 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2819 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4635 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4635 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4635 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4635 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 55172500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 55172500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 100155500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 100155500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 155328000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 155328000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 155328000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 155328000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 20600 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20600 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20600 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20600 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1812 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1812 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2817 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2817 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4629 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4629 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4629 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4629 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 59543000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 59543000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 108480500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 108480500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 168023500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 168023500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 168023500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 168023500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses @@ -542,102 +542,98 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30381.332599 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30381.332599 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35528.733593 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35528.733593 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33511.974110 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 33511.974110 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33511.974110 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33511.974110 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32860.375276 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32860.375276 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38509.229677 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38509.229677 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36298.012530 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36298.012530 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36298.012530 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36298.012530 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3993.397220 # Cycle average of tags in use -system.cpu.l2cache.total_refs 13323 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 5445 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.446832 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3998.487468 # Cycle average of tags in use +system.cpu.l2cache.total_refs 13321 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 5435 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.450966 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 372.052721 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2804.768410 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 816.576088 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011354 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.085595 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.024920 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.121869 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 12916 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 301 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13217 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1041 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1041 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits +system.cpu.l2cache.occ_blocks::writebacks 369.804523 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2809.273532 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 819.409413 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011286 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.085732 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.025006 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.122024 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 12911 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 300 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 13211 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1036 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1036 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 18 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 18 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12916 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 319 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13235 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12916 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 319 # number of overall hits -system.cpu.l2cache.overall_hits::total 13235 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3069 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1513 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4582 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 2802 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2802 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3069 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 4315 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7384 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3069 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 4315 # number of overall misses -system.cpu.l2cache.overall_misses::total 7384 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 105043500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51988500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 157032000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 96644500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 96644500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 105043500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 148633000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 253676500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 105043500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 148633000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 253676500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 15985 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1814 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_hits::cpu.inst 12911 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 318 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13229 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 12911 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 318 # number of overall hits +system.cpu.l2cache.overall_hits::total 13229 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3077 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1511 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4588 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 2800 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2800 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3077 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 4311 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7388 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3077 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 4311 # number of overall misses +system.cpu.l2cache.overall_misses::total 7388 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 108258000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 56236500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 164494500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104322000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 104322000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 108258000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 160558500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 268816500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 108258000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 160558500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 268816500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 15988 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1811 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 17799 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1041 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1041 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2820 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2820 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 15985 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 4634 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 20619 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 15985 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4634 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 20619 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.191992 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.834068 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.257430 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993617 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.993617 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.191992 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.931161 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.358116 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.191992 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.931161 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.358116 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34227.272727 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34361.202908 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34271.497163 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34491.256246 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34491.256246 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34227.272727 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34445.654693 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34354.888949 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34227.272727 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34445.654693 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34354.888949 # average overall miss latency +system.cpu.l2cache.Writeback_accesses::writebacks 1036 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1036 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2818 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2818 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 15988 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4629 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 20617 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 15988 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4629 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 20617 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192457 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.834346 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.257767 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993612 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.993612 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192457 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.931303 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.358345 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192457 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.931303 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.358345 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35182.970426 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 37218.067505 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35853.204010 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 37257.857143 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 37257.857143 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35182.970426 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37243.910926 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 36385.557661 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35182.970426 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37243.910926 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 36385.557661 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -646,59 +642,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 37 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 37 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 51 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 37 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 51 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3055 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1476 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4531 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2802 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 2802 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3055 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 4278 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7333 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3055 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 4278 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7333 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 94947500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 46180500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 141128000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 87716500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 87716500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 94947500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 133897000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 228844500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 94947500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 133897000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 228844500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191117 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.813671 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.254565 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993617 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993617 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191117 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923177 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.355643 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191117 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923177 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.355643 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31079.378069 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31287.601626 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31147.208122 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31304.960742 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31304.960742 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31079.378069 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31298.971482 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31207.486704 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31079.378069 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31298.971482 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31207.486704 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 19 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 41 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 19 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 41 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 60 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 19 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 41 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 60 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3058 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1470 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4528 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2800 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 2800 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3058 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4270 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7328 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3058 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 4270 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 98125000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 50350500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 148475500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 95488500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95488500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 98125000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 145839000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 243964000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 98125000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 145839000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 243964000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191268 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.811706 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.254396 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993612 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993612 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191268 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922445 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.355435 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191268 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922445 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.355435 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32087.965991 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34252.040816 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32790.525618 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34103.035714 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34103.035714 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32087.965991 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34154.332553 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33292.030568 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32087.965991 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34154.332553 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33292.030568 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini index 68ac46334..0fa8c3883 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini @@ -166,7 +166,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -198,7 +198,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout index ddb90c634..091d7545a 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:56:30 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 16:02:17 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -13,4 +13,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.520000 -Exiting @ tick 525854423000 because target called exit() +Exiting @ tick 525920061000 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index bbdf06ba7..3487a1e4f 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.525854 # Number of seconds simulated -sim_ticks 525854423000 # Number of ticks simulated -final_tick 525854423000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.525920 # Number of seconds simulated +sim_ticks 525920061000 # Number of ticks simulated +final_tick 525920061000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1009014 # Simulator instruction rate (inst/s) -host_op_rate 1289987 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1945426950 # Simulator tick rate (ticks/s) -host_mem_usage 241152 # Number of bytes of host memory used -host_seconds 270.30 # Real time elapsed on the host +host_inst_rate 966127 # Simulator instruction rate (inst/s) +host_op_rate 1235157 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1862970627 # Simulator tick rate (ticks/s) +host_mem_usage 241076 # Number of bytes of host memory used +host_seconds 282.30 # Real time elapsed on the host sim_insts 272739283 # Number of instructions simulated sim_ops 348687122 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 166976 # Nu system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 317533 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 513967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 831500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 317533 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317533 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 317533 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 513967 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 831500 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 317493 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 513903 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 831396 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 317493 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317493 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 317493 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 513903 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 831396 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,7 +70,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 1051708846 # number of cpu cycles simulated +system.cpu.numCycles 1051840122 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 272739283 # Number of instructions committed @@ -89,18 +89,18 @@ system.cpu.num_mem_refs 177024356 # nu system.cpu.num_load_insts 94648757 # Number of load instructions system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1051708846 # Number of busy cycles +system.cpu.num_busy_cycles 1051840122 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 13796 # number of replacements -system.cpu.icache.tagsinuse 1765.984191 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1765.965460 # Cycle average of tags in use system.cpu.icache.total_refs 348644747 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 22344.725181 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1765.984191 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.862297 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.862297 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1765.965460 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.862288 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.862288 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits @@ -113,12 +113,12 @@ system.cpu.icache.demand_misses::cpu.inst 15603 # n system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses system.cpu.icache.overall_misses::total 15603 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 328020000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 328020000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 328020000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 328020000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 328020000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 328020000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 328087000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 328087000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 328087000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 328087000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 328087000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 328087000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 348660350 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 348660350 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 348660350 # number of demand (read+write) accesses @@ -131,12 +131,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21022.880215 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21022.880215 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21022.880215 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21022.880215 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21022.880215 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21022.880215 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21027.174261 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21027.174261 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21027.174261 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21027.174261 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21027.174261 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21027.174261 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -151,34 +151,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603 system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281211000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281211000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281211000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281211000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281211000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281211000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281278000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 281278000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281278000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 281278000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281278000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 281278000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18022.880215 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18022.880215 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18027.174261 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18027.174261 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18027.174261 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18027.174261 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18027.174261 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18027.174261 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1332 # number of replacements -system.cpu.dcache.tagsinuse 3078.396294 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3078.361570 # Cycle average of tags in use system.cpu.dcache.total_refs 176641599 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4478 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 39446.538410 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3078.396294 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.751562 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.751562 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 3078.361570 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.751553 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.751553 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits @@ -199,14 +199,14 @@ system.cpu.dcache.demand_misses::cpu.data 4478 # n system.cpu.dcache.demand_misses::total 4478 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 4478 # number of overall misses system.cpu.dcache.overall_misses::total 4478 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 79898000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 79898000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 160160000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 160160000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 240058000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 240058000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 240058000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 240058000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 80120000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 80120000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 160192000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 160192000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 240312000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 240312000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 240312000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 240312000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94571610 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94571610 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) @@ -227,14 +227,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49749.688667 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49749.688667 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55766.016713 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55766.016713 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53608.307280 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53608.307280 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53608.307280 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53608.307280 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49887.920299 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49887.920299 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55777.158774 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55777.158774 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53665.029031 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53665.029031 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53665.029031 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53665.029031 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -253,14 +253,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4478 system.cpu.dcache.demand_mshr_misses::total 4478 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75080000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75080000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151544000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 151544000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226624000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 226624000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226624000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 226624000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75302000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75302000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151576000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 151576000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226878000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 226878000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226878000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 226878000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000017 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -269,28 +269,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46749.688667 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52766.016713 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46887.920299 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46887.920299 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52777.158774 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52777.158774 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50665.029031 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50665.029031 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50665.029031 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50665.029031 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3487.701804 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3487.655618 # Cycle average of tags in use system.cpu.l2cache.total_refs 13310 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 4882 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.726342 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 341.613277 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2408.384377 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 737.704150 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 341.607182 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2408.352970 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 737.695465 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.073498 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.073497 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.106436 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.106435 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits |