diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
| commit | 25e1b1c1f5f4e0ad3976c88998161700135f4aae (patch) | |
| tree | 36e668b99a36c3dfcfefc157d7bd6b102b8f8af6 /tests/long/se/30.eon/ref | |
| parent | 7e711c98f8fcd949b9430bbf243d60348d0ef28b (diff) | |
| download | gem5-25e1b1c1f5f4e0ad3976c88998161700135f4aae.tar.xz | |
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
Diffstat (limited to 'tests/long/se/30.eon/ref')
6 files changed, 2335 insertions, 2261 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index 5e6582f7a..1a7177e69 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.226051 # Number of seconds simulated -sim_ticks 226051212500 # Number of ticks simulated -final_tick 226051212500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.226045 # Number of seconds simulated +sim_ticks 226044973500 # Number of ticks simulated +final_tick 226044973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 313509 # Simulator instruction rate (inst/s) -host_op_rate 313509 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 177766322 # Simulator tick rate (ticks/s) -host_mem_usage 302576 # Number of bytes of host memory used -host_seconds 1271.62 # Real time elapsed on the host +host_inst_rate 304016 # Simulator instruction rate (inst/s) +host_op_rate 304016 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 172378586 # Simulator tick rate (ticks/s) +host_mem_usage 302856 # Number of bytes of host memory used +host_seconds 1311.33 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 249344 # Nu system.physmem.num_reads::cpu.inst 3896 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory system.physmem.num_reads::total 7874 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1103042 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1126258 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2229300 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1103042 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1103042 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1103042 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1126258 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2229300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1103073 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1126289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2229362 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1103073 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1103073 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1103073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1126289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2229362 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7874 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7874 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 226051111000 # Total gap between requests +system.physmem.totGap 226044886000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6818 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 82 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6812 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 977 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1564 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 321.964194 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 193.457187 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.645688 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 541 34.59% 34.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 357 22.83% 57.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 194 12.40% 69.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 101 6.46% 76.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 65 4.16% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 55 3.52% 83.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 35 2.24% 86.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 34 2.17% 88.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 182 11.64% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1564 # Bytes accessed per row activation -system.physmem.totQLat 54215500 # Total ticks spent queuing -system.physmem.totMemAccLat 201853000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1551 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 323.878788 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 193.961760 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.450478 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 540 34.82% 34.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 341 21.99% 56.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 198 12.77% 69.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 105 6.77% 76.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 68 4.38% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 43 2.77% 83.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 33 2.13% 85.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 36 2.32% 87.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 187 12.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1551 # Bytes accessed per row activation +system.physmem.totQLat 53691750 # Total ticks spent queuing +system.physmem.totMemAccLat 201329250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 39370000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6885.38 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6818.87 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25635.38 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25568.87 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.23 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.23 # Average system read bandwidth in MiByte/s @@ -216,70 +216,70 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6308 # Number of row buffer hits during reads +system.physmem.readRowHits 6316 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.11 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.21 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28708548.51 # Average gap between requests -system.physmem.pageHitRate 80.11 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6872040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3749625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 34327800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 28707757.94 # Average gap between requests +system.physmem.pageHitRate 80.21 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6811560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3716625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 34210800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14764513920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5850636750 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 130498264500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 151158364635 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.692398 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 217093450250 # Time in different power states -system.physmem_0.memoryStateTime::REF 7548320000 # Time in different power states +system.physmem_0.refreshEnergy 14764005360 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5854324365 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 130490358000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 151153426710 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.693587 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 217080502500 # Time in different power states +system.physmem_0.memoryStateTime::REF 7548060000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1408913500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1414335000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4951800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2701875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 27042600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 4914000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2681250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 27011400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14764513920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5592917520 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 130724334000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 151116461715 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.507029 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 217471574500 # Time in different power states -system.physmem_1.memoryStateTime::REF 7548320000 # Time in different power states +system.physmem_1.refreshEnergy 14764005360 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5569701705 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 130740027000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 151108340715 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.494129 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 217498306250 # Time in different power states +system.physmem_1.memoryStateTime::REF 7548060000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1030789250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 997097750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 46270925 # Number of BP lookups -system.cpu.branchPred.condPredicted 26727379 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1017826 # Number of conditional branches incorrect +system.cpu.branchPred.lookups 46270920 # Number of BP lookups +system.cpu.branchPred.condPredicted 26727376 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1017825 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 25620092 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21360644 # Number of BTB hits +system.cpu.branchPred.BTBHits 21360645 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.374580 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 8341960 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 83.374584 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 8341957 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 95612151 # DTB read hits +system.cpu.dtb.read_hits 95612152 # DTB read hits system.cpu.dtb.read_misses 116 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 95612267 # DTB read accesses -system.cpu.dtb.write_hits 73605971 # DTB write hits +system.cpu.dtb.read_accesses 95612268 # DTB read accesses +system.cpu.dtb.write_hits 73605970 # DTB write hits system.cpu.dtb.write_misses 858 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73606829 # DTB write accesses +system.cpu.dtb.write_accesses 73606828 # DTB write accesses system.cpu.dtb.data_hits 169218122 # DTB hits system.cpu.dtb.data_misses 974 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 169219096 # DTB accesses -system.cpu.itb.fetch_hits 98739643 # ITB hits +system.cpu.itb.fetch_hits 98739640 # ITB hits system.cpu.itb.fetch_misses 1232 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 98740875 # ITB accesses +system.cpu.itb.fetch_accesses 98740872 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,67 +293,67 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 452102425 # number of cpu cycles simulated +system.cpu.numCycles 452089947 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664665 # Number of instructions committed system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4488157 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 4488161 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.134042 # CPI: cycles per instruction -system.cpu.ipc 0.881802 # IPC: instructions per cycle -system.cpu.tickCycles 448265843 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3836582 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.134011 # CPI: cycles per instruction +system.cpu.ipc 0.881826 # IPC: instructions per cycle +system.cpu.tickCycles 448265885 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3824062 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.681680 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168032891 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3291.715048 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168032888 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40344.031453 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40344.030732 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3291.681680 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803633 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803633 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3291.715048 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803641 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803641 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336084169 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336084169 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 94518092 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94518092 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73514799 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73514799 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168032891 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168032891 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168032891 # number of overall hits -system.cpu.dcache.overall_hits::total 168032891 # number of overall hits +system.cpu.dcache.tags.tag_accesses 336084171 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336084171 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 94518093 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94518093 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73514795 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73514795 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168032888 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168032888 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168032888 # number of overall hits +system.cpu.dcache.overall_hits::total 168032888 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1180 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1180 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5931 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5931 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 7111 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7111 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7111 # number of overall misses -system.cpu.dcache.overall_misses::total 7111 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88098000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88098000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 432683750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 432683750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 520781750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 520781750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 520781750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 520781750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 94519272 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94519272 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 5935 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5935 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 7115 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7115 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7115 # number of overall misses +system.cpu.dcache.overall_misses::total 7115 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 87916000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 87916000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 428863500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 428863500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 516779500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 516779500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 516779500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 516779500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 94519273 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94519273 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168040002 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168040002 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168040002 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168040002 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168040003 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168040003 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168040003 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168040003 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000012 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses @@ -362,14 +362,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74659.322034 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 74659.322034 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72952.916877 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72952.916877 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73236.077907 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73236.077907 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73236.077907 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73236.077907 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74505.084746 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 74505.084746 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72260.067397 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 72260.067397 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72632.396346 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72632.396346 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72632.396346 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72632.396346 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,12 +382,12 @@ system.cpu.dcache.writebacks::writebacks 654 # nu system.cpu.dcache.writebacks::total 654 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 211 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2735 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2735 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2946 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2946 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2946 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2946 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2739 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2739 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2950 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2950 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2950 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2950 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses @@ -396,14 +396,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4165 system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 69978250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 69978250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 238524000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 238524000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 308502250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 308502250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 308502250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 308502250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 71088500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 71088500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 239432500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 239432500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 310521000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 310521000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 310521000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 310521000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -412,68 +412,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72216.976264 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72216.976264 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74632.040050 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74632.040050 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74070.168067 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74070.168067 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74070.168067 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74070.168067 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73362.745098 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73362.745098 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74916.301627 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74916.301627 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74554.861945 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74554.861945 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74554.861945 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74554.861945 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3197 # number of replacements -system.cpu.icache.tags.tagsinuse 1918.668517 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 98734468 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1918.682192 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 98734465 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 5175 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19079.124251 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 19079.123671 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1918.668517 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.936850 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.936850 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1918.682192 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.936857 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.936857 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 397 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1281 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 197484461 # Number of tag accesses -system.cpu.icache.tags.data_accesses 197484461 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 98734468 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 98734468 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 98734468 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 98734468 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 98734468 # number of overall hits -system.cpu.icache.overall_hits::total 98734468 # number of overall hits +system.cpu.icache.tags.tag_accesses 197484455 # Number of tag accesses +system.cpu.icache.tags.data_accesses 197484455 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 98734465 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 98734465 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 98734465 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 98734465 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 98734465 # number of overall hits +system.cpu.icache.overall_hits::total 98734465 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 5175 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 5175 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 5175 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 5175 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5175 # number of overall misses system.cpu.icache.overall_misses::total 5175 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 322926000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 322926000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 322926000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 322926000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 322926000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 322926000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 98739643 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 98739643 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 98739643 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 98739643 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 98739643 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 98739643 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 319209000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 319209000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 319209000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 319209000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 319209000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 319209000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 98739640 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 98739640 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 98739640 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 98739640 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 98739640 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 98739640 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62401.159420 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62401.159420 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62401.159420 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62401.159420 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62401.159420 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62401.159420 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61682.898551 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61682.898551 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61682.898551 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61682.898551 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61682.898551 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61682.898551 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -488,116 +488,122 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 5175 system.cpu.icache.demand_mshr_misses::total 5175 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 5175 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 5175 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 313513500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 313513500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 313513500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 313513500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 313513500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 313513500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 314034000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 314034000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 314034000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 314034000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 314034000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 314034000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60582.318841 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60582.318841 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60582.318841 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60582.318841 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60582.318841 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60582.318841 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60682.898551 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60682.898551 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60682.898551 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60682.898551 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60682.898551 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60682.898551 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4426.539250 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1494 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 4426.586364 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4808 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5274 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.283276 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.911642 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 373.086855 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.473471 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 641.978924 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 373.093241 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.507533 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 641.985590 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011386 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104110 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104111 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.019592 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.135087 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.135089 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 5274 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 612 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4443 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160950 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 88424 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 88424 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1279 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 126 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1405 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 114936 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 114936 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 654 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 654 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 61 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 61 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1279 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1279 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 126 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 126 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 1279 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 187 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1466 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1279 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 187 # number of overall hits system.cpu.l2cache.overall_hits::total 1466 # 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number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 302340250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 597248750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 5175 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 967 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 6142 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 234115500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 234115500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 292841000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 292841000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 68160500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 68160500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 292841000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 302276000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 595117000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 292841000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 302276000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 595117000 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 654 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 654 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 3198 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 3198 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5175 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 5175 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 967 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 967 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 5175 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4165 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 9340 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 5175 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4165 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9340 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.752850 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.869700 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.771247 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.980926 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.980926 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.752850 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.752850 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.869700 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.869700 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.752850 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.955102 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.843041 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.752850 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955102 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.843041 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75695.200205 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80302.318668 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 76513.141229 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74850.494103 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74850.494103 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75695.200205 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76003.079437 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75850.742951 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75695.200205 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76003.079437 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75850.742951 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74630.379343 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74630.379343 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75164.527721 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75164.527721 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81046.967895 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81046.967895 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75164.527721 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75986.928105 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75580.010160 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75164.527721 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75986.928105 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75580.010160 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -606,84 +612,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3896 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 841 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4737 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3137 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 3137 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3896 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3896 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 841 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 841 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 3896 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 3978 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 7874 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3896 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3978 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7874 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 246135500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56978250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 303113750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 195592000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 195592000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 246135500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 252570250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 498705750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 246135500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 252570250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 498705750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.752850 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771247 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 202745500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 202745500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 253881000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 253881000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59750500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59750500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 253881000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 262496000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 516377000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 253881000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 262496000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 516377000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.752850 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.752850 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.869700 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.752850 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.843041 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.752850 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.843041 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63176.463039 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67750.594530 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63988.547604 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62350.015939 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62350.015939 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63176.463039 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63491.767220 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63335.756922 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63176.463039 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63491.767220 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63335.756922 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64630.379343 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64630.379343 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65164.527721 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65164.527721 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71046.967895 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71046.967895 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65164.527721 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65986.928105 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65580.010160 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65164.527721 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65986.928105 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65580.010160 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 6142 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 6142 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 3314 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10350 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8984 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 19334 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 5175 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 967 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13547 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9101 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22648 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 331200 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 639616 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 9994 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 13308 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 9994 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 13308 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 9994 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5651000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 13308 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7308000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8587500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7762500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7035750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6247999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 4737 # Transaction distribution system.membus.trans_dist::ReadResp 4737 # Transaction distribution system.membus.trans_dist::ReadExReq 3137 # Transaction distribution system.membus.trans_dist::ReadExResp 3137 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4737 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15748 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 15748 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 503936 # Cumulative packet size per connected master and slave (bytes) @@ -699,9 +711,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7874 # Request fanout histogram -system.membus.reqLayer0.occupancy 9179500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9183500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 41811750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 41813250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 1cb945d89..be9d713b1 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.069793 # Number of seconds simulated -sim_ticks 69793219500 # Number of ticks simulated -final_tick 69793219500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.069809 # Number of seconds simulated +sim_ticks 69809049000 # Number of ticks simulated +final_tick 69809049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 237836 # Simulator instruction rate (inst/s) -host_op_rate 237836 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44197170 # Simulator tick rate (ticks/s) -host_mem_usage 232228 # Number of bytes of host memory used -host_seconds 1579.13 # Real time elapsed on the host +host_inst_rate 246384 # Simulator instruction rate (inst/s) +host_op_rate 246384 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45796096 # Simulator tick rate (ticks/s) +host_mem_usage 304152 # Number of bytes of host memory used +host_seconds 1524.35 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 221440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255808 # Number of bytes read from this memory -system.physmem.bytes_read::total 477248 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221440 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3460 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3997 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7457 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3172801 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3665227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6838028 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3172801 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3172801 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3172801 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3665227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6838028 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7457 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 221504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255680 # Number of bytes read from this memory +system.physmem.bytes_read::total 477184 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221504 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3461 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3995 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7456 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 3172998 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3662562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6835561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3172998 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3172998 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3172998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3662562 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6835561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7456 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7457 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7456 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 477248 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 477184 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 477248 # Total read bytes from the system interface side +system.physmem.bytesReadSys 477184 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 527 # Per bank write bursts -system.physmem.perBankRdBursts::1 657 # Per bank write bursts -system.physmem.perBankRdBursts::2 455 # Per bank write bursts -system.physmem.perBankRdBursts::3 602 # Per bank write bursts +system.physmem.perBankRdBursts::1 655 # Per bank write bursts +system.physmem.perBankRdBursts::2 454 # Per bank write bursts +system.physmem.perBankRdBursts::3 600 # Per bank write bursts system.physmem.perBankRdBursts::4 446 # Per bank write bursts -system.physmem.perBankRdBursts::5 454 # Per bank write bursts +system.physmem.perBankRdBursts::5 455 # Per bank write bursts system.physmem.perBankRdBursts::6 515 # Per bank write bursts -system.physmem.perBankRdBursts::7 522 # Per bank write bursts -system.physmem.perBankRdBursts::8 438 # Per bank write bursts +system.physmem.perBankRdBursts::7 525 # Per bank write bursts +system.physmem.perBankRdBursts::8 439 # Per bank write bursts system.physmem.perBankRdBursts::9 407 # Per bank write bursts -system.physmem.perBankRdBursts::10 339 # Per bank write bursts +system.physmem.perBankRdBursts::10 338 # Per bank write bursts system.physmem.perBankRdBursts::11 305 # Per bank write bursts system.physmem.perBankRdBursts::12 414 # Per bank write bursts system.physmem.perBankRdBursts::13 542 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 69793123000 # Total gap between requests +system.physmem.totGap 69808953500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7457 # Read request sizes (log2) +system.physmem.readPktSize::6 7456 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4245 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 898 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4273 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1892 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 323 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1360 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 348.047059 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 208.039838 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 346.646558 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 428 31.47% 31.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 327 24.04% 55.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 157 11.54% 67.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 92 6.76% 73.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 56 4.12% 77.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 39 2.87% 80.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 33 2.43% 83.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 25 1.84% 85.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 203 14.93% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1360 # Bytes accessed per row activation -system.physmem.totQLat 67335750 # Total ticks spent queuing -system.physmem.totMemAccLat 207154500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37285000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9029.87 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1355 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 349.142435 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 207.457712 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 347.186854 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 436 32.18% 32.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 321 23.69% 55.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 135 9.96% 65.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 103 7.60% 73.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 56 4.13% 77.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 42 3.10% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 37 2.73% 83.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 28 2.07% 85.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 197 14.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1355 # Bytes accessed per row activation +system.physmem.totQLat 63176250 # Total ticks spent queuing +system.physmem.totMemAccLat 202976250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37280000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8473.21 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27779.87 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27223.21 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.84 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.84 # Average system read bandwidth in MiByte/s @@ -214,72 +214,72 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6086 # Number of row buffer hits during reads +system.physmem.readRowHits 6090 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.68 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9359410.35 # Average gap between requests -system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined +system.physmem.avgGap 9362788.83 # Average gap between requests +system.physmem.pageHitRate 81.68 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 5828760 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 3180375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 32377800 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 32370000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4558223280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2111779035 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 40020613500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 46732002750 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.624038 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 66577889000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2330380000 # Time in different power states +system.physmem_0.refreshEnergy 4559240400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2097349200 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 40042614750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 46740583485 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.597578 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 66614495250 # Time in different power states +system.physmem_0.memoryStateTime::REF 2330900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 882777000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 861488750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4430160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2417250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 25272000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 4399920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2400750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 25256400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4558223280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2013356565 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 40106949000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 46710648255 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.318049 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 66719394750 # Time in different power states -system.physmem_1.memoryStateTime::REF 2330380000 # Time in different power states +system.physmem_1.refreshEnergy 4559240400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1988059680 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 40138482750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 46717839900 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.271757 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 66771998750 # Time in different power states +system.physmem_1.memoryStateTime::REF 2330900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 738657750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 701106250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 51259743 # Number of BP lookups -system.cpu.branchPred.condPredicted 29683169 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1233682 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26552604 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23664767 # Number of BTB hits +system.cpu.branchPred.lookups 51296431 # Number of BP lookups +system.cpu.branchPred.condPredicted 29722668 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1234399 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 27069453 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23684308 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.124091 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9366329 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 317 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 87.494594 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9353372 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 312 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 103795078 # DTB read hits -system.cpu.dtb.read_misses 91880 # DTB read misses -system.cpu.dtb.read_acv 49322 # DTB read access violations -system.cpu.dtb.read_accesses 103886958 # DTB read accesses -system.cpu.dtb.write_hits 79431295 # DTB write hits -system.cpu.dtb.write_misses 1540 # DTB write misses +system.cpu.dtb.read_hits 103786850 # DTB read hits +system.cpu.dtb.read_misses 91978 # DTB read misses +system.cpu.dtb.read_acv 49358 # DTB read access violations +system.cpu.dtb.read_accesses 103878828 # DTB read accesses +system.cpu.dtb.write_hits 79421845 # DTB write hits +system.cpu.dtb.write_misses 1562 # DTB write misses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 79432835 # DTB write accesses -system.cpu.dtb.data_hits 183226373 # DTB hits -system.cpu.dtb.data_misses 93420 # DTB misses -system.cpu.dtb.data_acv 49324 # DTB access violations -system.cpu.dtb.data_accesses 183319793 # DTB accesses -system.cpu.itb.fetch_hits 51424924 # ITB hits -system.cpu.itb.fetch_misses 367 # ITB misses +system.cpu.dtb.write_accesses 79423407 # DTB write accesses +system.cpu.dtb.data_hits 183208695 # DTB hits +system.cpu.dtb.data_misses 93540 # DTB misses +system.cpu.dtb.data_acv 49360 # DTB access violations +system.cpu.dtb.data_accesses 183302235 # DTB accesses +system.cpu.itb.fetch_hits 51432488 # ITB hits +system.cpu.itb.fetch_misses 372 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 51425291 # ITB accesses +system.cpu.itb.fetch_accesses 51432860 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,106 +293,106 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 139586442 # number of cpu cycles simulated +system.cpu.numCycles 139618100 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 52218190 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 457878359 # Number of instructions fetch has processed -system.cpu.fetch.Branches 51259743 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33031096 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 85762697 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2573496 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 52215637 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 458041697 # Number of instructions fetch has processed +system.cpu.fetch.Branches 51296431 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33037680 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 85803922 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2575582 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 172 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 13442 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 10 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 51424924 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 558112 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 139281263 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.287437 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.344389 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.MiscStallCycles 177 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 13927 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 49 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 51432488 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 569689 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 139321507 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.287660 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.344182 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 58400466 41.93% 41.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4519538 3.24% 45.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 7300185 5.24% 50.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5568881 4.00% 54.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11993718 8.61% 63.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 8035210 5.77% 68.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5954127 4.27% 73.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1896980 1.36% 74.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35612158 25.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58400173 41.92% 41.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4522566 3.25% 45.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 7306043 5.24% 50.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5576459 4.00% 54.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 12017776 8.63% 63.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 8032548 5.77% 68.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5948759 4.27% 73.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1886194 1.35% 74.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35630989 25.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 139281263 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.367226 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.280250 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45296559 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16238717 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 71951122 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4512320 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1282545 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9579038 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4257 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 452073358 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 14179 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1282545 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 47196926 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5664651 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 519192 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 74460720 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10157229 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 448418638 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 439172 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2532304 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2861217 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 3565763 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 292805975 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 590541853 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 420605547 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 169936305 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 139321507 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.367405 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.280676 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45279858 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16277373 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 71952167 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4528520 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1283589 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9590263 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4245 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 452242919 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 14142 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1283589 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 47190225 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5719256 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 519758 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 74463142 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 10145537 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 448534058 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 439648 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2541243 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2902301 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 3500431 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 292850852 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 590664412 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 420646005 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 170018406 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33273646 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 37923 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 33318523 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 37911 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 320 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 15988914 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 106425467 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 81691000 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12462225 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9670397 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 415046688 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 308 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 407272286 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 487219 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 39472187 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 18379010 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 93 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 139281263 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.924100 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.223091 # Number of insts issued each cycle +system.cpu.rename.skidInsts 16086321 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 106433302 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 81699514 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12490023 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9782021 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 415154479 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 307 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 407277518 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 483889 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 39579977 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 18549388 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 92 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 139321507 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.923293 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.222373 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24058662 17.27% 17.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19633951 14.10% 31.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22674806 16.28% 47.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18925755 13.59% 61.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 19544360 14.03% 75.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14234748 10.22% 85.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9653364 6.93% 92.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6204842 4.45% 96.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4350775 3.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24043039 17.26% 17.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19688824 14.13% 31.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22672553 16.27% 47.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18939258 13.59% 61.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 19545668 14.03% 75.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14219061 10.21% 85.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9684319 6.95% 92.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6188357 4.44% 96.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4340428 3.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 139281263 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 139321507 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 264805 1.33% 1.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 265122 1.33% 1.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.00% 1.33% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 1.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 148480 0.74% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 91560 0.46% 2.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 2226 0.01% 2.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 3500111 17.53% 20.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1672568 8.38% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 151057 0.76% 2.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 93335 0.47% 2.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 3062 0.02% 2.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 3506383 17.53% 20.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1668666 8.34% 28.44% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.44% # attempts to use FU when none available @@ -414,118 +414,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.44% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9323721 46.69% 75.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4965817 24.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9341831 46.71% 75.16% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4968318 24.84% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 153389569 37.66% 37.67% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2128191 0.52% 38.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 153385991 37.66% 37.67% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2128232 0.52% 38.19% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 37431648 9.19% 47.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7537641 1.85% 49.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2804878 0.69% 49.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16758896 4.11% 54.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1606846 0.39% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 105464958 25.90% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 80116078 19.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 37448194 9.19% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7543709 1.85% 49.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2805732 0.69% 49.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16759263 4.11% 54.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1610357 0.40% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 105461195 25.89% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 80101264 19.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 407272286 # Type of FU issued -system.cpu.iq.rate 2.917707 # Inst issue rate -system.cpu.iq.fu_busy_cnt 19969288 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.049032 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 626696170 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 266819247 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237458259 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 347586172 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 187775636 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 163387975 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 246426590 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 180781403 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19964423 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 407277518 # Type of FU issued +system.cpu.iq.rate 2.917083 # Inst issue rate +system.cpu.iq.fu_busy_cnt 19997775 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.049101 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 626671270 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 266840013 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237433052 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 347686937 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 187970906 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 163426789 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 246404368 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 180837344 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19931279 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 11670980 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 165408 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 76048 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8170271 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 11678815 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 164981 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 76480 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8178785 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 382447 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3767 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 381276 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3827 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1282545 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4525606 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 90420 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 440059104 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 152527 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 106425467 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 81691000 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 308 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7009 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 82356 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 76048 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1000879 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 421168 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1422047 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 403473304 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 103936308 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3798982 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1283589 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4537578 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 127300 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 440164979 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 164208 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 106433302 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 81699514 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 307 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6586 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 117247 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 76480 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1004792 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 416739 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1421531 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 403496390 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 103928218 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3781128 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 25012108 # number of nop insts executed -system.cpu.iew.exec_refs 183369178 # number of memory reference insts executed -system.cpu.iew.exec_branches 46997600 # Number of branches executed -system.cpu.iew.exec_stores 79432870 # Number of stores executed -system.cpu.iew.exec_rate 2.890491 # Inst execution rate -system.cpu.iew.wb_sent 401684713 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 400846234 # cumulative count of insts written-back -system.cpu.iew.wb_producers 198095133 # num instructions producing a value -system.cpu.iew.wb_consumers 284050882 # num instructions consuming a value +system.cpu.iew.exec_nop 25010193 # number of nop insts executed +system.cpu.iew.exec_refs 183351660 # number of memory reference insts executed +system.cpu.iew.exec_branches 47000418 # Number of branches executed +system.cpu.iew.exec_stores 79423442 # Number of stores executed +system.cpu.iew.exec_rate 2.890001 # Inst execution rate +system.cpu.iew.wb_sent 401708524 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 400859841 # cumulative count of insts written-back +system.cpu.iew.wb_producers 198115569 # num instructions producing a value +system.cpu.iew.wb_consumers 284128842 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.871670 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.697393 # average fanout of values written-back +system.cpu.iew.wb_rate 2.871117 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.697274 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 41395670 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 41501718 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1229479 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 133482933 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.986633 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.212859 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1230197 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 133512631 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.985969 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.212275 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 48683097 36.47% 36.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18109981 13.57% 50.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 9618460 7.21% 57.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8715508 6.53% 63.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6449297 4.83% 68.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4412968 3.31% 71.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5003390 3.75% 75.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2633066 1.97% 77.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29857166 22.37% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 48674660 36.46% 36.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18127731 13.58% 50.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 9648746 7.23% 57.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8719124 6.53% 63.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6443109 4.83% 68.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4416607 3.31% 71.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5004547 3.75% 75.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2625621 1.97% 77.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29852486 22.36% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 133482933 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 133512631 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -571,127 +571,127 @@ system.cpu.commit.op_class_0::MemWrite 73520729 18.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 398664583 # Class of committed instruction -system.cpu.commit.bw_lim_events 29857166 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 543683043 # The number of ROB reads -system.cpu.rob.rob_writes 885930772 # The number of ROB writes -system.cpu.timesIdled 3165 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 305179 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 29852486 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 543823469 # The number of ROB reads +system.cpu.rob.rob_writes 886153369 # The number of ROB writes +system.cpu.timesIdled 3159 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 296593 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.371661 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.371661 # CPI: Total CPI of All Threads -system.cpu.ipc 2.690625 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.690625 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 403591803 # number of integer regfile reads -system.cpu.int_regfile_writes 172078772 # number of integer regfile writes -system.cpu.fp_regfile_reads 157997982 # number of floating regfile reads -system.cpu.fp_regfile_writes 105636085 # number of floating regfile writes +system.cpu.cpi 0.371745 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.371745 # CPI: Total CPI of All Threads +system.cpu.ipc 2.690015 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.690015 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 403553331 # number of integer regfile reads +system.cpu.int_regfile_writes 172072539 # number of integer regfile writes +system.cpu.fp_regfile_reads 158043337 # number of floating regfile reads +system.cpu.fp_regfile_writes 105673333 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 806 # number of replacements -system.cpu.dcache.tags.tagsinuse 3297.136243 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 156944357 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4209 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37287.801616 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 795 # number of replacements +system.cpu.dcache.tags.tagsinuse 3296.035456 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 156970312 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4197 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37400.598523 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3297.136243 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.804965 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.804965 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3403 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 3296.035456 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.804696 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.804696 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3402 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 3119 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.830811 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 313935887 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 313935887 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 83443297 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 83443297 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501051 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501051 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 156944348 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 156944348 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 156944348 # number of overall hits -system.cpu.dcache.overall_hits::total 156944348 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1804 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1804 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19678 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19678 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21482 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21482 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21482 # number of overall misses -system.cpu.dcache.overall_misses::total 21482 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 122640500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 122640500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1228413709 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1228413709 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1351054209 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1351054209 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1351054209 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1351054209 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 83445101 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 83445101 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.830566 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 313987939 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 313987939 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 83469338 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 83469338 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73500964 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73500964 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 156970302 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 156970302 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 156970302 # number of overall hits +system.cpu.dcache.overall_hits::total 156970302 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1794 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1794 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19765 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19765 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21559 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21559 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21559 # number of overall misses +system.cpu.dcache.overall_misses::total 21559 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 128871000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 128871000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1185279954 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1185279954 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1314150954 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1314150954 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1314150954 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1314150954 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 83471132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 83471132 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 9 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 9 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 156965830 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 156965830 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 156965830 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 156965830 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000268 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000268 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 156991861 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 156991861 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 156991861 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 156991861 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000137 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000137 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000137 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000137 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67982.538803 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67982.538803 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62425.739862 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62425.739862 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62892.384741 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62892.384741 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62892.384741 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62892.384741 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 51314 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 108 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 737 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71834.448161 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71834.448161 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59968.629092 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59968.629092 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60956.025511 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60956.025511 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60956.025511 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60956.025511 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 49421 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 88 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 747 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.625509 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 108 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 66.159304 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 88 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 682 # number of writebacks -system.cpu.dcache.writebacks::total 682 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 803 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 803 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16470 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16470 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17273 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17273 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17273 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17273 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1001 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1001 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3208 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3208 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4209 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4209 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4209 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4209 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 72824500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 72824500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 253362750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 253362750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 326187250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 326187250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 326187250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 326187250 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 671 # number of writebacks +system.cpu.dcache.writebacks::total 671 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 799 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 799 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16563 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16563 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17362 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17362 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17362 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17362 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 995 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 995 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4197 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4197 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4197 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4197 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76593500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 76593500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 246844000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 246844000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 323437500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 323437500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 323437500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 323437500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -700,198 +700,204 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72751.748252 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72751.748252 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78978.413342 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78978.413342 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77497.564742 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77497.564742 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77497.564742 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77497.564742 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76978.391960 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76978.391960 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77090.568395 # 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Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2157 # number of replacements +system.cpu.icache.tags.tagsinuse 1832.216020 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 51426803 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4084 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12592.263222 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1831.206745 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.894144 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.894144 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1832.216020 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894637 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894637 # 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miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.847453 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.868342 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.868342 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.847453 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.951870 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.900374 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.847453 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.951870 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.900374 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77036.889173 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77036.889173 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75867.090436 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75867.090436 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85225.115741 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85225.115741 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75867.090436 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78807.759700 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77442.730687 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75867.090436 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78807.759700 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77442.730687 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -900,102 +906,108 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3460 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 867 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4327 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3130 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3130 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3460 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3997 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7457 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3460 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3997 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7457 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 220205500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 59518000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 279723500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 210540750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 210540750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 220205500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 270058750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 490264250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 220205500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 270058750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 490264250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.846587 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.866134 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.850432 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.975686 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.975686 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.846587 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.949632 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.898867 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.846587 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.949632 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.898867 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63643.208092 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68648.212226 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64646.059626 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67265.415335 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67265.415335 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63643.208092 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67565.361521 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65745.507577 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63643.208092 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67565.361521 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65745.507577 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3131 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3131 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3461 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3461 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 864 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 864 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3461 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3995 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7456 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3461 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3995 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7456 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 209892500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 209892500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 227966000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 227966000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 64994500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 64994500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 227966000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 274887000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 502853000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 227966000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 274887000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 502853000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.977826 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.977826 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.847453 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.847453 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.868342 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.868342 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.847453 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.951870 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.900374 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.847453 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.951870 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.900374 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67036.889173 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67036.889173 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65867.090436 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65867.090436 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75225.115741 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75225.115741 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65867.090436 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68807.759700 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67442.730687 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65867.090436 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68807.759700 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67442.730687 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 5088 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5088 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 682 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3208 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3208 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8174 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9100 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 17274 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 313024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 574592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadResp 5079 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 671 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2281 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3202 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3202 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4084 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 995 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10325 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9189 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 19514 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 572928 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 8978 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 11233 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 8978 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11233 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8978 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5171000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11233 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 6287500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6830250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6126000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6882750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6295500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 4327 # Transaction distribution -system.membus.trans_dist::ReadResp 4327 # Transaction distribution -system.membus.trans_dist::ReadExReq 3130 # Transaction distribution -system.membus.trans_dist::ReadExResp 3130 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14914 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14914 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477248 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 477248 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 4325 # Transaction distribution +system.membus.trans_dist::ReadExReq 3131 # Transaction distribution +system.membus.trans_dist::ReadExResp 3131 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4325 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14912 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477184 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 477184 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7457 # Request fanout histogram +system.membus.snoop_fanout::samples 7456 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7457 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7456 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7457 # Request fanout histogram -system.membus.reqLayer0.occupancy 9341500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7456 # Request fanout histogram +system.membus.reqLayer0.occupancy 9215500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 39310250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 39331250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 97440304f..8c86953a0 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.567335 # Number of seconds simulated -sim_ticks 567335093500 # Number of ticks simulated -final_tick 567335093500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 567335097500 # Number of ticks simulated +final_tick 567335097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1360508 # Simulator instruction rate (inst/s) -host_op_rate 1360508 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1936123010 # Simulator tick rate (ticks/s) -host_mem_usage 299124 # Number of bytes of host memory used -host_seconds 293.03 # Real time elapsed on the host +host_inst_rate 1293186 # Simulator instruction rate (inst/s) +host_op_rate 1293186 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1840317995 # Simulator tick rate (ticks/s) +host_mem_usage 300812 # Number of bytes of host memory used +host_seconds 308.28 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -63,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 1134670187 # number of cpu cycles simulated +system.cpu.numCycles 1134670195 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664609 # Number of instructions committed @@ -82,7 +82,7 @@ system.cpu.num_mem_refs 168275276 # nu system.cpu.num_load_insts 94754511 # Number of load instructions system.cpu.num_store_insts 73520765 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1134670187 # Number of busy cycles +system.cpu.num_busy_cycles 1134670195 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 44587535 # Number of branches fetched @@ -122,12 +122,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 398664665 # Class of executed instruction system.cpu.dcache.tags.replacements 764 # number of replacements -system.cpu.dcache.tags.tagsinuse 3288.930570 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3288.930558 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3288.930570 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 3288.930558 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.802962 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id @@ -205,14 +205,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45659000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 45659000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 168787000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 168787000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 214446000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 214446000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 214446000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 214446000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 46134000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 46134000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 170388000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 170388000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 216522000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 216522000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 216522000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 216522000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -221,22 +221,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48062.105263 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48062.105263 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52712.991880 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52712.991880 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51648.843931 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51648.843931 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51648.843931 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51648.843931 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48562.105263 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48562.105263 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53212.991880 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53212.991880 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52148.843931 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52148.843931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52148.843931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52148.843931 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1769 # number of replacements -system.cpu.icache.tags.tagsinuse 1795.138960 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1795.138955 # Cycle average of tags in use system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1795.138960 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1795.138955 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.876533 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1904 # Occupied blocks per task id @@ -260,12 +260,12 @@ system.cpu.icache.demand_misses::cpu.inst 3673 # n system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses system.cpu.icache.overall_misses::total 3673 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 182359500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 182359500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 182359500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 182359500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 182359500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 182359500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 182363500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 182363500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 182363500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 182363500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 182363500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 182363500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses @@ -278,12 +278,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49648.652328 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49648.652328 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49648.652328 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49648.652328 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49648.652328 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49648.652328 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49649.741356 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49649.741356 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49649.741356 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49649.741356 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49649.741356 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49649.741356 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -298,34 +298,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3673 system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 176850000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 176850000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 176850000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 176850000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 176850000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 176850000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 178690500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 178690500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 178690500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 178690500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 178690500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 178690500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48148.652328 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48148.652328 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48148.652328 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48148.652328 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48148.652328 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48148.652328 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48649.741356 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48649.741356 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48649.741356 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48649.741356 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48649.741356 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48649.741356 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3772.485298 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 677 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3772.485272 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2561 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4566 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.148270 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.560885 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 371.540220 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.469918 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 630.475159 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 371.540218 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.469899 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 630.475155 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011339 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.019241 # Average percentage of cache occupancy @@ -337,78 +337,84 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 75 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 497 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3787 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.139343 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 75560 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 75560 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 468 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 591 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 90632 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 90632 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 468 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 468 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 123 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 123 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 468 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 651 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 468 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits system.cpu.l2cache.overall_hits::total 651 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3205 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 827 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4032 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 3142 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 3142 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3205 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3205 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 827 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 827 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 3205 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 3969 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 7174 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7174 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 168263000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43417500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 211680500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 164955000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 164955000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 168263000 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 168265000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 168265000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 43417500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 43417500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 168265000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 208372500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 376635500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 168263000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 376637500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 168265000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 208372500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 376635500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 3673 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 950 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 4623 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_miss_latency::total 376637500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 3202 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 3202 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 3673 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 3673 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 950 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 950 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 3673 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 7825 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 3673 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 7825 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.872584 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870526 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.872161 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981262 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.981262 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.872584 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.872584 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.870526 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.870526 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.872584 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.916805 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916805 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.156006 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.124008 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.156006 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52500.780031 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52500.780031 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.780031 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52500.069696 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.156006 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.348481 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.780031 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52500.069696 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.348481 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -417,84 +423,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3205 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 827 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4032 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3142 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 3142 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3205 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3205 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 827 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 827 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 3205 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 3969 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 7174 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7174 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 129802500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33493500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 163296000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 127251000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 127251000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129802500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160744500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 290547000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129802500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160744500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 290547000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870526 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.872161 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133535000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133535000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 136215000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 136215000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 35147500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 35147500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 136215000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168682500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 304897500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 136215000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168682500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 304897500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981262 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.872584 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.870526 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.870526 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.916805 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.916805 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42500.780031 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42500.780031 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42500.780031 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.348481 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42500.780031 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.348481 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 4623 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1884 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 3202 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 3202 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7346 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8953 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16299 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 3673 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 950 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9115 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9068 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 18183 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 235072 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 542336 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 8474 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 10358 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 8474 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 10358 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8474 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4886000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 10358 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5828000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 5509500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6228000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 4032 # Transaction distribution system.membus.trans_dist::ReadResp 4032 # Transaction distribution system.membus.trans_dist::ReadExReq 3142 # Transaction distribution system.membus.trans_dist::ReadExResp 3142 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4032 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14348 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 14348 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes) @@ -510,9 +522,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7174 # Request fanout histogram -system.membus.reqLayer0.occupancy 7174500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 7176500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 35870500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 35872500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 572510825..454441ad4 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.216140 # Number of seconds simulated -sim_ticks 216139917000 # Number of ticks simulated -final_tick 216139917000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.216071 # Number of seconds simulated +sim_ticks 216071083000 # Number of ticks simulated +final_tick 216071083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 173188 # Simulator instruction rate (inst/s) -host_op_rate 207931 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 137097336 # Simulator tick rate (ticks/s) -host_mem_usage 323040 # Number of bytes of host memory used -host_seconds 1576.54 # Real time elapsed on the host +host_inst_rate 173126 # Simulator instruction rate (inst/s) +host_op_rate 207857 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 137004908 # Simulator tick rate (ticks/s) +host_mem_usage 323124 # Number of bytes of host memory used +host_seconds 1577.10 # Real time elapsed on the host sim_insts 273037857 # Number of instructions simulated sim_ops 327812214 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 219136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 266368 # Number of bytes read from this memory -system.physmem.bytes_read::total 485504 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219136 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3424 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 485440 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3423 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7586 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1013862 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1232387 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2246249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1013862 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1013862 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1013862 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1232387 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2246249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7586 # Number of read requests accepted +system.physmem.num_reads::total 7585 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1013889 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1232779 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2246668 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1013889 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1013889 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1013889 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1232779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2246668 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7585 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7586 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7585 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 485504 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 485440 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 485504 # Total read bytes from the system interface side +system.physmem.bytesReadSys 485440 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -56,7 +56,7 @@ system.physmem.perBankRdBursts::11 428 # Pe system.physmem.perBankRdBursts::12 553 # Per bank write bursts system.physmem.perBankRdBursts::13 706 # Per bank write bursts system.physmem.perBankRdBursts::14 638 # Per bank write bursts -system.physmem.perBankRdBursts::15 541 # Per bank write bursts +system.physmem.perBankRdBursts::15 540 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 216139680500 # Total gap between requests +system.physmem.totGap 216070847500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7586 # Read request sizes (log2) +system.physmem.readPktSize::6 7585 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6624 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 901 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1523 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 318.319107 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.795582 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.243204 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 551 36.18% 36.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 346 22.72% 58.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 176 11.56% 70.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 81 5.32% 75.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 75 4.92% 80.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 50 3.28% 83.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 32 2.10% 86.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 28 1.84% 87.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 184 12.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1523 # Bytes accessed per row activation -system.physmem.totQLat 53007250 # Total ticks spent queuing -system.physmem.totMemAccLat 195244750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37930000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6987.51 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1505 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 321.445847 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.975712 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.801659 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 552 36.68% 36.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 337 22.39% 59.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 156 10.37% 69.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 81 5.38% 74.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 75 4.98% 79.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 59 3.92% 83.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 41 2.72% 86.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 29 1.93% 88.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 175 11.63% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1505 # Bytes accessed per row activation +system.physmem.totQLat 52368250 # Total ticks spent queuing +system.physmem.totMemAccLat 194587000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37925000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6904.19 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25737.51 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25654.19 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.25 # Average system read bandwidth in MiByte/s @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6060 # Number of row buffer hits during reads +system.physmem.readRowHits 6074 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.88 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.08 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28491916.75 # Average gap between requests -system.physmem.pageHitRate 79.88 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5004720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2730750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 30022200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 28486598.22 # Average gap between requests +system.physmem.pageHitRate 80.08 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5050080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2755500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 29959800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14117117040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5648540400 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 124728404250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 144531819360 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.699173 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 207494790250 # Time in different power states -system.physmem_0.memoryStateTime::REF 7217340000 # Time in different power states +system.physmem_0.refreshEnergy 14112540000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5672899350 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 124664991000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 144488195730 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.714152 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 207389955000 # Time in different power states +system.physmem_0.memoryStateTime::REF 7215000000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1426657250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1464485500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6509160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3551625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 29062800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 6320160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3448500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 28992600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14117117040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5781551040 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 124611728250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 144549519915 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.781068 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 207298156250 # Time in different power states -system.physmem_1.memoryStateTime::REF 7217340000 # Time in different power states +system.physmem_1.refreshEnergy 14112540000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5762856465 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 124586081250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 144500238975 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.769890 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 207255387750 # Time in different power states +system.physmem_1.memoryStateTime::REF 7215000000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1623563250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1598323500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 33139216 # Number of BP lookups -system.cpu.branchPred.condPredicted 17107199 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1560655 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17520877 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15610870 # Number of BTB hits +system.cpu.branchPred.lookups 33111389 # Number of BP lookups +system.cpu.branchPred.condPredicted 17094855 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1552605 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17374125 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15590921 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.098679 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6611023 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 89.736439 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6603992 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,69 +377,69 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 432279834 # number of cpu cycles simulated +system.cpu.numCycles 432142166 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 273037857 # Number of instructions committed system.cpu.committedOps 327812214 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4207498 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 4177938 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.583223 # CPI: cycles per instruction -system.cpu.ipc 0.631623 # IPC: instructions per cycle -system.cpu.tickCycles 428628441 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3651393 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.582719 # CPI: cycles per instruction +system.cpu.ipc 0.631824 # IPC: instructions per cycle +system.cpu.tickCycles 428506724 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3635442 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 1354 # number of replacements -system.cpu.dcache.tags.tagsinuse 3085.737950 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168771151 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3085.759854 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168767138 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37413.245622 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37412.356019 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3085.737950 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.753354 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.753354 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3085.759854 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.753359 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.753359 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 337561379 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 337561379 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 86638362 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86638362 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82047459 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047459 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 337553367 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337553367 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86634356 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86634356 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82047452 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047452 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 63540 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 63540 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168685821 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168685821 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168749361 # number of overall hits -system.cpu.dcache.overall_hits::total 168749361 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 168681808 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168681808 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168745348 # number of overall hits +system.cpu.dcache.overall_hits::total 168745348 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 2059 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2059 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5218 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5218 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5225 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5225 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 6 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 6 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 7277 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7277 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7283 # number of overall misses -system.cpu.dcache.overall_misses::total 7283 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 136967456 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 136967456 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 400451000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 400451000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 537418456 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 537418456 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 537418456 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 537418456 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86640421 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86640421 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7284 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7284 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7290 # number of overall misses +system.cpu.dcache.overall_misses::total 7290 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 134727000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 134727000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 395694000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 395694000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 530421000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 530421000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 530421000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 530421000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86636415 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86636415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 63546 # number of SoftPFReq accesses(hits+misses) @@ -448,10 +448,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168693098 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168693098 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168756644 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168756644 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168689092 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168689092 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168752638 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168752638 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses @@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66521.348227 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66521.348227 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76744.154849 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76744.154849 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73851.649856 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73851.649856 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73790.808183 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73790.808183 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65433.220010 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 65433.220010 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75730.909091 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75730.909091 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72820.016474 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72820.016474 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72760.082305 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72760.082305 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,12 +482,12 @@ system.cpu.dcache.writebacks::writebacks 1010 # nu system.cpu.dcache.writebacks::total 1010 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2348 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2348 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2770 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2770 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2770 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2770 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2355 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2355 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2777 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2777 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2777 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2777 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1637 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1637 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses @@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4507 system.cpu.dcache.demand_mshr_misses::total 4507 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 108888792 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 108888792 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 220256750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 220256750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 320750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 320750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329145542 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 329145542 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329466292 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 329466292 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 108637000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 108637000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 220584500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 220584500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 322000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 322000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329221500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 329221500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329543500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 329543500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -518,71 +518,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66517.282834 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66517.282834 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76744.512195 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76744.512195 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80187.500000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80187.500000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73029.851786 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73029.851786 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73036.198626 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73036.198626 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66363.469762 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66363.469762 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76858.710801 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76858.710801 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80500 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73046.705125 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73046.705125 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73053.314121 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73053.314121 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 36928 # number of replacements -system.cpu.icache.tags.tagsinuse 1924.841098 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 73108223 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 38865 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1881.081256 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 36911 # number of replacements +system.cpu.icache.tags.tagsinuse 1924.852805 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 73041980 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 38848 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1880.199238 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1924.841098 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939864 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939864 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.852805 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939870 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939870 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1487 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 274 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1488 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146333043 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146333043 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 73108223 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 73108223 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 73108223 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 73108223 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 73108223 # number of overall hits -system.cpu.icache.overall_hits::total 73108223 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 38866 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 38866 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 38866 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 38866 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 38866 # number of overall misses -system.cpu.icache.overall_misses::total 38866 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 728130248 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 728130248 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 728130248 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 728130248 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 728130248 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 728130248 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 73147089 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 73147089 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 73147089 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 73147089 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 73147089 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 73147089 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000531 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000531 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000531 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000531 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000531 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000531 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18734.375753 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18734.375753 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18734.375753 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18734.375753 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18734.375753 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18734.375753 # average overall miss latency +system.cpu.icache.tags.tag_accesses 146200506 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146200506 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 73041980 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 73041980 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 73041980 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 73041980 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 73041980 # number of overall hits +system.cpu.icache.overall_hits::total 73041980 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 38849 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 38849 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 38849 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 38849 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 38849 # number of overall misses +system.cpu.icache.overall_misses::total 38849 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 726693000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 726693000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 726693000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 726693000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 726693000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 726693000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 73080829 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 73080829 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 73080829 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 73080829 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 73080829 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 73080829 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000532 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000532 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000532 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000532 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000532 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000532 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18705.578007 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18705.578007 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18705.578007 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18705.578007 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18705.578007 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18705.578007 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,123 +591,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38866 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 38866 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 38866 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 38866 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 38866 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 38866 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 668381252 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 668381252 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 668381252 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 668381252 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 668381252 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 668381252 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000531 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000531 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000531 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17197.068183 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17197.068183 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17197.068183 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17197.068183 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17197.068183 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17197.068183 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38849 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 38849 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 38849 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 38849 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 38849 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 38849 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 687845000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 687845000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 687845000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 687845000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 687845000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 687845000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000532 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000532 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000532 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000532 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000532 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000532 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17705.603748 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17705.603748 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17705.603748 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17705.603748 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17705.603748 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17705.603748 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4199.211257 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 35810 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5648 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.340297 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 4199.240994 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 58015 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5647 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.273597 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 353.787736 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.125698 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 678.297823 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 353.792548 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.144889 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 678.303557 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010797 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096653 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096654 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.020700 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.128150 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5648 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::total 0.128151 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5647 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 42 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1252 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1251 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4261 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172363 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 363614 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 363614 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 35440 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 291 # 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number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088098 # mshr miss rate for demand accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.088110 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.088110 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.797075 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.797075 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088110 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.174885 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088098 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.174931 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088110 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.174885 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62616.457360 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65311.735474 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63361.475063 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63588.735109 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63588.735109 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62616.457360 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64130.225853 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63446.974690 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62616.457360 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64130.225853 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63446.974690 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.174931 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65710.056062 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65710.056062 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65224.072451 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65224.072451 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66750.382263 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66750.382263 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65224.072451 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66037.001442 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65670.138431 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65224.072451 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66037.001442 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65670.138431 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 40507 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 40506 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 40489 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 22221 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77731 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10032 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 87763 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2487360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 38849 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1641 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 99690 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10260 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 109950 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2486272 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2840704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2839616 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 44387 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 81625 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 44387 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 81625 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 44387 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 23203500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 81625 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 41822500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 59023248 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 58272998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7574708 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6787458 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 4732 # Transaction distribution -system.membus.trans_dist::ReadResp 4732 # Transaction distribution +system.membus.trans_dist::ReadResp 4731 # Transaction distribution system.membus.trans_dist::ReadExReq 2854 # Transaction distribution system.membus.trans_dist::ReadExResp 2854 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15172 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15172 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 485504 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 4731 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15170 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15170 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 485440 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7586 # Request fanout histogram +system.membus.snoop_fanout::samples 7585 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7586 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7585 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7586 # Request fanout histogram -system.membus.reqLayer0.occupancy 8848500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7585 # Request fanout histogram +system.membus.reqLayer0.occupancy 8844500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 40266750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40248250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 94f7097ff..8a385b77d 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.112557 # Number of seconds simulated -sim_ticks 112556618500 # Number of ticks simulated -final_tick 112556618500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.112686 # Number of seconds simulated +sim_ticks 112686104500 # Number of ticks simulated +final_tick 112686104500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125639 # Simulator instruction rate (inst/s) -host_op_rate 150843 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51793233 # Simulator tick rate (ticks/s) -host_mem_usage 327772 # Number of bytes of host memory used -host_seconds 2173.19 # Real time elapsed on the host +host_inst_rate 125538 # Simulator instruction rate (inst/s) +host_op_rate 150722 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51811162 # Simulator tick rate (ticks/s) +host_mem_usage 327864 # Number of bytes of host memory used +host_seconds 2174.94 # Real time elapsed on the host sim_insts 273037220 # Number of instructions simulated sim_ops 327811602 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 187072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 117696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 162752 # Number of bytes read from this memory -system.physmem.bytes_read::total 467520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 167936 # Number of bytes read from this memory +system.physmem.bytes_read::total 467904 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 187072 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 187072 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 2923 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1839 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 2543 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7305 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1662026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1045660 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 1445957 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4153643 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1662026 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1662026 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1662026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1045660 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 1445957 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4153643 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7305 # Number of read requests accepted +system.physmem.num_reads::cpu.data 1764 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2624 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7311 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1660116 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1001863 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1490299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4152278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1660116 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1660116 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1660116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1001863 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1490299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4152278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7311 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7305 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7311 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 467520 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 467904 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 467520 # Total read bytes from the system interface side +system.physmem.bytesReadSys 467904 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -51,16 +51,16 @@ system.physmem.perBankRdBursts::2 601 # Pe system.physmem.perBankRdBursts::3 520 # Per bank write bursts system.physmem.perBankRdBursts::4 444 # Per bank write bursts system.physmem.perBankRdBursts::5 346 # Per bank write bursts -system.physmem.perBankRdBursts::6 146 # Per bank write bursts -system.physmem.perBankRdBursts::7 247 # Per bank write bursts +system.physmem.perBankRdBursts::6 153 # Per bank write bursts +system.physmem.perBankRdBursts::7 252 # Per bank write bursts system.physmem.perBankRdBursts::8 219 # Per bank write bursts system.physmem.perBankRdBursts::9 290 # Per bank write bursts system.physmem.perBankRdBursts::10 315 # Per bank write bursts system.physmem.perBankRdBursts::11 411 # Per bank write bursts -system.physmem.perBankRdBursts::12 540 # Per bank write bursts +system.physmem.perBankRdBursts::12 547 # Per bank write bursts system.physmem.perBankRdBursts::13 678 # Per bank write bursts system.physmem.perBankRdBursts::14 615 # Per bank write bursts -system.physmem.perBankRdBursts::15 555 # Per bank write bursts +system.physmem.perBankRdBursts::15 542 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 112556460000 # Total gap between requests +system.physmem.totGap 112685946000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7305 # Read request sizes (log2) +system.physmem.readPktSize::6 7311 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,22 +94,22 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4013 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1460 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 289 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 191 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 137 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 186 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3986 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 235 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 200 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 198 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 66 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -190,26 +190,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1395 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 333.121147 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 192.861490 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 347.787983 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 501 35.91% 35.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 324 23.23% 59.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 138 9.89% 69.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 72 5.16% 74.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 60 4.30% 78.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 40 2.87% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 25 1.79% 83.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 33 2.37% 85.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 202 14.48% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1395 # Bytes accessed per row activation -system.physmem.totQLat 103629565 # Total ticks spent queuing -system.physmem.totMemAccLat 240598315 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 36525000 # Total ticks spent in databus transfers -system.physmem.avgQLat 14186.11 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1367 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 340.646672 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 198.022122 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 348.529599 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 486 35.55% 35.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 298 21.80% 57.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 139 10.17% 67.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 76 5.56% 73.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 63 4.61% 77.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 51 3.73% 81.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 27 1.98% 83.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 26 1.90% 85.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 201 14.70% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1367 # Bytes accessed per row activation +system.physmem.totQLat 102208518 # Total ticks spent queuing +system.physmem.totMemAccLat 239289768 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36555000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13980.10 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32936.11 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 32730.10 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.15 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.15 # Average system read bandwidth in MiByte/s @@ -218,51 +218,51 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.37 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.49 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5900 # Number of row buffer hits during reads +system.physmem.readRowHits 5935 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.77 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.18 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 15408139.63 # Average gap between requests -system.physmem.pageHitRate 80.77 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4800600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2619375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 28509000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 15413205.58 # Average gap between requests +system.physmem.pageHitRate 81.18 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4815720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2627625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 28657200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 7351234800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3210095790 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 64714428750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 75311688315 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.136839 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 107655127862 # Time in different power states -system.physmem_0.memoryStateTime::REF 3758300000 # Time in different power states +system.physmem_0.refreshEnergy 7359880320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3231673425 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 64774920750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 75402575040 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.157389 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 107755851914 # Time in different power states +system.physmem_0.memoryStateTime::REF 3762720000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1137230638 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1164613086 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5692680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3106125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 28033200 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 5496120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2998875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 28064400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 7351234800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3321763065 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 64616466750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 75326296620 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.266714 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 107490739638 # Time in different power states -system.physmem_1.memoryStateTime::REF 3758300000 # Time in different power states +system.physmem_1.refreshEnergy 7359880320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3295137510 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 64719250500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 75410827725 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.230627 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 107661884129 # Time in different power states +system.physmem_1.memoryStateTime::REF 3762720000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1301464112 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1258279621 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 37745745 # Number of BP lookups -system.cpu.branchPred.condPredicted 20165036 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1746193 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18664433 # Number of BTB lookups -system.cpu.branchPred.BTBHits 17299757 # Number of BTB hits +system.cpu.branchPred.lookups 37742989 # Number of BP lookups +system.cpu.branchPred.condPredicted 20164516 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1746156 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18663196 # Number of BTB lookups +system.cpu.branchPred.BTBHits 17299233 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.688361 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7225644 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.691697 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7223653 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3816 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,129 +381,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 225113238 # number of cpu cycles simulated +system.cpu.numCycles 225372210 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12251417 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 334051298 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37745745 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24525401 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 210778013 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3510671 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1214 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 2374 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 89095174 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 21831 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 224788353 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.802613 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.228565 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12439138 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 334051202 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37742989 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24522886 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 210855691 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3510707 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1284 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 2593 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 89092155 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 21708 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 225054059 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.800470 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.229417 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 51103569 22.73% 22.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42898008 19.08% 41.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 30051948 13.37% 55.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 100734828 44.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 51374086 22.83% 22.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42891136 19.06% 41.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 30054592 13.35% 55.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 100734245 44.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 224788353 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.167674 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.483926 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 27670582 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63851253 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108576447 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 23069494 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1620577 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6880022 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 135197 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 363530011 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 6168132 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1620577 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 44985380 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 17900890 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 342489 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 113387887 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 46551130 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 355747905 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 2899336 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 6599141 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 195125 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7751977 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 21225499 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 2892433 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 403402217 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2533894130 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 350207887 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 194891394 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 225054059 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.167470 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.482220 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 27837229 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63912010 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108618315 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 23065911 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1620594 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6880048 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 135198 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 363546099 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6169805 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1620594 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 45200014 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 17874059 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 342377 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 113380979 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 46636036 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 355768136 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 2890465 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 6610669 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 177931 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7803674 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 21223053 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 2890533 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 403406015 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2534023592 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 350247327 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 194894263 # Number of floating rename lookups system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31172166 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 17015 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 17024 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 55319848 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 92416628 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 88482470 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1658909 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1843123 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 353235356 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28024 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 346405014 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 2300418 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 25451778 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 73600174 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 5904 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 224788353 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.541027 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.099686 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 31175964 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 17016 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 17025 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 55505783 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 92416404 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 88498336 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1661010 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1846418 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 353252226 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 28026 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 346438238 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 2301579 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 25468650 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 73725461 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 5906 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 225054059 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.539356 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.099855 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 40435382 17.99% 17.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 78271933 34.82% 52.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 61035531 27.15% 79.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34789384 15.48% 95.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9595504 4.27% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 651863 0.29% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8756 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 40665072 18.07% 18.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 78300215 34.79% 52.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 60997700 27.10% 79.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34882254 15.50% 95.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9557051 4.25% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 642945 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8822 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 224788353 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 225054059 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9471637 7.62% 7.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7328 0.01% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 257062 0.21% 7.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 126985 0.10% 7.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 92941 0.07% 8.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 68002 0.05% 8.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 719490 0.58% 8.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 316341 0.25% 8.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 682827 0.55% 9.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 53603507 43.13% 52.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 58947270 47.43% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9490410 7.63% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7314 0.01% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 255762 0.21% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 126866 0.10% 7.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 93218 0.07% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 68015 0.05% 8.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 721741 0.58% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 297231 0.24% 8.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 683043 0.55% 9.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 53642366 43.14% 52.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 58960700 47.42% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 110656004 31.94% 31.94% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148356 0.62% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 110655140 31.94% 31.94% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148362 0.62% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.56% # Type of FU issued @@ -522,93 +522,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.56% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6798499 1.96% 34.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8668326 2.50% 37.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3332485 0.96% 37.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1592467 0.46% 38.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20930113 6.04% 44.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7182308 2.07% 46.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7148959 2.06% 48.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6798396 1.96% 34.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8668155 2.50% 37.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3332481 0.96% 37.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592458 0.46% 38.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20930094 6.04% 44.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7182326 2.07% 46.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7148962 2.06% 48.63% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 91886991 26.53% 75.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 85885220 24.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 91923219 26.53% 75.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 85883359 24.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 346405014 # Type of FU issued -system.cpu.iq.rate 1.538803 # Inst issue rate -system.cpu.iq.fu_busy_cnt 124293390 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.358809 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 756692141 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 251708637 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 223263072 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 287500048 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 127016707 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 117424886 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 303165485 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 167532919 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5066153 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 346438238 # Type of FU issued +system.cpu.iq.rate 1.537183 # Inst issue rate +system.cpu.iq.fu_busy_cnt 124346666 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.358929 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 757024395 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 251740362 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 223260150 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 287554385 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 127018791 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 117424955 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 303230405 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 167554499 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5064919 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6684353 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13689 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 10190 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6106853 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6684129 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13573 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 10255 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6122719 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 154467 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 567717 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 155303 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 607776 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1620577 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2121612 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 331103 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 353264247 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 1620594 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2118849 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 332046 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 353281117 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 92416628 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 88482470 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 16991 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 8045 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 337585 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 10190 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1220609 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 439082 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1659691 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 342414524 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 90667106 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3990490 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 92416404 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 88498336 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 16993 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 8049 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 338505 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 10255 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1220656 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 439058 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1659714 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 342448377 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 90703712 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3989861 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 867 # number of nop insts executed -system.cpu.iew.exec_refs 175256113 # number of memory reference insts executed -system.cpu.iew.exec_branches 31752933 # Number of branches executed -system.cpu.iew.exec_stores 84589007 # Number of stores executed -system.cpu.iew.exec_rate 1.521077 # Inst execution rate -system.cpu.iew.wb_sent 340946411 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 340687958 # cumulative count of insts written-back -system.cpu.iew.wb_producers 153730891 # num instructions producing a value -system.cpu.iew.wb_consumers 266895127 # num instructions consuming a value +system.cpu.iew.exec_nop 865 # number of nop insts executed +system.cpu.iew.exec_refs 175291126 # number of memory reference insts executed +system.cpu.iew.exec_branches 31752707 # Number of branches executed +system.cpu.iew.exec_stores 84587414 # Number of stores executed +system.cpu.iew.exec_rate 1.519479 # Inst execution rate +system.cpu.iew.wb_sent 340943800 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 340685105 # cumulative count of insts written-back +system.cpu.iew.wb_producers 153662327 # num instructions producing a value +system.cpu.iew.wb_consumers 266738216 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.513407 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.575997 # average fanout of values written-back +system.cpu.iew.wb_rate 1.511655 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.576079 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23077429 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23082519 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1611435 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 221063225 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.482889 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.052142 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1611397 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 221328864 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.481109 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.050764 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 87359166 39.52% 39.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 70369846 31.83% 71.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 20804571 9.41% 80.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13442893 6.08% 86.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8809424 3.99% 90.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4514904 2.04% 92.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2991184 1.35% 94.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2424669 1.10% 95.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10346568 4.68% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 87530154 39.55% 39.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 70479011 31.84% 71.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 20814829 9.40% 80.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13433176 6.07% 86.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8801116 3.98% 90.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4514131 2.04% 92.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2986629 1.35% 94.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2449420 1.11% 95.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10320398 4.66% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 221063225 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 221328864 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037832 # Number of instructions committed system.cpu.commit.committedOps 327812214 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -654,154 +654,154 @@ system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 327812214 # Class of committed instruction -system.cpu.commit.bw_lim_events 10346568 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 561603777 # The number of ROB reads -system.cpu.rob.rob_writes 705508335 # The number of ROB writes -system.cpu.timesIdled 50687 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 324885 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 10320398 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 561900676 # The number of ROB reads +system.cpu.rob.rob_writes 705518580 # The number of ROB writes +system.cpu.timesIdled 50864 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 318151 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273037220 # Number of Instructions Simulated system.cpu.committedOps 327811602 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.824478 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.824478 # CPI: Total CPI of All Threads -system.cpu.ipc 1.212888 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.212888 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 331301011 # number of integer regfile reads -system.cpu.int_regfile_writes 136940115 # number of integer regfile writes -system.cpu.fp_regfile_reads 187107432 # number of floating regfile reads -system.cpu.fp_regfile_writes 132177980 # number of floating regfile writes -system.cpu.cc_regfile_reads 1297030870 # number of cc regfile reads -system.cpu.cc_regfile_writes 80242369 # number of cc regfile writes -system.cpu.misc_regfile_reads 1182848919 # number of misc regfile reads +system.cpu.cpi 0.825427 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.825427 # CPI: Total CPI of All Threads +system.cpu.ipc 1.211495 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.211495 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 331331443 # number of integer regfile reads +system.cpu.int_regfile_writes 136939322 # number of integer regfile writes +system.cpu.fp_regfile_reads 187108010 # number of floating regfile reads +system.cpu.fp_regfile_writes 132178699 # number of floating regfile writes +system.cpu.cc_regfile_reads 1297132712 # number of cc regfile reads +system.cpu.cc_regfile_writes 80241070 # number of cc regfile writes +system.cpu.misc_regfile_reads 1183128145 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1533856 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.842901 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 163689178 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1534368 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 106.681825 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 84489000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.842901 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999693 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999693 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1533845 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.844014 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 163642665 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1534357 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 106.652275 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 82317000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.844014 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999695 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999695 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336633512 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336633512 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 82631334 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 82631334 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80965560 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80965560 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 70478 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 70478 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 336636785 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336636785 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 82609327 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 82609327 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80941037 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80941037 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 70495 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 70495 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 163596894 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 163596894 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 163667372 # number of overall hits -system.cpu.dcache.overall_hits::total 163667372 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2773234 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2773234 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1087139 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1087139 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 163550364 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 163550364 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 163620859 # number of overall hits +system.cpu.dcache.overall_hits::total 163620859 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2796866 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2796866 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1111662 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1111662 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3860373 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3860373 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3860391 # number of overall misses -system.cpu.dcache.overall_misses::total 3860391 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 22353219965 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 22353219965 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8921439031 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8921439031 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 189750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31274658996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31274658996 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31274658996 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31274658996 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 85404568 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 85404568 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3908528 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3908528 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3908546 # number of overall misses +system.cpu.dcache.overall_misses::total 3908546 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 22404027000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 22404027000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8967503998 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8967503998 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 189000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31371530998 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31371530998 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31371530998 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31371530998 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 85406193 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 85406193 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 70496 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 70496 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 70513 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 70513 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 167457267 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 167457267 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 167527763 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 167527763 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032472 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032472 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013249 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013249 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 167458892 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 167458892 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 167529405 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 167529405 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032748 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032748 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013548 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013548 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000255 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.000255 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023053 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023053 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023043 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8060.343976 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 8060.343976 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8206.346227 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8206.346227 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37950 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37950 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 8101.460402 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 8101.460402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 8101.422627 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 8101.422627 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.023340 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023340 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023331 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023331 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8010.404145 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 8010.404145 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8066.754102 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8066.754102 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37800 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37800 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 8026.431178 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 8026.431178 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 8026.394214 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 8026.394214 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 920181 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1059827 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 117395 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 134751 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7.838332 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7.865077 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 966341 # number of writebacks -system.cpu.dcache.writebacks::total 966341 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1459520 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1459520 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 866494 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 866494 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 966339 # number of writebacks +system.cpu.dcache.writebacks::total 966339 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1483173 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1483173 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 891007 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 891007 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2326014 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2326014 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2326014 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2326014 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313714 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1313714 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220645 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 220645 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 2374180 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2374180 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2374180 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2374180 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313693 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1313693 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220655 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 220655 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1534359 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1534359 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1534370 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1534370 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9970454284 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9970454284 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1720952041 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1720952041 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 709000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 709000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11691406325 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11691406325 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11692115325 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11692115325 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1534348 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1534348 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1534359 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1534359 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10622731000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10622731000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1827670779 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1827670779 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 681000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 681000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12450401779 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12450401779 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12451082779 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12451082779 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015382 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015382 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002689 # mshr miss rate for WriteReq accesses @@ -812,368 +812,381 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009163 system.cpu.dcache.demand_mshr_miss_rate::total 0.009163 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009159 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.009159 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7589.516656 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7589.516656 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7799.642145 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7799.642145 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 64454.545455 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 64454.545455 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7619.733273 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 7619.733273 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7620.140726 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 7620.140726 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8086.159399 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8086.159399 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8282.933897 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8282.933897 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61909.090909 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61909.090909 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8114.457593 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8114.457593 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8114.843253 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8114.843253 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 715712 # 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Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 123.397113 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 324802500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.830268 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999668 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999668 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 245 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 178906541 # Number of tag accesses -system.cpu.icache.tags.data_accesses 178906541 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 88374047 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 88374047 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 88374047 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 88374047 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 88374047 # number of overall hits -system.cpu.icache.overall_hits::total 88374047 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 721111 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 721111 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 721111 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 721111 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 721111 # number of overall misses -system.cpu.icache.overall_misses::total 721111 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 5974650710 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 5974650710 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 5974650710 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 5974650710 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 5974650710 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 5974650710 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 89095158 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 89095158 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 89095158 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 89095158 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 89095158 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 89095158 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008094 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008094 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008094 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008094 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008094 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008094 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8285.341244 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8285.341244 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8285.341244 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8285.341244 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8285.341244 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8285.341244 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 59670 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 95 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2032 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 178900425 # Number of tag accesses +system.cpu.icache.tags.data_accesses 178900425 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 88370349 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 88370349 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 88370349 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 88370349 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 88370349 # number of overall hits +system.cpu.icache.overall_hits::total 88370349 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 721790 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 721790 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 721790 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 721790 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 721790 # number of overall misses +system.cpu.icache.overall_misses::total 721790 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 5973224944 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 5973224944 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 5973224944 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 5973224944 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 5973224944 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 5973224944 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 89092139 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 89092139 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 89092139 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 89092139 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 89092139 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 89092139 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008102 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008102 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008102 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008102 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008102 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008102 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8275.571765 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8275.571765 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8275.571765 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8275.571765 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8275.571765 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8275.571765 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 62134 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2178 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 29.365157 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 31.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.528007 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 31.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4886 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4886 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4886 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4886 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4886 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4886 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 716225 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 716225 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 716225 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 716225 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 716225 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 716225 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5193352944 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 5193352944 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5193352944 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 5193352944 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5193352944 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 5193352944 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008039 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.008039 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.008039 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7251.007636 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7251.007636 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7251.007636 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7251.007636 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7251.007636 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7251.007636 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 5643 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 5643 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 5643 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 5643 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 5643 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 5643 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 716147 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 716147 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 716147 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 716147 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 716147 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 716147 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5549831453 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 5549831453 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5549831453 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 5549831453 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5549831453 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 5549831453 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008038 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008038 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008038 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.008038 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008038 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.008038 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7749.570204 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7749.570204 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7749.570204 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7749.570204 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7749.570204 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7749.570204 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 405309 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 405577 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 209 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 404667 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 404963 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 238 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 27975 # number of prefetches not generated due to page crossing +system.cpu.l2cache.prefetcher.pfSpanPage 28037 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 5974.758413 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2806551 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 7279 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 385.568210 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 5979.453401 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3840411 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 7285 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 527.166918 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2575.130596 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2680.592596 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 609.586326 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 109.448896 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.157173 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.163610 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.037206 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006680 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 52729252 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 175790791 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 119823752 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 295614543 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 175790791 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 119823752 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 178618011 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 474232554 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004086 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000787 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001950 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1764 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 30350 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 35037 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 188993302 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 188993302 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 17000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 17000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 50613500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 50613500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 181139000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 181139000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 68370000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 68370000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 181139000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 118983500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 300122500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 181139000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 118983500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 188993302 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 489115802 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003648 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003648 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004086 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001199 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.002117 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004086 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001199 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003354 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003354 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004087 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004087 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000779 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000779 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004087 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001150 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.002083 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004087 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001150 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.015565 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60140.537462 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64888.297872 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61381.170331 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5903.946949 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 5903.946949 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65502.176398 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65502.176398 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60140.537462 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65157.015769 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62077.812474 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60140.537462 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65157.015769 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5903.946949 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13543.310315 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.015575 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6227.126919 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 6227.126919 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68396.621622 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68396.621622 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61970.236059 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61970.236059 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66767.578125 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66767.578125 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61970.236059 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67450.963719 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64032.963516 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61970.236059 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67450.963719 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6227.126919 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13959.979507 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2029950 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2029950 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 966341 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 31609 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2029851 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 966339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1033895 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 31761 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 220643 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 220643 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1431544 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4035081 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5466625 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45780416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160045376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205825792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 32515 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3248545 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.009730 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.098161 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 220653 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 220653 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 716147 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1313704 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2122577 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4377763 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6500340 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45775424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160044544 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205819968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 32667 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4531746 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.007009 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.083423 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3216936 99.03% 99.03% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 31609 0.97% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4499985 99.30% 99.30% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 31761 0.70% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3248545 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2574809000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1075177011 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4531746 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3216331500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1074485469 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2301798469 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2301553965 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 6500 # Transaction distribution -system.membus.trans_dist::ReadResp 6500 # Transaction distribution +system.membus.trans_dist::ReadResp 6571 # Transaction distribution system.membus.trans_dist::UpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 805 # Transaction distribution -system.membus.trans_dist::ReadExResp 805 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14612 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14612 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 467520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 467520 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 740 # Transaction distribution +system.membus.trans_dist::ReadExResp 740 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 6571 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14624 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14624 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 467904 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 467904 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7306 # Request fanout histogram +system.membus.snoop_fanout::samples 7312 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7306 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7312 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7306 # Request fanout histogram -system.membus.reqLayer0.occupancy 9226230 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7312 # Request fanout histogram +system.membus.reqLayer0.occupancy 9348857 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 38266679 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 38261400 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index cfbe2044c..b10e642ea 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.517235 # Number of seconds simulated -sim_ticks 517235405500 # Number of ticks simulated -final_tick 517235405500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 517235407500 # Number of ticks simulated +final_tick 517235407500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 520716 # Simulator instruction rate (inst/s) -host_op_rate 625139 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 987510163 # Simulator tick rate (ticks/s) -host_mem_usage 313820 # Number of bytes of host memory used -host_seconds 523.78 # Real time elapsed on the host +host_inst_rate 785915 # Simulator instruction rate (inst/s) +host_op_rate 943520 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1490444540 # Simulator tick rate (ticks/s) +host_mem_usage 321320 # Number of bytes of host memory used +host_seconds 347.03 # Real time elapsed on the host sim_insts 272739286 # Number of instructions simulated sim_ops 327433744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 1034470811 # number of cpu cycles simulated +system.cpu.numCycles 1034470815 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 272739286 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 168107847 # nu system.cpu.num_load_insts 85732248 # Number of load instructions system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1034470810.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1034470814.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 30563503 # Number of branches fetched @@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812214 # Class of executed instruction system.cpu.dcache.tags.replacements 1332 # number of replacements -system.cpu.dcache.tags.tagsinuse 3078.445034 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3078.445031 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445034 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445031 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id @@ -251,12 +251,12 @@ system.cpu.dcache.overall_misses::cpu.data 4479 # system.cpu.dcache.overall_misses::total 4479 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 78396000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 78396000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 157422500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 157422500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 235818500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 235818500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 235818500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 235818500 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 157423500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 157423500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 235819500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 235819500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 235819500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 235819500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) @@ -283,12 +283,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48875.311721 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 48875.311721 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54812.848189 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54812.848189 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52685.098302 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52685.098302 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52649.810225 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52649.810225 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.196379 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.196379 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52685.321716 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52685.321716 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52650.033490 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52650.033490 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -315,16 +315,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4475 system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75951500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75951500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 153114500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 153114500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 160500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 160500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 229066000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 229066000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 229226500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 229226500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76753000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 76753000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 154551500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 154551500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 162000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 162000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 231304500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 231304500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 231466500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 231466500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -335,24 +335,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47380.848409 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47380.848409 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53312.848189 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53312.848189 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51187.932961 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51187.932961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51189.481912 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51189.481912 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47880.848409 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47880.848409 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53813.196379 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53813.196379 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51688.156425 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51688.156425 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51689.705226 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51689.705226 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13796 # number of replacements -system.cpu.icache.tags.tagsinuse 1766.007655 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1766.007653 # Cycle average of tags in use system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007655 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007653 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id @@ -376,12 +376,12 @@ system.cpu.icache.demand_misses::cpu.inst 15603 # n system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses system.cpu.icache.overall_misses::total 15603 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 312482000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 312482000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 312482000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 312482000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 312482000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 312482000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 312483000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 312483000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 312483000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 312483000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 312483000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 312483000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses @@ -394,12 +394,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20027.046081 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20027.046081 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20027.046081 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20027.046081 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20027.046081 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20027.046081 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20027.110171 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20027.110171 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20027.110171 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20027.110171 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20027.110171 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20027.110171 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -414,34 +414,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603 system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 289077500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 289077500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 289077500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 289077500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 289077500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 289077500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 296880000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 296880000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 296880000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 296880000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 296880000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 296880000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18527.046081 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18527.046081 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18527.046081 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18527.046081 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18527.046081 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18527.046081 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19027.110171 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19027.110171 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19027.110171 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19027.110171 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19027.110171 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19027.110171 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3487.765010 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3487.764994 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 341.623059 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.427162 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 738.714789 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 341.623058 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.427152 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 738.714783 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010426 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073469 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.022544 # Average percentage of cache occupancy @@ -453,78 +453,84 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 176386 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 176386 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 12995 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 238 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 998 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 998 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12995 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 12995 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 238 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 238 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 12995 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 254 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 13249 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 12995 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 254 # number of overall hits system.cpu.l2cache.overall_hits::total 13249 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2608 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1368 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 3976 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2608 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2608 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1368 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 1368 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 2608 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 4224 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 2608 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4224 # number of overall misses system.cpu.l2cache.overall_misses::total 6832 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 137027000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 72007000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 209034000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 150074500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 150074500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 137027000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 222081500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 359108500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 137027000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 222081500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 359108500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 150075000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 150075000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 137027500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 137027500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 72007000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 72007000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 137027500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 222082000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 359109500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 137027500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 222082000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 359109500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 998 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 998 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15603 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 15603 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1606 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1606 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.167147 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.851806 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.231042 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167147 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167147 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.851806 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.851806 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167147 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.943278 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167147 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.943278 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52541.027607 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52636.695906 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52573.943662 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52547.093838 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52547.093838 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52541.027607 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52576.112689 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52562.719555 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52541.027607 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52576.112689 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52562.719555 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52547.268908 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52547.268908 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52541.219325 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52541.219325 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52636.695906 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52636.695906 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52541.219325 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52576.231061 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52562.865925 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52541.219325 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52576.231061 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52562.865925 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -533,84 +539,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2608 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1368 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3976 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2608 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2608 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1368 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1368 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2608 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 4224 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2608 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4224 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 105625000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55404000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 161029000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115668000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115668000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 105625000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 171072000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 276697000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 105625000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 171072000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 276697000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851806 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231042 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 121515000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 121515000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 110947500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 110947500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 58327000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 58327000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110947500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 179842000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 290789500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110947500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 179842000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 290789500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167147 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851806 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851806 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500.383436 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.251509 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500.383436 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.146370 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500.383436 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.146370 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42547.268908 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42547.268908 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42541.219325 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42541.219325 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42636.695906 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42636.695906 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42541.219325 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42576.231061 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42562.865925 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42541.219325 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42576.231061 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42562.865925 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6465 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31206 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9954 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 41160 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 37418 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10207 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 47625 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 998592 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 21079 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 35209 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 21079 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 35209 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 21079 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 35209 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 18602500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3976 # Transaction distribution system.membus.trans_dist::ReadResp 3976 # Transaction distribution system.membus.trans_dist::ReadExReq 2856 # Transaction distribution system.membus.trans_dist::ReadExResp 2856 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3976 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) @@ -626,9 +638,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 6833 # Request fanout histogram -system.membus.reqLayer0.occupancy 7260500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 7261500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 34587500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 34588500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |