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authorSteve Reinhardt <steve.reinhardt@amd.com>2016-03-17 10:30:58 -0700
committerSteve Reinhardt <steve.reinhardt@amd.com>2016-03-17 10:30:58 -0700
commit4fc69db8f89049a881a5f4aa68545840818b124c (patch)
tree7388f5b2755f6f4937b7ce9b8ba889f0d48bc403 /tests/long/se/30.eon/ref
parentdbad391a9b4e861fd3d660069ed448db85144e17 (diff)
downloadgem5-4fc69db8f89049a881a5f4aa68545840818b124c.tar.xz
stats: update stats for mmap changes
Diffstat (limited to 'tests/long/se/30.eon/ref')
-rw-r--r--tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini26
-rwxr-xr-xtests/long/se/30.eon/ref/arm/linux/simple-timing/simerr1
-rwxr-xr-xtests/long/se/30.eon/ref/arm/linux/simple-timing/simout10
-rw-r--r--tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt702
4 files changed, 377 insertions, 362 deletions
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
index 892e458ed..2a5bb3732 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
@@ -15,6 +15,7 @@ boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
eventq_index=0
+exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
@@ -24,6 +25,7 @@ mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
+multi_thread=false
num_work_ids=16
readfile=
symbolfile=
@@ -85,9 +87,9 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -101,6 +103,7 @@ system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
+writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -161,9 +164,9 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -177,6 +180,7 @@ system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
+writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@@ -196,6 +200,7 @@ eventq_index=0
[system.cpu.isa]
type=ArmISA
+decoderFlavour=Generic
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
@@ -271,9 +276,9 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -287,6 +292,7 @@ system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
+writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@@ -302,12 +308,14 @@ size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
@@ -315,6 +323,13 @@ width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
@@ -329,7 +344,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
+executable=/dist/m5/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
kvmInSE=false
@@ -364,6 +379,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr
index a25196116..7e050de51 100755
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr
@@ -1,4 +1,3 @@
-warn: Sockets disabled, not accepting gdb connections
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
index d5cd58d2c..7ed803ee9 100755
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 14 2015 23:29:19
-gem5 started Sep 15 2015 03:56:42
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
+gem5 compiled Mar 16 2016 15:51:04
+gem5 started Mar 16 2016 17:19:39
+gem5 executing on dinar2c11, pid 17050
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -16,4 +16,4 @@ info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
OO-style eon Time= 0.510000
-Exiting @ tick 517235407500 because target called exit()
+Exiting @ tick 517287152500 because target called exit()
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
index 42b8a5c86..7d459034e 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
@@ -1,34 +1,34 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.517291 # Number of seconds simulated
-sim_ticks 517291025500 # Number of ticks simulated
-final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.517287 # Number of seconds simulated
+sim_ticks 517287152500 # Number of ticks simulated
+final_tick 517287152500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 634406 # Simulator instruction rate (inst/s)
-host_op_rate 761628 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1203245454 # Simulator tick rate (ticks/s)
-host_mem_usage 324572 # Number of bytes of host memory used
-host_seconds 429.91 # Real time elapsed on the host
-sim_insts 272739286 # Number of instructions simulated
-sim_ops 327433744 # Number of ops (including micro ops) simulated
+host_inst_rate 131506 # Simulator instruction rate (inst/s)
+host_op_rate 157879 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 249419657 # Simulator tick rate (ticks/s)
+host_mem_usage 307088 # Number of bytes of host memory used
+host_seconds 2073.96 # Real time elapsed on the host
+sim_insts 272737951 # Number of instructions simulated
+sim_ops 327435116 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory
-system.physmem.bytes_read::total 437248 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 166912 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 166912 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 322666 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 522599 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 845265 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 322666 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 322666 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 269696 # Number of bytes read from this memory
+system.physmem.bytes_read::total 436672 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 166976 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 4214 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 6823 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 322792 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 521366 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 844158 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 322792 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 322792 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 322792 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 521366 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 844158 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@@ -147,33 +147,33 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
-system.cpu.numCycles 1034582051 # number of cpu cycles simulated
+system.cpu.numCycles 1034574305 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 272739286 # Number of instructions committed
-system.cpu.committedOps 327433744 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses
+system.cpu.committedInsts 272737951 # Number of instructions committed
+system.cpu.committedOps 327435116 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 258332236 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
-system.cpu.num_func_calls 12448615 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls
-system.cpu.num_int_insts 258331537 # number of integer instructions
+system.cpu.num_func_calls 12449970 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 15800021 # number of instructions that are conditional controls
+system.cpu.num_int_insts 258332236 # number of integer instructions
system.cpu.num_fp_insts 114216705 # number of float instructions
-system.cpu.num_int_register_reads 1215888421 # number of times the integer registers were read
-system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written
+system.cpu.num_int_register_reads 1215886434 # number of times the integer registers were read
+system.cpu.num_int_register_writes 162499715 # number of times the integer registers were written
system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 1242915503 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written
-system.cpu.num_mem_refs 168107847 # number of memory refs
-system.cpu.num_load_insts 85732248 # Number of load instructions
-system.cpu.num_store_insts 82375599 # Number of store instructions
+system.cpu.num_cc_register_reads 1242911540 # number of times the CC registers were read
+system.cpu.num_cc_register_writes 76355719 # number of times the CC registers were written
+system.cpu.num_mem_refs 168105830 # number of memory refs
+system.cpu.num_load_insts 85730232 # Number of load instructions
+system.cpu.num_store_insts 82375598 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 1034582050.998000 # Number of busy cycles
+system.cpu.num_busy_cycles 1034574304.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 30563503 # Number of branches fetched
+system.cpu.Branches 30566209 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu 104312544 31.82% 31.82% # Class of executed instruction
+system.cpu.op_class::IntAlu 104315933 31.82% 31.82% # Class of executed instruction
system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction
@@ -198,79 +198,79 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Cl
system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 19652356 5.99% 44.33% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.67% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction
-system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction
-system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction
+system.cpu.op_class::MemRead 85730232 26.15% 74.87% # Class of executed instruction
+system.cpu.op_class::MemWrite 82375598 25.13% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 327812214 # Class of executed instruction
-system.cpu.dcache.tags.replacements 1332 # number of replacements
-system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks.
+system.cpu.op_class::total 327813586 # Class of executed instruction
+system.cpu.dcache.tags.replacements 1326 # number of replacements
+system.cpu.dcache.tags.tagsinuse 3078.339297 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 168357609 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 4469 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 37672.322443 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 3078.335714 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.751547 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.751547 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data 3078.339297 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.751548 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.751548 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 3143 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 678 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4 2434 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.767334 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 336728627 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 336728627 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 86231946 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 86231946 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 82049814 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 82049814 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits
-system.cpu.dcache.overall_hits::total 168337827 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data 168281760 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 168281760 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 168335819 # number of overall hits
+system.cpu.dcache.overall_hits::total 168335819 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1605 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1605 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 2862 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2862 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses
-system.cpu.dcache.overall_misses::total 4479 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 88052000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 88052000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 177422500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 177422500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 265474500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 265474500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 265474500 # number of overall miss cycles
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system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
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-system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses
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-system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses
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+system.cpu.dcache.demand_accesses::total 168286227 # number of demand (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses
@@ -281,14 +281,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000027
system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
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-system.cpu.dcache.ReadReq_avg_miss_latency::total 54895.261845 # average ReadReq miss latency
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-system.cpu.dcache.WriteReq_avg_miss_latency::total 61776.636490 # average WriteReq miss latency
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-system.cpu.dcache.demand_avg_miss_latency::total 59310.656836 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 59270.931011 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 59270.931011 # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54869.781931 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 54869.781931 # average ReadReq miss latency
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+system.cpu.dcache.WriteReq_avg_miss_latency::total 61775.856045 # average WriteReq miss latency
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+system.cpu.dcache.demand_avg_miss_latency::total 59294.492948 # average overall miss latency
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+system.cpu.dcache.overall_avg_miss_latency::total 59254.697987 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -297,34 +297,34 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 998 # number of writebacks
-system.cpu.dcache.writebacks::total 998 # number of writebacks
+system.cpu.dcache.writebacks::writebacks 997 # number of writebacks
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system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
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system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
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system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits
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system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
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system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 183000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 183000 # number of SoftPFReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
@@ -335,71 +335,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
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-system.cpu.icache.tags.replacements 13796 # number of replacements
-system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use
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system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy
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system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -408,42 +408,42 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 67911000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129212000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 209421500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 338633500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129212000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 209421500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 338633500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167147 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851806 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851806 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.494398 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.494398 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.478528 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.478528 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129261500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 208926500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 338188000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129261500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 208926500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 338188000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994410 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994410 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167190 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167190 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851276 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851276 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167190 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942940 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.339892 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167190 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942940 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.339892 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.664793 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.664793 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.461479 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.461479 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.461479 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49579.140959 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.880111 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.461479 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49579.140959 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.880111 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests 35198 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 15220 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7664 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 334 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45002 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10288 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 55290 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881536 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 2232000 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadResp 17212 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty 997 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 13798 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 329 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 2862 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 2862 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 15605 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 1607 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45008 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10264 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 55272 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881792 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 349824 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 2231616 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 20081 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.386335 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.486921 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 20074 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.386570 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.486976 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 12323 61.37% 61.37% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 7758 38.63% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 12314 61.34% 61.34% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 7760 38.66% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 20081 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 32398500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 20074 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 32394000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 23407500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 6703500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.trans_dist::ReadResp 3976 # Transaction distribution
-system.membus.trans_dist::ReadExReq 2856 # Transaction distribution
-system.membus.trans_dist::ReadExResp 2856 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 3976 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp 3977 # Transaction distribution
+system.membus.trans_dist::ReadExReq 2846 # Transaction distribution
+system.membus.trans_dist::ReadExResp 2846 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 3977 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13646 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 13646 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 436672 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 436672 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 6833 # Request fanout histogram
+system.membus.snoop_fanout::samples 6824 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 6824 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 6833 # Request fanout histogram
-system.membus.reqLayer0.occupancy 7281500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 6824 # Request fanout histogram
+system.membus.reqLayer0.occupancy 7272500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 34160000 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 34115000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------