diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
| commit | a217eba078b17c51f6a74c9237584f066ef78bf1 (patch) | |
| tree | e566cbeb3520341dbdf6ecb0d3932a31d4e156fe /tests/long/se/30.eon/ref | |
| parent | db430698bfd4d77a49e11031bb65444552891f37 (diff) | |
| download | gem5-a217eba078b17c51f6a74c9237584f066ef78bf1.tar.xz | |
stats: Update stats for CPU and cache changes
This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
Diffstat (limited to 'tests/long/se/30.eon/ref')
8 files changed, 2587 insertions, 2542 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index 0b41505d8..2ad80aa5a 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.219644 # Number of seconds simulated -sim_ticks 219644167500 # Number of ticks simulated -final_tick 219644167500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.220941 # Number of seconds simulated +sim_ticks 220941341500 # Number of ticks simulated +final_tick 220941341500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 184210 # Simulator instruction rate (inst/s) -host_op_rate 184210 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 101490439 # Simulator tick rate (ticks/s) -host_mem_usage 247040 # Number of bytes of host memory used -host_seconds 2164.19 # Real time elapsed on the host +host_inst_rate 303038 # Simulator instruction rate (inst/s) +host_op_rate 303038 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 167944827 # Simulator tick rate (ticks/s) +host_mem_usage 273400 # Number of bytes of host memory used +host_seconds 1315.56 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -19,12 +19,12 @@ system.physmem.bytes_inst_read::cpu.inst 249408 # Nu system.physmem.bytes_inst_read::total 249408 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 7875 # Number of read requests responded to by this memory system.physmem.num_reads::total 7875 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2294620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2294620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1135509 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1135509 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2294620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2294620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 2281148 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2281148 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1128843 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1128843 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2281148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2281148 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7875 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7875 # Number of DRAM read bursts, including those serviced by the write queue @@ -71,7 +71,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 219644086000 # Total gap between requests +system.physmem.totGap 220941260000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -86,8 +86,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6822 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 970 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6820 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 972 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -182,29 +182,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1515 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 331.828383 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 199.155331 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.926802 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 511 33.73% 33.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 341 22.51% 56.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 189 12.48% 68.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 107 7.06% 75.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 50 3.30% 79.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 60 3.96% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 36 2.38% 85.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 30 1.98% 87.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 191 12.61% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1515 # Bytes accessed per row activation -system.physmem.totQLat 51832750 # Total ticks spent queuing -system.physmem.totMemAccLat 199489000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1518 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 330.160738 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 197.894458 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.998951 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 519 34.19% 34.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 336 22.13% 56.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 186 12.25% 68.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 110 7.25% 75.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 56 3.69% 79.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 56 3.69% 83.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 37 2.44% 85.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 28 1.84% 87.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 190 12.52% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1518 # Bytes accessed per row activation +system.physmem.totQLat 52730250 # Total ticks spent queuing +system.physmem.totMemAccLat 200386500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 39375000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6581.94 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6695.90 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25331.94 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25445.90 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.28 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.28 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage @@ -212,18 +212,18 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6354 # Number of row buffer hits during reads +system.physmem.readRowHits 6348 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.69 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 27891312.51 # Average gap between requests -system.physmem.pageHitRate 80.69 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 210595847500 # Time in different power states -system.physmem.memoryStateTime::REF 7334340000 # Time in different power states +system.physmem.avgGap 28056033.02 # Average gap between requests +system.physmem.pageHitRate 80.61 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 211835989750 # Time in different power states +system.physmem.memoryStateTime::REF 7377500000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1712418250 # Time in different power states +system.physmem.memoryStateTime::ACT 1721627750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 2294620 # Throughput (bytes/s) +system.membus.throughput 2281148 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 4737 # Transaction distribution system.membus.trans_dist::ReadResp 4737 # Transaction distribution system.membus.trans_dist::ReadExReq 3138 # Transaction distribution @@ -234,40 +234,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 504000 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 504000 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 9401500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9511500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 73916250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 74010500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 46223200 # Number of BP lookups -system.cpu.branchPred.condPredicted 26710359 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1014875 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25598344 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21333887 # Number of BTB hits +system.cpu.branchPred.lookups 46221231 # Number of BP lookups +system.cpu.branchPred.condPredicted 26710053 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1012987 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 25408308 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21330923 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.340887 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 8326899 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 83.952552 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 8326726 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 95595217 # DTB read hits -system.cpu.dtb.read_misses 114 # DTB read misses +system.cpu.dtb.read_hits 95595776 # DTB read hits +system.cpu.dtb.read_misses 118 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 95595331 # DTB read accesses -system.cpu.dtb.write_hits 73605959 # DTB write hits +system.cpu.dtb.read_accesses 95595894 # DTB read accesses +system.cpu.dtb.write_hits 73604420 # DTB write hits system.cpu.dtb.write_misses 858 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73606817 # DTB write accesses -system.cpu.dtb.data_hits 169201176 # DTB hits -system.cpu.dtb.data_misses 972 # DTB misses +system.cpu.dtb.write_accesses 73605278 # DTB write accesses +system.cpu.dtb.data_hits 169200196 # DTB hits +system.cpu.dtb.data_misses 976 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 169202148 # DTB accesses -system.cpu.itb.fetch_hits 98054052 # ITB hits -system.cpu.itb.fetch_misses 1240 # ITB misses +system.cpu.dtb.data_accesses 169201172 # DTB accesses +system.cpu.itb.fetch_hits 98242303 # ITB hits +system.cpu.itb.fetch_misses 1225 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 98055292 # ITB accesses +system.cpu.itb.fetch_accesses 98243528 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -281,70 +281,70 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 439288335 # number of cpu cycles simulated +system.cpu.numCycles 441882683 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664665 # Number of instructions committed system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4458110 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 4446127 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.101899 # CPI: cycles per instruction -system.cpu.ipc 0.907524 # IPC: instructions per cycle -system.cpu.tickCycles 435056382 # Number of cycles that the object actually ticked -system.cpu.idleCycles 4231953 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.108407 # CPI: cycles per instruction +system.cpu.ipc 0.902196 # IPC: instructions per cycle +system.cpu.tickCycles 437732113 # Number of cycles that the object actually ticked +system.cpu.idleCycles 4150570 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 3195 # number of replacements -system.cpu.icache.tags.tagsinuse 1919.689869 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 98048879 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1919.708567 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 98237130 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 5173 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18953.968490 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 18990.359559 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1919.689869 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.937349 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.937349 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1919.708567 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.937358 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.937358 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 200 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 198 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 398 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1282 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 196113277 # Number of tag accesses -system.cpu.icache.tags.data_accesses 196113277 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 98048879 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 98048879 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 98048879 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 98048879 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 98048879 # number of overall hits -system.cpu.icache.overall_hits::total 98048879 # number of overall hits +system.cpu.icache.tags.tag_accesses 196489779 # Number of tag accesses +system.cpu.icache.tags.data_accesses 196489779 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 98237130 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 98237130 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 98237130 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 98237130 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 98237130 # number of overall hits +system.cpu.icache.overall_hits::total 98237130 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 5173 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 5173 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 5173 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 5173 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5173 # number of overall misses system.cpu.icache.overall_misses::total 5173 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 293884750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 293884750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 293884750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 293884750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 293884750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 293884750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 98054052 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 98054052 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 98054052 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 98054052 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 98054052 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 98054052 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 293554750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 293554750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 293554750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 293554750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 293554750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 293554750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 98242303 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 98242303 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 98242303 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 98242303 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 98242303 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 98242303 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000053 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000053 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000053 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56811.279722 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56811.279722 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56811.279722 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56811.279722 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56811.279722 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56811.279722 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56747.486951 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56747.486951 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56747.486951 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56747.486951 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56747.486951 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56747.486951 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -359,26 +359,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 5173 system.cpu.icache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 5173 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 5173 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281914250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281914250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281914250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281914250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281914250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281914250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281585250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 281585250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281585250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 281585250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281585250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 281585250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54497.245312 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54497.245312 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54497.245312 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54497.245312 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54497.245312 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54497.245312 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54433.645853 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54433.645853 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54433.645853 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54433.645853 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54433.645853 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54433.645853 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 2911473 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 2894379 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 6139 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 6139 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution @@ -394,24 +394,24 @@ system.cpu.toL2Bus.data_through_bus 639488 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 5650000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8571750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 8571250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6975500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6974750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4427.544414 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4427.627395 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1491 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5274 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.282708 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 373.069820 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4054.474595 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011385 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123733 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.135118 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 373.083919 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4054.543476 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011386 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123735 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.135120 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 5274 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 612 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4444 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160950 # Percentage of cache occupancy per task id @@ -435,14 +435,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 7875 # system.cpu.l2cache.demand_misses::total 7875 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 7875 # number of overall misses system.cpu.l2cache.overall_misses::total 7875 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 325631750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 325631750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 212036500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 212036500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 537668250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 537668250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 537668250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 537668250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 325767500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 325767500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 212904500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 212904500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 538672000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 538672000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 538672000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 538672000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 6139 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 6139 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 654 # number of Writeback accesses(hits+misses) @@ -461,14 +461,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.843328 system.cpu.l2cache.demand_miss_rate::total 0.843328 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.843328 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.843328 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68742.189149 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68742.189149 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67570.586361 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67570.586361 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68275.333333 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68275.333333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68275.333333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68275.333333 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68770.846527 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68770.846527 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67847.195666 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67847.195666 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68402.793651 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68402.793651 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68402.793651 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68402.793651 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -485,14 +485,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 7875 system.cpu.l2cache.demand_mshr_misses::total 7875 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 7875 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7875 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266250750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266250750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 172336000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 172336000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 438586750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 438586750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 438586750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 438586750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266387000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266387000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 173110500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 173110500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 439497500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 439497500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 439497500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 439497500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.771624 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771624 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.980932 # mshr miss rate for ReadExReq accesses @@ -501,65 +501,65 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.843328 system.cpu.l2cache.demand_mshr_miss_rate::total 0.843328 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.843328 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.843328 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56206.618113 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56206.618113 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54919.056724 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54919.056724 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55693.555556 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55693.555556 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55693.555556 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55693.555556 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56235.381043 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56235.381043 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55165.869981 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55165.869981 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55809.206349 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55809.206349 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55809.206349 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55809.206349 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.682067 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168006905 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3291.748201 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168007181 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40337.792317 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40337.858583 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.682067 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.803633 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803633 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.748201 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.803649 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803649 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336032209 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336032209 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 94492115 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94492115 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 73514790 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73514790 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 168006905 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168006905 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 168006905 # number of overall hits -system.cpu.dcache.overall_hits::total 168006905 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 1177 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1177 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 5940 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5940 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 7117 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7117 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 7117 # number of overall misses -system.cpu.dcache.overall_misses::total 7117 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 80734750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 80734750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 392862000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 392862000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 473596750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 473596750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 473596750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 473596750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 94493292 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94493292 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 336032765 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336032765 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 94492394 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94492394 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 73514787 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73514787 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 168007181 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168007181 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 168007181 # number of overall hits +system.cpu.dcache.overall_hits::total 168007181 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 1176 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1176 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 5943 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5943 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 7119 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7119 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 7119 # number of overall misses +system.cpu.dcache.overall_misses::total 7119 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 81035500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 81035500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 393767750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 393767750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 474803250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 474803250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 474803250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 474803250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 94493570 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94493570 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 73520730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 168014022 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168014022 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 168014022 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168014022 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.inst 168014300 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168014300 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 168014300 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168014300 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000081 # miss rate for WriteReq accesses @@ -568,14 +568,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.000042 system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68593.670348 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68593.670348 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66138.383838 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66138.383838 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66544.435858 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66544.435858 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66544.435858 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66544.435858 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68907.738095 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68907.738095 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66257.403668 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66257.403668 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66695.217025 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66695.217025 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66695.217025 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66695.217025 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -588,28 +588,28 @@ system.cpu.dcache.writebacks::writebacks 654 # nu system.cpu.dcache.writebacks::total 654 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 208 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 208 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2744 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2744 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 2952 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2952 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 2952 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2952 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 969 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 3196 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3196 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2746 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2746 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 2954 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2954 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 2954 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2954 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 968 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 968 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 3197 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3197 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.inst 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 64078250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 64078250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 215682250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 215682250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 279760500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 279760500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 279760500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 279760500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 64480250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 64480250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 216613000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 216613000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 281093250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 281093250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 281093250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 281093250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for WriteReq accesses @@ -618,14 +618,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66128.224974 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66128.224974 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67485.059449 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67485.059449 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67169.387755 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67169.387755 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67169.387755 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67169.387755 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66611.828512 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66611.828512 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67755.082890 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67755.082890 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67489.375750 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67489.375750 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67489.375750 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67489.375750 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 35136e25d..0f0c79704 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.072880 # Number of seconds simulated -sim_ticks 72880000500 # Number of ticks simulated -final_tick 72880000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.069652 # Number of seconds simulated +sim_ticks 69651704000 # Number of ticks simulated +final_tick 69651704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 219272 # Simulator instruction rate (inst/s) -host_op_rate 219272 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42549566 # Simulator tick rate (ticks/s) -host_mem_usage 229100 # Number of bytes of host memory used -host_seconds 1712.83 # Real time elapsed on the host +host_inst_rate 185769 # Simulator instruction rate (inst/s) +host_op_rate 185769 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34451530 # Simulator tick rate (ticks/s) +host_mem_usage 243176 # Number of bytes of host memory used +host_seconds 2021.73 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 221696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255296 # Number of bytes read from this memory -system.physmem.bytes_read::total 476992 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3464 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3989 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7453 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3041932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3502964 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6544896 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3041932 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3041932 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3041932 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3502964 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6544896 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7453 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 221568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255744 # Number of bytes read from this memory +system.physmem.bytes_read::total 477312 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221568 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3462 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3996 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7458 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 3181085 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3671755 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6852840 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3181085 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3181085 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3181085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3671755 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6852840 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7458 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7453 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7458 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 476992 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 477312 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 476992 # Total read bytes from the system interface side +system.physmem.bytesReadSys 477312 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 527 # Per bank write bursts -system.physmem.perBankRdBursts::1 653 # Per bank write bursts -system.physmem.perBankRdBursts::2 448 # Per bank write bursts +system.physmem.perBankRdBursts::0 528 # Per bank write bursts +system.physmem.perBankRdBursts::1 655 # Per bank write bursts +system.physmem.perBankRdBursts::2 455 # Per bank write bursts system.physmem.perBankRdBursts::3 602 # Per bank write bursts -system.physmem.perBankRdBursts::4 447 # Per bank write bursts -system.physmem.perBankRdBursts::5 455 # Per bank write bursts +system.physmem.perBankRdBursts::4 446 # Per bank write bursts +system.physmem.perBankRdBursts::5 454 # Per bank write bursts system.physmem.perBankRdBursts::6 515 # Per bank write bursts system.physmem.perBankRdBursts::7 524 # Per bank write bursts -system.physmem.perBankRdBursts::8 438 # Per bank write bursts -system.physmem.perBankRdBursts::9 405 # Per bank write bursts -system.physmem.perBankRdBursts::10 337 # Per bank write bursts -system.physmem.perBankRdBursts::11 306 # Per bank write bursts +system.physmem.perBankRdBursts::8 439 # Per bank write bursts +system.physmem.perBankRdBursts::9 406 # Per bank write bursts +system.physmem.perBankRdBursts::10 340 # Per bank write bursts +system.physmem.perBankRdBursts::11 305 # Per bank write bursts system.physmem.perBankRdBursts::12 414 # Per bank write bursts -system.physmem.perBankRdBursts::13 544 # Per bank write bursts -system.physmem.perBankRdBursts::14 457 # Per bank write bursts -system.physmem.perBankRdBursts::15 381 # Per bank write bursts +system.physmem.perBankRdBursts::13 542 # Per bank write bursts +system.physmem.perBankRdBursts::14 454 # Per bank write bursts +system.physmem.perBankRdBursts::15 379 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 72879898500 # Total gap between requests +system.physmem.totGap 69651614500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7453 # Read request sizes (log2) +system.physmem.readPktSize::6 7458 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 858 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4229 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1956 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 918 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 291 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 62 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,92 +186,92 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1352 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 352.520710 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 211.357899 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 348.521013 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 414 30.62% 30.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 333 24.63% 55.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 156 11.54% 66.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 86 6.36% 73.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 58 4.29% 77.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 36 2.66% 80.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 33 2.44% 82.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 35 2.59% 85.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 201 14.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1352 # Bytes accessed per row activation -system.physmem.totQLat 65605500 # Total ticks spent queuing -system.physmem.totMemAccLat 205349250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37265000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8802.56 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1354 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 350.251108 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 208.626324 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 348.782669 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 425 31.39% 31.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 330 24.37% 55.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 151 11.15% 66.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 84 6.20% 73.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 54 3.99% 77.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 42 3.10% 80.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 39 2.88% 83.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 25 1.85% 84.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 204 15.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1354 # Bytes accessed per row activation +system.physmem.totQLat 65436750 # Total ticks spent queuing +system.physmem.totMemAccLat 205274250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37290000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8774.03 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27552.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.54 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27524.03 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.85 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.54 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.85 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6099 # Number of row buffer hits during reads +system.physmem.readRowHits 6095 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.83 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.72 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9778599.02 # Average gap between requests -system.physmem.pageHitRate 81.83 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 69326847500 # Time in different power states -system.physmem.memoryStateTime::REF 2433600000 # Time in different power states +system.physmem.avgGap 9339181.35 # Average gap between requests +system.physmem.pageHitRate 81.72 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 66207100500 # Time in different power states +system.physmem.memoryStateTime::REF 2325700000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1119126250 # Time in different power states +system.physmem.memoryStateTime::ACT 1115479500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 6544896 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4323 # Transaction distribution -system.membus.trans_dist::ReadResp 4323 # Transaction distribution +system.membus.throughput 6852840 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4328 # Transaction distribution +system.membus.trans_dist::ReadResp 4328 # Transaction distribution system.membus.trans_dist::ReadExReq 3130 # Transaction distribution system.membus.trans_dist::ReadExResp 3130 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14906 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476992 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 476992 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 476992 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14916 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14916 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477312 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 477312 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 477312 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 9314500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9424500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 69584750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 69714000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 50777064 # Number of BP lookups -system.cpu.branchPred.condPredicted 29451932 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1209851 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26262147 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23434234 # Number of BTB hits +system.cpu.branchPred.lookups 51167476 # Number of BP lookups +system.cpu.branchPred.condPredicted 29641015 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1213095 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 25804997 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23600999 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.231981 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9219036 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1140 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 91.459026 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9351095 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 307 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 102450301 # DTB read hits -system.cpu.dtb.read_misses 84837 # DTB read misses -system.cpu.dtb.read_acv 48604 # DTB read access violations -system.cpu.dtb.read_accesses 102535138 # DTB read accesses -system.cpu.dtb.write_hits 78798145 # DTB write hits -system.cpu.dtb.write_misses 1517 # DTB write misses +system.cpu.dtb.read_hits 103696201 # DTB read hits +system.cpu.dtb.read_misses 91462 # DTB read misses +system.cpu.dtb.read_acv 49407 # DTB read access violations +system.cpu.dtb.read_accesses 103787663 # DTB read accesses +system.cpu.dtb.write_hits 79414480 # DTB write hits +system.cpu.dtb.write_misses 1579 # DTB write misses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 78799662 # DTB write accesses -system.cpu.dtb.data_hits 181248446 # DTB hits -system.cpu.dtb.data_misses 86354 # DTB misses -system.cpu.dtb.data_acv 48606 # DTB access violations -system.cpu.dtb.data_accesses 181334800 # DTB accesses -system.cpu.itb.fetch_hits 50876988 # ITB hits -system.cpu.itb.fetch_misses 370 # ITB misses +system.cpu.dtb.write_accesses 79416059 # DTB write accesses +system.cpu.dtb.data_hits 183110681 # DTB hits +system.cpu.dtb.data_misses 93041 # DTB misses +system.cpu.dtb.data_acv 49409 # DTB access violations +system.cpu.dtb.data_accesses 183203722 # DTB accesses +system.cpu.itb.fetch_hits 51277823 # ITB hits +system.cpu.itb.fetch_misses 422 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 50877358 # ITB accesses +system.cpu.itb.fetch_accesses 51278245 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -285,239 +285,239 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 145760003 # number of cpu cycles simulated +system.cpu.numCycles 139303411 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 51716425 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 453983948 # Number of instructions fetch has processed -system.cpu.fetch.Branches 50777064 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 32653270 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 79737605 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6706722 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 8534058 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 10415 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 50876988 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 470753 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 145449114 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.121256 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.346528 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 52063836 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 457094552 # Number of instructions fetch has processed +system.cpu.fetch.Branches 51167476 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 32952094 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 85692293 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2532764 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 13783 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 51277823 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 545280 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 139036498 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.287587 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.344928 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 65711509 45.18% 45.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4353129 2.99% 48.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6951535 4.78% 52.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5417508 3.72% 56.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11887137 8.17% 64.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 7943266 5.46% 70.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5717445 3.93% 74.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1835003 1.26% 75.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35632582 24.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58307253 41.94% 41.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4519217 3.25% 45.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 7280822 5.24% 50.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5545601 3.99% 54.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11970287 8.61% 63.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 8019991 5.77% 68.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5933035 4.27% 73.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1884761 1.36% 74.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35575531 25.59% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 145449114 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.348361 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.114599 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 53474843 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7565433 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 78027173 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 935486 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5446179 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9541832 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4276 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 449545046 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12399 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5446179 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 54745977 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 756567 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 422703 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 77638167 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6439521 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 445569466 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 326953 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1035803 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1822362 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 2964059 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 290831608 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 586091926 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 418076358 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168015567 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 139036498 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.367310 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.281288 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45112294 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16348159 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 71786999 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4526862 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1262184 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9563244 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4245 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 451283163 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 14200 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1262184 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 47010937 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5663540 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 519055 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 74309214 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 10271568 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 447721649 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 439815 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2540100 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2926498 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 3600584 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 292278306 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 589607782 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 419965282 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 169642499 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31299279 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 36843 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 279 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 7560708 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 105663529 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 81235477 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 11146516 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 7815881 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 412301107 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 261 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 404056264 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1312815 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 35808008 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 18428665 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 145449114 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.777991 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.042688 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 32745977 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 37893 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 316 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 16173803 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 106306370 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 81667386 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12470725 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9729569 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 414594685 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 306 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 406915916 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 484036 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 38878487 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 18208108 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 91 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 139036498 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.926684 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.221929 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 25098996 17.26% 17.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 21117633 14.52% 31.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22669138 15.59% 47.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 22701668 15.61% 62.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 23036562 15.84% 78.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15514820 10.67% 89.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8774349 6.03% 95.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 5158675 3.55% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1377273 0.95% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23891417 17.18% 17.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19616673 14.11% 31.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22677490 16.31% 47.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18900240 13.59% 61.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 19609415 14.10% 75.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14153869 10.18% 85.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9626408 6.92% 92.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6209798 4.47% 96.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4351188 3.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 145449114 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 139036498 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 102079 0.82% 0.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 0.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 61666 0.50% 1.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 48308 0.39% 1.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 3198 0.03% 1.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1785372 14.39% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1353790 10.91% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5374985 43.31% 70.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3681074 29.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 258477 1.29% 1.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.00% 1.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 145250 0.73% 2.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 90218 0.45% 2.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 2947 0.01% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 3497968 17.50% 19.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1676632 8.39% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9338598 46.73% 75.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4976149 24.90% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 156664975 38.77% 38.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2127225 0.53% 39.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32964847 8.16% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7504684 1.86% 49.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2799878 0.69% 50.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16685729 4.13% 54.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1581715 0.39% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 104147450 25.78% 80.31% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 79546180 19.69% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 153207489 37.65% 37.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2128182 0.52% 38.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 37392506 9.19% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7524499 1.85% 49.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2804822 0.69% 49.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16757586 4.12% 54.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1601657 0.39% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 105367867 25.89% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 80097727 19.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 404056264 # Type of FU issued -system.cpu.iq.rate 2.772065 # Inst issue rate -system.cpu.iq.fu_busy_cnt 12410472 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.030715 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 628197329 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 263376555 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 235877430 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 339087600 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 184792904 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 162158669 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 243128966 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 173304189 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17056087 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 406915916 # Type of FU issued +system.cpu.iq.rate 2.921076 # Inst issue rate +system.cpu.iq.fu_busy_cnt 19986240 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.049116 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 625896967 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 265989715 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237228630 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 347441639 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 187559752 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 163339265 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 246150912 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 180717663 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19936358 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10909042 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 154314 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 60406 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7714748 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 11551883 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 163597 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 76334 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8146657 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 360272 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4287 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 381699 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4486 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5446179 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1032 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 211342 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 437229791 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 59050 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 105663529 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 81235477 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 261 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4770 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 204982 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 60406 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 953368 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 408257 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1361625 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 400360320 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 102583778 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3695944 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1262184 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4471522 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 139226 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 439574480 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 145285 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 106306370 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 81667386 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 306 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6690 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 131709 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 76334 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 976027 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412585 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1388612 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 403157734 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 103837101 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3758182 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24928423 # number of nop insts executed -system.cpu.iew.exec_refs 181383470 # number of memory reference insts executed -system.cpu.iew.exec_branches 46799473 # Number of branches executed -system.cpu.iew.exec_stores 78799692 # Number of stores executed -system.cpu.iew.exec_rate 2.746709 # Inst execution rate -system.cpu.iew.wb_sent 398772945 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 398036099 # cumulative count of insts written-back -system.cpu.iew.wb_producers 201124096 # num instructions producing a value -system.cpu.iew.wb_consumers 293988661 # num instructions consuming a value +system.cpu.iew.exec_nop 24979489 # number of nop insts executed +system.cpu.iew.exec_refs 183253197 # number of memory reference insts executed +system.cpu.iew.exec_branches 46959988 # Number of branches executed +system.cpu.iew.exec_stores 79416096 # Number of stores executed +system.cpu.iew.exec_rate 2.894098 # Inst execution rate +system.cpu.iew.wb_sent 401401506 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 400567895 # cumulative count of insts written-back +system.cpu.iew.wb_producers 198000447 # num instructions producing a value +system.cpu.iew.wb_consumers 283955601 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.730764 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.684122 # average fanout of values written-back +system.cpu.iew.wb_rate 2.875507 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.697294 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 38564789 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 40912072 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1205629 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 140002935 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.847544 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.108853 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1208897 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 133310645 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.990493 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.213946 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 50426990 36.02% 36.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 20519996 14.66% 50.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11173587 7.98% 58.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9865184 7.05% 65.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 7560021 5.40% 71.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4963241 3.55% 74.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4885893 3.49% 78.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3033970 2.17% 80.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 27574053 19.70% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 48555640 36.42% 36.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18055919 13.54% 49.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 9630862 7.22% 57.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8737321 6.55% 63.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6426213 4.82% 68.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4404757 3.30% 71.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 4988495 3.74% 75.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2616134 1.96% 77.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29895304 22.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 140002935 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 133310645 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -529,10 +529,10 @@ system.cpu.commit.fp_insts 155295106 # Nu system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 145805186 36.57% 42.37% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2124322 0.53% 42.91% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 42.91% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 31467419 7.89% 50.80% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 141652545 35.53% 41.33% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 41.86% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 35620060 8.93% 50.80% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 7072549 1.77% 52.57% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 2735231 0.69% 53.26% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 16498021 4.14% 57.40% # Class of committed instruction @@ -563,227 +563,227 @@ system.cpu.commit.op_class_0::MemWrite 73520729 18.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 398664583 # Class of committed instruction -system.cpu.commit.bw_lim_events 27574053 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29895304 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 549655277 # The number of ROB reads -system.cpu.rob.rob_writes 879919465 # The number of ROB writes -system.cpu.timesIdled 3916 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 310889 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 542989019 # The number of ROB reads +system.cpu.rob.rob_writes 884890973 # The number of ROB writes +system.cpu.timesIdled 3471 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 266913 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.388098 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.388098 # CPI: Total CPI of All Threads -system.cpu.ipc 2.576666 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.576666 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 400324799 # number of integer regfile reads -system.cpu.int_regfile_writes 170964393 # number of integer regfile writes -system.cpu.fp_regfile_reads 157088507 # number of floating regfile reads -system.cpu.fp_regfile_writes 104631166 # number of floating regfile writes +system.cpu.cpi 0.370907 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.370907 # CPI: Total CPI of All Threads +system.cpu.ipc 2.696092 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.696092 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 403240144 # number of integer regfile reads +system.cpu.int_regfile_writes 171897287 # number of integer regfile writes +system.cpu.fp_regfile_reads 157938395 # number of floating regfile reads +system.cpu.fp_regfile_writes 105579710 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 7854226 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 5074 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5074 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 670 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3200 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3200 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8166 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9052 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 17218 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311104 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 572416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 572416 # Total data (bytes) +system.cpu.toL2Bus.throughput 8238478 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 5089 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5089 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 674 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3203 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3203 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8182 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9076 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 17258 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 573824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 573824 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 5142000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 5157000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6782500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6787250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6677500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6699750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 2155 # number of replacements -system.cpu.icache.tags.tagsinuse 1832.273556 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 50871213 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4083 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12459.273328 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2164 # number of replacements +system.cpu.icache.tags.tagsinuse 1832.364341 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 51272145 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4091 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12532.912491 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1832.273556 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.894665 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.894665 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1928 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 137 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1338 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 101758059 # Number of tag accesses -system.cpu.icache.tags.data_accesses 101758059 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 50871213 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 50871213 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 50871213 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 50871213 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 50871213 # number of overall hits -system.cpu.icache.overall_hits::total 50871213 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5775 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5775 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5775 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5775 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5775 # number of overall misses -system.cpu.icache.overall_misses::total 5775 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 343384000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 343384000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 343384000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 343384000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 343384000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 343384000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 50876988 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 50876988 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 50876988 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 50876988 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 50876988 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 50876988 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000114 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000114 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000114 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000114 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000114 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000114 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59460.432900 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 59460.432900 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 59460.432900 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 59460.432900 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 59460.432900 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 59460.432900 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 389 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 400 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 55.571429 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 400 # average number of cycles each access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1832.364341 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894709 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894709 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1927 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 294 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1343 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.940918 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 102559737 # Number of tag accesses +system.cpu.icache.tags.data_accesses 102559737 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 51272145 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 51272145 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 51272145 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 51272145 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 51272145 # number of overall hits +system.cpu.icache.overall_hits::total 51272145 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5678 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5678 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5678 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5678 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5678 # number of overall misses +system.cpu.icache.overall_misses::total 5678 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 339990499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 339990499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 339990499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 339990499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 339990499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 339990499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 51277823 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 51277823 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 51277823 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 51277823 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 51277823 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 51277823 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000111 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000111 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000111 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000111 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000111 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000111 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59878.566221 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 59878.566221 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 59878.566221 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 59878.566221 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 59878.566221 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 59878.566221 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 528 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 58.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1692 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1692 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1692 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1692 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1692 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1692 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4083 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4083 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4083 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4083 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4083 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4083 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 250419500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 250419500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 250419500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 250419500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 250419500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 250419500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1587 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1587 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1587 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1587 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1587 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1587 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4091 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4091 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4091 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4091 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4091 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4091 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249912250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 249912250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249912250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 249912250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249912250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 249912250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61332.231203 # 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average overall mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3462 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3996 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7458 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3462 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3996 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7458 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 195634750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54618250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 250253000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 193410500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 193410500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195634750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 248028750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 443663500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195634750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 248028750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 443663500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867735 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.850462 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.977209 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.977209 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.951202 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.899421 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.951202 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.899421 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56509.170999 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63069.572748 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57821.857671 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61792.492013 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61792.492013 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56509.170999 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62069.256757 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59488.267632 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56509.170999 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62069.256757 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59488.267632 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 790 # number of replacements -system.cpu.dcache.tags.tagsinuse 3294.829760 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 158529737 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4191 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37826.231687 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 798 # number of replacements +system.cpu.dcache.tags.tagsinuse 3297.113069 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 156873476 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4201 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37341.936682 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3294.829760 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.804402 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.804402 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3401 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 3297.113069 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.804959 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.804959 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3403 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 3117 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.830322 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 317106037 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 317106037 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 85028391 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 85028391 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501342 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501342 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 158529733 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 158529733 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 158529733 # number of overall hits -system.cpu.dcache.overall_hits::total 158529733 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1799 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1799 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19387 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19387 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21186 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21186 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21186 # number of overall misses -system.cpu.dcache.overall_misses::total 21186 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 115077500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 115077500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1124516028 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1124516028 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1239593528 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1239593528 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1239593528 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1239593528 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 85030190 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 85030190 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.830811 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 313794583 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 313794583 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 83372633 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 83372633 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73500836 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73500836 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 7 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 7 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 156873469 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 156873469 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 156873469 # number of overall hits +system.cpu.dcache.overall_hits::total 156873469 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1822 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1822 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19893 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19893 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21715 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21715 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21715 # number of overall misses +system.cpu.dcache.overall_misses::total 21715 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 114614250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 114614250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1125204835 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1125204835 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1239819085 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1239819085 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1239819085 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1239819085 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 83374455 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 83374455 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 158550919 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 158550919 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 158550919 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 158550919 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000264 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000264 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000134 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000134 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000134 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000134 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63967.481934 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63967.481934 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58003.612111 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 58003.612111 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 58510.031530 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 58510.031530 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 58510.031530 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 58510.031530 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 44616 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 797 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.979925 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 7 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 7 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 156895184 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 156895184 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 156895184 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 156895184 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000271 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000271 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000138 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000138 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000138 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000138 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62905.735456 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62905.735456 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56562.853014 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56562.853014 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 57095.053419 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 57095.053419 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 57095.053419 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 57095.053419 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 46429 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 61 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 948 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.975738 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 61 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 670 # number of writebacks -system.cpu.dcache.writebacks::total 670 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 808 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 808 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16187 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16187 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 16995 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 16995 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 16995 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 16995 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 991 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 991 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3200 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3200 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4191 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4191 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4191 # 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number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 824 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 824 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16690 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16690 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17514 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17514 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17514 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17514 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 998 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 998 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3203 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3203 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4201 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4201 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4201 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4201 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67699250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 67699250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 236024500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 236024500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 303723750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 303723750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 303723750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 303723750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68443.995964 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68443.995964 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73441.406250 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73441.406250 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72259.723216 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72259.723216 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72259.723216 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72259.723216 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67834.919840 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67834.919840 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73688.573213 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73688.573213 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72297.964770 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72297.964770 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72297.964770 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72297.964770 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt index 4cd29aa5b..bde0ba631 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.199332 # Nu sim_ticks 199332411500 # Number of ticks simulated final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2589605 # Simulator instruction rate (inst/s) -host_op_rate 2589605 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1294803220 # Simulator tick rate (ticks/s) -host_mem_usage 262692 # Number of bytes of host memory used -host_seconds 153.95 # Real time elapsed on the host +host_inst_rate 3159999 # Simulator instruction rate (inst/s) +host_op_rate 3159998 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1579999901 # Simulator tick rate (ticks/s) +host_mem_usage 261616 # Number of bytes of host memory used +host_seconds 126.16 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -96,10 +96,10 @@ system.cpu.not_idle_fraction 1 # Pe system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 44587532 # Number of branches fetched system.cpu.op_class::No_OpClass 23123356 5.80% 5.80% # Class of executed instruction -system.cpu.op_class::IntAlu 145805196 36.57% 42.37% # Class of executed instruction -system.cpu.op_class::IntMult 2124322 0.53% 42.91% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 42.91% # Class of executed instruction -system.cpu.op_class::FloatAdd 31467419 7.89% 50.80% # Class of executed instruction +system.cpu.op_class::IntAlu 141652555 35.53% 41.33% # Class of executed instruction +system.cpu.op_class::IntMult 2124322 0.53% 41.86% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 41.86% # Class of executed instruction +system.cpu.op_class::FloatAdd 35620060 8.93% 50.80% # Class of executed instruction system.cpu.op_class::FloatCmp 7072549 1.77% 52.57% # Class of executed instruction system.cpu.op_class::FloatCvt 2735231 0.69% 53.26% # Class of executed instruction system.cpu.op_class::FloatMult 16498021 4.14% 57.40% # Class of executed instruction diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index c52832ea0..f8ab96a0a 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.567335 # Nu sim_ticks 567335093000 # Number of ticks simulated final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1080224 # Simulator instruction rate (inst/s) -host_op_rate 1080224 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1537254294 # Simulator tick rate (ticks/s) -host_mem_usage 271408 # Number of bytes of host memory used -host_seconds 369.06 # Real time elapsed on the host +host_inst_rate 1556013 # Simulator instruction rate (inst/s) +host_op_rate 1556013 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2214344764 # Simulator tick rate (ticks/s) +host_mem_usage 270340 # Number of bytes of host memory used +host_seconds 256.21 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -102,10 +102,10 @@ system.cpu.not_idle_fraction 1 # Pe system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 44587535 # Number of branches fetched system.cpu.op_class::No_OpClass 23123356 5.80% 5.80% # Class of executed instruction -system.cpu.op_class::IntAlu 145805208 36.57% 42.37% # Class of executed instruction -system.cpu.op_class::IntMult 2124322 0.53% 42.91% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 42.91% # Class of executed instruction -system.cpu.op_class::FloatAdd 31467419 7.89% 50.80% # Class of executed instruction +system.cpu.op_class::IntAlu 141652567 35.53% 41.33% # Class of executed instruction +system.cpu.op_class::IntMult 2124322 0.53% 41.86% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 41.86% # Class of executed instruction +system.cpu.op_class::FloatAdd 35620060 8.93% 50.80% # Class of executed instruction system.cpu.op_class::FloatCmp 7072549 1.77% 52.57% # Class of executed instruction system.cpu.op_class::FloatCvt 2735231 0.69% 53.26% # Class of executed instruction system.cpu.op_class::FloatMult 16498021 4.14% 57.40% # Class of executed instruction diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 0a05ac469..73979cce4 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,560 +1,58 @@ ---------- Begin Simulation Statistics ---------- -final_tick 227445516000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -host_inst_rate 153700 # Simulator instruction rate (inst/s) -host_mem_usage 303376 # Number of bytes of host memory used -host_op_rate 196498 # Simulator op (including micro ops) rate (op/s) -host_seconds 1776.44 # Real time elapsed on the host -host_tick_rate 128034740 # Simulator tick rate (ticks/s) +sim_seconds 0.212377 # Number of seconds simulated +sim_ticks 212377413000 # Number of ticks simulated +final_tick 212377413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 273037854 # Number of instructions simulated -sim_ops 349065592 # Number of ops (including micro ops) simulated -sim_seconds 0.227446 # Number of seconds simulated -sim_ticks 227445516000 # Number of ticks simulated +host_inst_rate 166098 # Simulator instruction rate (inst/s) +host_op_rate 199419 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 129195965 # Simulator tick rate (ticks/s) +host_mem_usage 326468 # Number of bytes of host memory used +host_seconds 1643.84 # Real time elapsed on the host +sim_insts 273037856 # Number of instructions simulated +sim_ops 327812213 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.362247 # BTB Hit Percentage -system.cpu.branchPred.BTBHits 16723894 # Number of BTB hits -system.cpu.branchPred.BTBLookups 20061712 # Number of BTB lookups -system.cpu.branchPred.RASInCorrect 121 # Number of incorrect RAS predictions. -system.cpu.branchPred.condIncorrect 1671536 # Number of conditional branches incorrect -system.cpu.branchPred.condPredicted 21059526 # Number of conditional branches predicted -system.cpu.branchPred.lookups 35363260 # Number of BP lookups -system.cpu.branchPred.usedRAS 6617396 # Number of times the RAS was used to get a target. -system.cpu.committedInsts 273037854 # Number of instructions committed -system.cpu.committedOps 349065592 # Number of ops (including micro ops) committed -system.cpu.cpi 1.666037 # CPI: cycles per instruction -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 10895 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 10895 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses::cpu.inst 95145110 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 95145110 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61749.740048 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61749.740048 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61620.734497 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61620.734497 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits::cpu.inst 95143025 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 95143025 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 128748208 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 128748208 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::cpu.inst 2085 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2085 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 424 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 102352040 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 102352040 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000017 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1661 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1661 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::cpu.inst 10895 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68469.206380 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 68469.206380 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68654.108392 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68654.108392 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits::cpu.inst 82047473 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047473 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 356313750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 356313750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000063 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000063 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::cpu.inst 5204 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5204 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2344 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2344 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 196350750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 196350750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2860 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2860 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::cpu.inst 177197787 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 177197787 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66547.120044 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66547.120044 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66070.070781 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66070.070781 # average overall mshr miss latency -system.cpu.dcache.demand_hits::cpu.inst 177190498 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 177190498 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::cpu.inst 485061958 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 485061958 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000041 # miss rate for demand accesses -system.cpu.dcache.demand_misses::cpu.inst 7289 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7289 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::cpu.inst 2768 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2768 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 298702790 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 298702790 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::cpu.inst 4521 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4521 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses::cpu.inst 177197787 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 177197787 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66547.120044 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66547.120044 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66070.070781 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66070.070781 # average overall mshr miss latency -system.cpu.dcache.overall_hits::cpu.inst 177190498 # number of overall hits -system.cpu.dcache.overall_hits::total 177190498 # number of overall hits -system.cpu.dcache.overall_miss_latency::cpu.inst 485061958 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 485061958 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.dcache.overall_misses::cpu.inst 7289 # number of overall misses -system.cpu.dcache.overall_misses::total 7289 # number of overall misses -system.cpu.dcache.overall_mshr_hits::cpu.inst 2768 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2768 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 298702790 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 298702790 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::cpu.inst 4521 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4521 # number of overall MSHR misses -system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 674 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2436 # Occupied blocks per task id -system.cpu.dcache.tags.avg_refs 39197.586375 # Average number of references to valid blocks. -system.cpu.dcache.tags.data_accesses 354443675 # Number of data accesses -system.cpu.dcache.tags.occ_blocks::cpu.inst 3089.554835 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.754286 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.754286 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3161 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.771729 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.replacements 1360 # number of replacements -system.cpu.dcache.tags.sampled_refs 4521 # Sample count of references to valid blocks. -system.cpu.dcache.tags.tag_accesses 354443675 # Number of tag accesses -system.cpu.dcache.tags.tagsinuse 3089.554835 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 177212288 # Total number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks::writebacks 1013 # number of writebacks -system.cpu.dcache.writebacks::total 1013 # number of writebacks -system.cpu.discardedOps 6932970 # Number of ops (including micro ops) which were discarded before commit -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses::cpu.inst 77471042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 77471042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17858.870336 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17858.870336 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15825.006083 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15825.006083 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::cpu.inst 77429612 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 77429612 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::cpu.inst 739892998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 739892998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000535 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000535 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::cpu.inst 41430 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 41430 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 655630002 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 655630002 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000535 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 41430 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 41430 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::cpu.inst 77471042 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 77471042 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17858.870336 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17858.870336 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15825.006083 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15825.006083 # average overall mshr miss latency -system.cpu.icache.demand_hits::cpu.inst 77429612 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 77429612 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::cpu.inst 739892998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 739892998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::cpu.inst 0.000535 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000535 # miss rate for demand accesses -system.cpu.icache.demand_misses::cpu.inst 41430 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 41430 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 655630002 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 655630002 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000535 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::cpu.inst 41430 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 41430 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses::cpu.inst 77471042 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 77471042 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17858.870336 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17858.870336 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15825.006083 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15825.006083 # average overall mshr miss latency -system.cpu.icache.overall_hits::cpu.inst 77429612 # number of overall hits -system.cpu.icache.overall_hits::total 77429612 # number of overall hits -system.cpu.icache.overall_miss_latency::cpu.inst 739892998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 739892998 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::cpu.inst 0.000535 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000535 # miss rate for overall accesses -system.cpu.icache.overall_misses::cpu.inst 41430 # number of overall misses -system.cpu.icache.overall_misses::total 41430 # number of overall misses -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 655630002 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 655630002 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000535 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::cpu.inst 41430 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 41430 # number of overall MSHR misses -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 288 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1478 # Occupied blocks per task id -system.cpu.icache.tags.avg_refs 1868.971300 # Average number of references to valid blocks. -system.cpu.icache.tags.data_accesses 154983513 # Number of data accesses -system.cpu.icache.tags.occ_blocks::cpu.inst 1927.026996 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.940931 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.940931 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1941 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.947754 # Percentage of cache occupancy per task id -system.cpu.icache.tags.replacements 39488 # number of replacements -system.cpu.icache.tags.sampled_refs 41429 # Sample count of references to valid blocks. -system.cpu.icache.tags.tag_accesses 154983513 # Number of tag accesses -system.cpu.icache.tags.tagsinuse 1927.026996 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 77429612 # Total number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.idleCycles 4029946 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.ipc 0.600227 # IPC: instructions per cycle -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2860 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2860 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67967.563291 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67967.563291 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55399.173699 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55399.173699 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits::cpu.inst 16 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 193299750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 193299750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.994406 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.994406 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 2844 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2844 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 157555250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 157555250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994406 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994406 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 2844 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 2844 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 43091 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 43091 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68852.642487 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68852.642487 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56391.699770 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56391.699770 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits::cpu.inst 38266 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 38266 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 332214000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 332214000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.111972 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.111972 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 4825 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4825 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 42 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 269721500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 269721500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.110998 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.110998 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4783 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4783 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses::writebacks 1013 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1013 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits::writebacks 1013 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1013 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses::cpu.inst 45951 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 45951 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68524.416482 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68524.416482 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56021.600892 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56021.600892 # average overall mshr miss latency -system.cpu.l2cache.demand_hits::cpu.inst 38282 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 38282 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::cpu.inst 525513750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 525513750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.166895 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.166895 # miss rate for demand accesses -system.cpu.l2cache.demand_misses::cpu.inst 7669 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7669 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits::cpu.inst 42 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 42 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 427276750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 427276750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.165981 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.165981 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7627 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7627 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses::cpu.inst 45951 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 45951 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68524.416482 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68524.416482 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56021.600892 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56021.600892 # average overall mshr miss latency -system.cpu.l2cache.overall_hits::cpu.inst 38282 # number of overall hits -system.cpu.l2cache.overall_hits::total 38282 # number of overall hits -system.cpu.l2cache.overall_miss_latency::cpu.inst 525513750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 525513750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.166895 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.166895 # miss rate for overall accesses -system.cpu.l2cache.overall_misses::cpu.inst 7669 # number of overall misses -system.cpu.l2cache.overall_misses::total 7669 # number of overall misses -system.cpu.l2cache.overall_mshr_hits::cpu.inst 42 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 42 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 427276750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 427276750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.165981 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.165981 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7627 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7627 # number of overall MSHR misses -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1262 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4305 # Occupied blocks per task id -system.cpu.l2cache.tags.avg_refs 6.727368 # Average number of references to valid blocks. -system.cpu.l2cache.tags.data_accesses 384272 # Number of data accesses -system.cpu.l2cache.tags.occ_blocks::writebacks 356.812936 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3883.048925 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.010889 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.118501 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.129390 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5700 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.173950 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.sampled_refs 5700 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.tag_accesses 384272 # Number of tag accesses -system.cpu.l2cache.tags.tagsinuse 4239.861860 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 38346 # Total number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.numCycles 454891032 # number of cpu cycles simulated -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.tickCycles 450861086 # Number of cycles that the CPU actually ticked -system.cpu.toL2Bus.data_through_bus 3005632 # Total data (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 82859 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10055 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 92914 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 24495000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 62845998 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7514710 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.throughput 13214734 # Throughput (bytes/s) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2651456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 354176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 3005632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.trans_dist::ReadReq 43091 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 43090 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1013 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2860 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2860 # Transaction distribution -system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.membus.data_through_bus 488128 # Total data (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15254 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15254 # Packet count per connected master and slave (bytes) -system.membus.reqLayer0.occupancy 8910000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 71341750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.throughput 2146132 # Throughput (bytes/s) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 488128 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 488128 # Cumulative packet size per connected master and slave (bytes) -system.membus.trans_dist::ReadReq 4783 # Transaction distribution -system.membus.trans_dist::ReadResp 4783 # Transaction distribution -system.membus.trans_dist::ReadExReq 2844 # Transaction distribution -system.membus.trans_dist::ReadExResp 2844 # Transaction distribution -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgGap 29821084.57 # Average gap between requests -system.physmem.avgMemAccLat 25580.41 # Average memory access latency per DRAM burst -system.physmem.avgQLat 6830.41 # Average queueing delay per DRAM burst -system.physmem.avgRdBW 2.15 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.15 # Average system read bandwidth in MiByte/s -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.busUtil 0.02 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.bw_inst_read::cpu.inst 974721 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 974721 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 2146132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2146132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2146132 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2146132 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytesPerActivate::samples 1544 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 315.689119 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 184.950751 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.584238 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 593 38.41% 38.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 326 21.11% 59.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 172 11.14% 70.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 76 4.92% 75.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 71 4.60% 80.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 58 3.76% 83.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 38 2.46% 86.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 28 1.81% 88.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 182 11.79% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1544 # Bytes accessed per row activation -system.physmem.bytesReadDRAM 488128 # Total number of bytes read from DRAM -system.physmem.bytesReadSys 488128 # Total read bytes from the system interface side +system.physmem.bytes_read::cpu.inst 485312 # Number of bytes read from this memory +system.physmem.bytes_read::total 485312 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219008 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 7583 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2285139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2285139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1031221 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1031221 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2285139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2285139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7583 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 7583 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 485312 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 485312 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory -system.physmem.bytes_read::cpu.inst 488128 # Number of bytes read from this memory -system.physmem.bytes_read::total 488128 # Number of bytes read from this memory -system.physmem.memoryStateTime::IDLE 217468466000 # Time in different power states -system.physmem.memoryStateTime::REF 7594860000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 2381096500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.num_reads::cpu.inst 7627 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7627 # Number of read requests responded to by this memory -system.physmem.pageHitRate 79.70 # Row buffer hit rate, read and write combined -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.perBankRdBursts::0 637 # Per bank write bursts -system.physmem.perBankRdBursts::1 850 # Per bank write bursts -system.physmem.perBankRdBursts::2 633 # Per bank write bursts +system.physmem.perBankRdBursts::0 630 # Per bank write bursts +system.physmem.perBankRdBursts::1 843 # Per bank write bursts +system.physmem.perBankRdBursts::2 628 # Per bank write bursts system.physmem.perBankRdBursts::3 541 # Per bank write bursts -system.physmem.perBankRdBursts::4 470 # Per bank write bursts -system.physmem.perBankRdBursts::5 350 # Per bank write bursts -system.physmem.perBankRdBursts::6 175 # Per bank write bursts -system.physmem.perBankRdBursts::7 229 # Per bank write bursts -system.physmem.perBankRdBursts::8 210 # Per bank write bursts -system.physmem.perBankRdBursts::9 309 # Per bank write bursts -system.physmem.perBankRdBursts::10 346 # Per bank write bursts +system.physmem.perBankRdBursts::4 466 # Per bank write bursts +system.physmem.perBankRdBursts::5 349 # Per bank write bursts +system.physmem.perBankRdBursts::6 173 # Per bank write bursts +system.physmem.perBankRdBursts::7 228 # Per bank write bursts +system.physmem.perBankRdBursts::8 209 # Per bank write bursts +system.physmem.perBankRdBursts::9 310 # Per bank write bursts +system.physmem.perBankRdBursts::10 342 # Per bank write bursts system.physmem.perBankRdBursts::11 428 # Per bank write bursts -system.physmem.perBankRdBursts::12 552 # Per bank write bursts -system.physmem.perBankRdBursts::13 714 # Per bank write bursts -system.physmem.perBankRdBursts::14 639 # Per bank write bursts -system.physmem.perBankRdBursts::15 544 # Per bank write bursts +system.physmem.perBankRdBursts::12 554 # Per bank write bursts +system.physmem.perBankRdBursts::13 705 # Per bank write bursts +system.physmem.perBankRdBursts::14 637 # Per bank write bursts +system.physmem.perBankRdBursts::15 540 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -571,9 +69,26 @@ system.physmem.perBankWrBursts::12 0 # Pe system.physmem.perBankWrBursts::13 0 # Per bank write bursts system.physmem.perBankWrBursts::14 0 # Per bank write bursts system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.rdQLenPdf::0 6680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 887 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 212377186000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 7583 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 6625 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -603,22 +118,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.readBursts 7627 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7627 # Read request sizes (log2) -system.physmem.readReqs 7627 # Number of read requests accepted -system.physmem.readRowHitRate 79.70 # Row buffer hit rate for reads -system.physmem.readRowHits 6079 # Number of row buffer hits during reads -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.totBusLat 38135000 # Total ticks spent in databus transfers -system.physmem.totGap 227445412000 # Total gap between requests -system.physmem.totMemAccLat 195101750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totQLat 52095500 # Total ticks spent queuing system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -683,17 +182,518 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.bytesPerActivate::samples 1498 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 322.691589 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.527839 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 333.553355 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 554 36.98% 36.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 333 22.23% 59.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 160 10.68% 69.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 67 4.47% 74.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 72 4.81% 79.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 61 4.07% 83.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 43 2.87% 86.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 33 2.20% 88.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 175 11.68% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1498 # Bytes accessed per row activation +system.physmem.totQLat 52122500 # Total ticks spent queuing +system.physmem.totMemAccLat 194303750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37915000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6873.60 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 25623.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 6077 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.voltage_domain.voltage 1 # Voltage in Volts +system.physmem.readRowHitRate 80.14 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 28007013.85 # Average gap between requests +system.physmem.pageHitRate 80.14 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 202838268250 # Time in different power states +system.physmem.memoryStateTime::REF 7091500000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 2441586750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 2285139 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4730 # Transaction distribution +system.membus.trans_dist::ReadResp 4730 # Transaction distribution +system.membus.trans_dist::ReadExReq 2853 # Transaction distribution +system.membus.trans_dist::ReadExResp 2853 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15166 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15166 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 485312 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 8812000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 70869000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 33146135 # Number of BP lookups +system.cpu.branchPred.condPredicted 17115100 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1582628 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18038083 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15622031 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 86.605827 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6627212 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 191 # Number of system calls +system.cpu.numCycles 424754826 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 273037856 # Number of instructions committed +system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed +system.cpu.discardedOps 4318160 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.555663 # CPI: cycles per instruction +system.cpu.ipc 0.642813 # IPC: instructions per cycle +system.cpu.tickCycles 420995897 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3758929 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 36952 # number of replacements +system.cpu.icache.tags.tagsinuse 1924.941242 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 73208047 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 38889 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1882.487259 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.941242 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939913 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939913 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1488 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 146532763 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146532763 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 73208047 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 73208047 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 73208047 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 73208047 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 73208047 # number of overall hits +system.cpu.icache.overall_hits::total 73208047 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 38890 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 38890 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 38890 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 38890 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 38890 # number of overall misses +system.cpu.icache.overall_misses::total 38890 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 704978746 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 704978746 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 704978746 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 704978746 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 704978746 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 704978746 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 73246937 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 73246937 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 73246937 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 73246937 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 73246937 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 73246937 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000531 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000531 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000531 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000531 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000531 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000531 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18127.506968 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18127.506968 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18127.506968 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18127.506968 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18127.506968 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18127.506968 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38890 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 38890 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 38890 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 38890 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 38890 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 38890 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 625804254 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 625804254 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 625804254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 625804254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 625804254 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 625804254 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000531 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000531 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000531 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16091.649627 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16091.649627 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16091.649627 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16091.649627 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16091.649627 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16091.649627 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 13382365 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 40531 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 40530 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1009 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2869 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2869 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77779 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10029 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 87808 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2488896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 2842112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 2842112 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 23213500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 59031746 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 7495460 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 4198.136947 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 35837 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5644 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.349575 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 353.492029 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.644919 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.010788 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117329 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.128117 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5644 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1251 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4259 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172241 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 363785 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 363785 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 35758 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 35758 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1009 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1009 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 16 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 35774 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 35774 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 35774 # number of overall hits +system.cpu.l2cache.overall_hits::total 35774 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 4773 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4773 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 2853 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2853 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 7626 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7626 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 7626 # number of overall misses +system.cpu.l2cache.overall_misses::total 7626 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 328392750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 328392750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194194500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 194194500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 522587250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 522587250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 522587250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 522587250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 40531 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 40531 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1009 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1009 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2869 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2869 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 43400 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 43400 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 43400 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 43400 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.117762 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.117762 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.994423 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.994423 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.175714 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.175714 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.175714 # 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mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.174724 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174724 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.174724 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56388.900634 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56388.900634 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55514.195584 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55514.195584 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56059.804827 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56059.804827 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56059.804827 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56059.804827 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.tags.replacements 1353 # number of replacements +system.cpu.dcache.tags.tagsinuse 3085.890933 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168774540 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4510 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37422.292683 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 3085.890933 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.753391 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.753391 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 671 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2433 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 337568172 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337568172 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 86705299 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86705299 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 82047451 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047451 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 10895 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.inst 10895 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.inst 168752750 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168752750 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 168752750 # number of overall hits +system.cpu.dcache.overall_hits::total 168752750 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 2065 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2065 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 5226 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5226 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 7291 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7291 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 7291 # number of overall misses +system.cpu.dcache.overall_misses::total 7291 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 127204208 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 127204208 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 358851000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 358851000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 486055208 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 486055208 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 486055208 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 486055208 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 86707364 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86707364 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 10895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 168760041 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168760041 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 168760041 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168760041 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000064 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.000043 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61600.100726 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61600.100726 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68666.475316 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 68666.475316 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66665.095049 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66665.095049 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66665.095049 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66665.095049 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 1009 # number of writebacks +system.cpu.dcache.writebacks::total 1009 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 424 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2357 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2357 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 2781 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2781 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 2781 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2781 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1641 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1641 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2869 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2869 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 4510 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4510 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 4510 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4510 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100713040 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 100713040 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197262500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 197262500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297975540 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 297975540 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297975540 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 297975540 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61372.967703 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61372.967703 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68756.535378 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68756.535378 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66069.964523 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66069.964523 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66069.964523 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66069.964523 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index dff7f3d85..6d48708ce 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.064767 # Number of seconds simulated -sim_ticks 64766858000 # Number of ticks simulated -final_tick 64766858000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058843 # Number of seconds simulated +sim_ticks 58842982000 # Number of ticks simulated +final_tick 58842982000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139181 # Simulator instruction rate (inst/s) -host_op_rate 177937 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33015138 # Simulator tick rate (ticks/s) -host_mem_usage 270440 # Number of bytes of host memory used -host_seconds 1961.73 # Real time elapsed on the host -sim_insts 273036725 # Number of instructions simulated -sim_ops 349064449 # Number of ops (including micro ops) simulated +host_inst_rate 157851 # Simulator instruction rate (inst/s) +host_op_rate 189517 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34018873 # Simulator tick rate (ticks/s) +host_mem_usage 327492 # Number of bytes of host memory used +host_seconds 1729.72 # Real time elapsed on the host +sim_insts 273036656 # Number of instructions simulated +sim_ops 327810999 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 194688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272960 # Number of bytes read from this memory -system.physmem.bytes_read::total 467648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 194688 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 194688 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3042 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4265 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7307 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3005982 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4214501 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7220483 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3005982 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3005982 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3005982 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4214501 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7220483 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7307 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 189376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272128 # Number of bytes read from this memory +system.physmem.bytes_read::total 461504 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 189376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 189376 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2959 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4252 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7211 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 3218328 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4624647 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7842974 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3218328 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3218328 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3218328 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4624647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7842974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7211 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7307 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7211 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 467648 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 461504 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 467648 # Total read bytes from the system interface side +system.physmem.bytesReadSys 461504 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 604 # Per bank write bursts -system.physmem.perBankRdBursts::1 805 # Per bank write bursts -system.physmem.perBankRdBursts::2 608 # Per bank write bursts -system.physmem.perBankRdBursts::3 526 # Per bank write bursts -system.physmem.perBankRdBursts::4 446 # Per bank write bursts -system.physmem.perBankRdBursts::5 361 # Per bank write bursts -system.physmem.perBankRdBursts::6 162 # Per bank write bursts -system.physmem.perBankRdBursts::7 221 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 11 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 592 # Per bank write bursts +system.physmem.perBankRdBursts::1 792 # Per bank write bursts +system.physmem.perBankRdBursts::2 603 # Per bank write bursts +system.physmem.perBankRdBursts::3 519 # Per bank write bursts +system.physmem.perBankRdBursts::4 437 # Per bank write bursts +system.physmem.perBankRdBursts::5 342 # Per bank write bursts +system.physmem.perBankRdBursts::6 159 # Per bank write bursts +system.physmem.perBankRdBursts::7 228 # Per bank write bursts system.physmem.perBankRdBursts::8 208 # Per bank write bursts -system.physmem.perBankRdBursts::9 290 # Per bank write bursts -system.physmem.perBankRdBursts::10 326 # Per bank write bursts -system.physmem.perBankRdBursts::11 415 # Per bank write bursts -system.physmem.perBankRdBursts::12 530 # Per bank write bursts -system.physmem.perBankRdBursts::13 688 # Per bank write bursts -system.physmem.perBankRdBursts::14 613 # Per bank write bursts +system.physmem.perBankRdBursts::9 292 # Per bank write bursts +system.physmem.perBankRdBursts::10 317 # Per bank write bursts +system.physmem.perBankRdBursts::11 409 # Per bank write bursts +system.physmem.perBankRdBursts::12 526 # Per bank write bursts +system.physmem.perBankRdBursts::13 671 # Per bank write bursts +system.physmem.perBankRdBursts::14 612 # Per bank write bursts system.physmem.perBankRdBursts::15 504 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 64766656000 # Total gap between requests +system.physmem.totGap 58842848000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7307 # Read request sizes (log2) +system.physmem.readPktSize::6 7211 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4265 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 623 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 229 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 69 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4240 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2012 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 646 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 244 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1462 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 319.430917 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 186.825713 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 340.055999 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 519 35.50% 35.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 381 26.06% 61.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 138 9.44% 71.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 81 5.54% 76.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 49 3.35% 79.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 41 2.80% 82.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 27 1.85% 84.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 24 1.64% 86.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 202 13.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1462 # Bytes accessed per row activation -system.physmem.totQLat 61897500 # Total ticks spent queuing -system.physmem.totMemAccLat 198903750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 36535000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8470.99 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1405 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 327.288256 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 191.332764 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.731237 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 492 35.02% 35.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 350 24.91% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 132 9.40% 69.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 82 5.84% 75.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 53 3.77% 78.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 47 3.35% 82.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 27 1.92% 84.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 22 1.57% 85.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 200 14.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1405 # Bytes accessed per row activation +system.physmem.totQLat 59614750 # Total ticks spent queuing +system.physmem.totMemAccLat 194821000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36055000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8267.20 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27220.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 7.22 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27017.20 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 7.84 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 7.22 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 7.84 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage @@ -216,44 +216,44 @@ system.physmem.busUtilRead 0.06 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5841 # Number of row buffer hits during reads +system.physmem.readRowHits 5798 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.94 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.40 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8863645.27 # Average gap between requests -system.physmem.pageHitRate 79.94 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 60826618500 # Time in different power states -system.physmem.memoryStateTime::REF 2162680000 # Time in different power states +system.physmem.avgGap 8160150.88 # Average gap between requests +system.physmem.pageHitRate 80.40 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 55121576750 # Time in different power states +system.physmem.memoryStateTime::REF 1964820000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1777002750 # Time in different power states +system.physmem.memoryStateTime::ACT 1754568250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 7220483 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4488 # Transaction distribution -system.membus.trans_dist::ReadResp 4488 # Transaction distribution -system.membus.trans_dist::UpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 2819 # Transaction distribution -system.membus.trans_dist::ReadExResp 2819 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14620 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14620 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 467648 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 467648 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 467648 # Total data (bytes) +system.membus.throughput 7842974 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4381 # Transaction distribution +system.membus.trans_dist::ReadResp 4381 # Transaction distribution +system.membus.trans_dist::UpgradeReq 11 # Transaction distribution +system.membus.trans_dist::UpgradeResp 11 # Transaction distribution +system.membus.trans_dist::ReadExReq 2830 # Transaction distribution +system.membus.trans_dist::ReadExResp 2830 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14444 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14444 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 461504 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 461504 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 461504 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8747000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8714000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 67869997 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 67059990 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 36489443 # Number of BP lookups -system.cpu.branchPred.condPredicted 21873029 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1677086 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19094793 # Number of BTB lookups -system.cpu.branchPred.BTBHits 17269038 # Number of BTB hits +system.cpu.branchPred.lookups 36678579 # Number of BP lookups +system.cpu.branchPred.condPredicted 19369962 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1628976 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19217639 # Number of BTB lookups +system.cpu.branchPred.BTBHits 17291098 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 90.438467 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7051020 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 13969 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.975142 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7036393 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 5252 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -339,516 +339,519 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 129533717 # number of cpu cycles simulated +system.cpu.numCycles 117685965 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 40065447 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 327212599 # Number of instructions fetch has processed -system.cpu.fetch.Branches 36489443 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24320058 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 72959266 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8220576 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 9614052 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 94 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1657 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 76 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 38688978 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 553522 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 129167933 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.246487 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.483221 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 40172132 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 329927106 # Number of instructions fetch has processed +system.cpu.fetch.Branches 36678579 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24327491 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 75600101 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3327960 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 175 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2800 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 38768855 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 530996 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 117439229 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.389931 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.437439 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 56843632 44.01% 44.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6961373 5.39% 49.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5946764 4.60% 54.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6307392 4.88% 58.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 5037669 3.90% 62.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4117601 3.19% 65.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3252291 2.52% 68.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4297115 3.33% 71.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36404096 28.18% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 46731814 39.79% 39.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 7329854 6.24% 46.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6574514 5.60% 51.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6398088 5.45% 57.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4252484 3.62% 60.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5520861 4.70% 65.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3987559 3.40% 68.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3254311 2.77% 71.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 33389744 28.43% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 129167933 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.281698 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.526081 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 43040295 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8294549 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 70704377 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 671384 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6457328 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7532389 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 70819 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 413867422 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 226829 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6457328 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 45867800 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 237018 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 350499 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 68547941 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 7707347 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 406294876 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 117439229 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.311665 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.803453 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 34271331 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16148849 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 61039844 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4384832 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1594373 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7530126 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 70364 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 389722126 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 437543 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1594373 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37031203 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5569218 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 387986 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62601924 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 10254525 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 382340457 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2372159 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1808118 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 3023073 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 35743 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 447044512 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2837901709 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1622364142 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 210216215 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 62478319 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 12155 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 12154 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 14556867 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 106022236 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 93881214 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5184446 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5926802 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 394612578 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 23007 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 378124394 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 2730874 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 45321613 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 166213653 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 887 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 129167933 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.927386 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.138502 # Number of insts issued each cycle +system.cpu.rename.IQFullEvents 4583661 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2043172 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 2989050 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 65700 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 432935056 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2729953830 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 376601971 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 209126886 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 372229219 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 60705837 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 14453 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 15060 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 19856485 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 96101144 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 93882304 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9920575 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10878783 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 370378331 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 25182 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 358744041 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1234352 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 42331510 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 132428138 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3062 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 117439229 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.054721 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.223263 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23289729 18.03% 18.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17219322 13.33% 31.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17000952 13.16% 44.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 16863081 13.06% 57.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 22471092 17.40% 74.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15547625 12.04% 87.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10749417 8.32% 95.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4018790 3.11% 98.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2007925 1.55% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 21274018 18.11% 18.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14280801 12.16% 30.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 14869023 12.66% 42.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13830819 11.78% 54.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 20620243 17.56% 72.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15076681 12.84% 85.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10030176 8.54% 93.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4472440 3.81% 97.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2985028 2.54% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 129167933 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 117439229 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 70479 0.37% 0.37% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4864 0.03% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 116556 0.60% 1.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 10208 0.05% 1.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 2498 0.01% 1.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 1.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 192000 1.00% 2.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 6622 0.03% 2.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 104426 0.54% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 10354293 53.72% 56.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 8412591 43.65% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 30566 0.13% 0.13% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5035 0.02% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 218902 0.91% 1.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 207576 0.86% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 15328 0.06% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 1824 0.01% 1.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 338916 1.41% 3.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 30886 0.13% 3.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 130712 0.54% 4.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.07% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 13684069 56.78% 60.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9438097 39.16% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 127925021 33.83% 33.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2175908 0.58% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 6 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6792348 1.80% 36.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8524841 2.25% 38.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3465145 0.92% 39.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1600581 0.42% 39.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21035851 5.56% 45.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7175261 1.90% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7134800 1.89% 49.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103072110 27.26% 76.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 89047235 23.55% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 114997382 32.06% 32.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2177572 0.61% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6789188 1.89% 34.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8562613 2.39% 36.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3491505 0.97% 37.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1605361 0.45% 38.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 21185799 5.91% 44.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7196318 2.01% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147739 1.99% 48.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 183217 0.05% 48.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 95472748 26.61% 74.93% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 89934599 25.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 378124394 # Type of FU issued -system.cpu.iq.rate 2.919119 # Inst issue rate -system.cpu.iq.fu_busy_cnt 19274540 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.050974 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 653351237 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 300092831 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 252502629 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 254070898 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 139884609 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118704168 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266903131 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 130495803 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12681428 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 358744041 # Type of FU issued +system.cpu.iq.rate 3.048316 # Inst issue rate +system.cpu.iq.fu_busy_cnt 24101911 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.067184 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 600140343 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 274631052 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 231134438 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 260123231 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 138160310 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 119811956 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 246702850 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 136143102 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 13691987 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 11373488 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 85866 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20564 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11505631 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 10368919 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 114059 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 68397 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11506726 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 299397 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2800 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1395971 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 850 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6457328 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4758 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17342 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 394637253 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 715920 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 106022236 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 93881214 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11972 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 602 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17793 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20564 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1298443 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 381522 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1679965 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 373834206 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101210545 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4290188 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1594373 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4558099 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 129859 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 370404619 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1080086 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 96101144 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 93882304 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 14149 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 21825 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 109033 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 68397 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1241378 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 435662 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1677040 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 354745077 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 94263609 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3998964 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1668 # number of nop insts executed -system.cpu.iew.exec_refs 189079864 # number of memory reference insts executed -system.cpu.iew.exec_branches 32211788 # Number of branches executed -system.cpu.iew.exec_stores 87869319 # Number of stores executed -system.cpu.iew.exec_rate 2.885999 # Inst execution rate -system.cpu.iew.wb_sent 372104883 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 371206797 # cumulative count of insts written-back -system.cpu.iew.wb_producers 194146455 # num instructions producing a value -system.cpu.iew.wb_consumers 400678068 # num instructions consuming a value +system.cpu.iew.exec_nop 1106 # number of nop insts executed +system.cpu.iew.exec_refs 182843438 # number of memory reference insts executed +system.cpu.iew.exec_branches 32405794 # Number of branches executed +system.cpu.iew.exec_stores 88579829 # Number of stores executed +system.cpu.iew.exec_rate 3.014336 # Inst execution rate +system.cpu.iew.wb_sent 352024494 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 350946394 # cumulative count of insts written-back +system.cpu.iew.wb_producers 175212964 # num instructions producing a value +system.cpu.iew.wb_consumers 355804607 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.865716 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.484545 # average fanout of values written-back +system.cpu.iew.wb_rate 2.982058 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.492442 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 45577363 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 42598489 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1607073 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 122710605 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.844620 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.797026 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1559369 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 111323846 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.944667 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.904010 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 31366686 25.56% 25.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 25118346 20.47% 46.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 12977285 10.58% 56.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 10004590 8.15% 64.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11874018 9.68% 74.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 6164142 5.02% 79.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4197962 3.42% 82.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3586787 2.92% 85.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 17420789 14.20% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 29334492 26.35% 26.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 21002495 18.87% 45.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 12438899 11.17% 56.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8843852 7.94% 64.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8943359 8.03% 72.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5286497 4.75% 77.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3580965 3.22% 80.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3438245 3.09% 83.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 18455042 16.58% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 122710605 # Number of insts commited each cycle -system.cpu.commit.committedInsts 273037337 # Number of instructions committed -system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 111323846 # Number of insts commited each cycle +system.cpu.commit.committedInsts 273037268 # Number of instructions committed +system.cpu.commit.committedOps 327811611 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 177024331 # Number of memory references committed -system.cpu.commit.loads 94648748 # Number of loads committed +system.cpu.commit.refs 168107803 # Number of memory references committed +system.cpu.commit.loads 85732225 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 30563497 # Number of branches committed +system.cpu.commit.branches 30563485 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. +system.cpu.commit.int_insts 258331174 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 116648967 33.42% 33.42% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2145845 0.61% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 6594343 1.89% 35.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 35.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 7943502 2.28% 38.20% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 3118180 0.89% 39.09% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 1563217 0.45% 39.54% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 19652356 5.63% 45.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.04% 47.21% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.02% 49.24% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 49.29% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 94648748 27.11% 76.40% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 82375583 23.60% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 104312045 31.82% 31.82% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2145845 0.65% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 85732225 26.15% 74.87% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 82375578 25.13% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 349065061 # Class of committed instruction -system.cpu.commit.bw_lim_events 17420789 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 327811611 # Class of committed instruction +system.cpu.commit.bw_lim_events 18455042 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 499929717 # The number of ROB reads -system.cpu.rob.rob_writes 795751266 # The number of ROB writes -system.cpu.timesIdled 6646 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 365784 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 273036725 # Number of Instructions Simulated -system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.474419 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.474419 # CPI: Total CPI of All Threads -system.cpu.ipc 2.107843 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.107843 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1785673756 # number of integer regfile reads -system.cpu.int_regfile_writes 235086257 # number of integer regfile writes -system.cpu.fp_regfile_reads 188627632 # number of floating regfile reads -system.cpu.fp_regfile_writes 133402932 # number of floating regfile writes -system.cpu.misc_regfile_reads 1210936846 # number of misc regfile reads +system.cpu.rob.rob_reads 463276381 # The number of ROB reads +system.cpu.rob.rob_writes 746948197 # The number of ROB writes +system.cpu.timesIdled 5570 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 246736 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 273036656 # Number of Instructions Simulated +system.cpu.committedOps 327810999 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.431026 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.431026 # CPI: Total CPI of All Threads +system.cpu.ipc 2.320044 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.320044 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 344698387 # number of integer regfile reads +system.cpu.int_regfile_writes 141985623 # number of integer regfile writes +system.cpu.fp_regfile_reads 189510679 # number of floating regfile reads +system.cpu.fp_regfile_writes 134618624 # number of floating regfile writes +system.cpu.cc_regfile_reads 1340695625 # number of cc regfile reads +system.cpu.cc_regfile_writes 80827327 # number of cc regfile writes +system.cpu.misc_regfile_reads 1216328122 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.toL2Bus.throughput 21331404 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 17706 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 17706 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1042 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2839 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2839 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31825 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10310 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 42135 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1018304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 363072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 1381376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 1381376 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 11837000 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 23209157 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 17471 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 17471 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1022 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2846 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2846 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31432 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10234 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 41666 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1005376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 359424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 1364800 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 1364800 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 896 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 11697999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24407489 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24104992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7420712 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7380470 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 14019 # number of replacements -system.cpu.icache.tags.tagsinuse 1852.281625 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 38671572 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15912 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 2430.340121 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 13841 # number of replacements +system.cpu.icache.tags.tagsinuse 1830.861112 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 38751311 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15711 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2466.508243 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1852.281625 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.904434 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.904434 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1893 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1830.861112 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.893975 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.893975 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1870 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 208 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1526 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.924316 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 77393866 # Number of tag accesses -system.cpu.icache.tags.data_accesses 77393866 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 38671572 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 38671572 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 38671572 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 38671572 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 38671572 # number of overall hits -system.cpu.icache.overall_hits::total 38671572 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17404 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17404 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17404 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17404 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17404 # number of overall misses -system.cpu.icache.overall_misses::total 17404 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 452089736 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 452089736 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 452089736 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 452089736 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 452089736 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 452089736 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 38688976 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 38688976 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 38688976 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 38688976 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 38688976 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 38688976 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000450 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000450 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000450 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000450 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000450 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000450 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25976.197196 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25976.197196 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25976.197196 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25976.197196 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25976.197196 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25976.197196 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1041 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1522 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.913086 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 77553427 # Number of tag accesses +system.cpu.icache.tags.data_accesses 77553427 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 38751328 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 38751328 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 38751328 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 38751328 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 38751328 # number of overall hits +system.cpu.icache.overall_hits::total 38751328 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17524 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17524 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17524 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17524 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17524 # number of overall misses +system.cpu.icache.overall_misses::total 17524 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 439561740 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 439561740 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 439561740 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 439561740 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 439561740 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 439561740 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 38768852 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 38768852 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 38768852 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 38768852 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 38768852 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 38768852 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000452 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000452 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000452 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000452 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000452 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000452 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25083.413604 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25083.413604 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25083.413604 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25083.413604 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25083.413604 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25083.413604 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 684 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 47.318182 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1490 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1490 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1490 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1490 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1490 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1490 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15914 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15914 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15914 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15914 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15914 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15914 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 359079759 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 359079759 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 359079759 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 359079759 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 359079759 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 359079759 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000411 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000411 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000411 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000411 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000411 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000411 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22563.765175 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22563.765175 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22563.765175 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22563.765175 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22563.765175 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22563.765175 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1801 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1801 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1801 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1801 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1801 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1801 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15723 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15723 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15723 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15723 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15723 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15723 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 350218008 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 350218008 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 350218008 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 350218008 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 350218008 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 350218008 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000406 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000406 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000406 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000406 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000406 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000406 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22274.248426 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22274.248426 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22274.248426 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22274.248426 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22274.248426 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22274.248426 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3952.099762 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 13258 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5413 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.449289 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3837.051468 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 13121 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5294 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.478466 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 379.383220 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2782.580366 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 790.136176 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011578 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084918 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.024113 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.120609 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5413 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1243 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4021 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.165192 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 180948 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 180948 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 12858 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 305 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13163 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1042 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1042 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 20 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 20 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12858 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 325 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13183 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12858 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 325 # number of overall hits -system.cpu.l2cache.overall_hits::total 13183 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3053 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1487 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4540 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 2819 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2819 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3053 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 4306 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7359 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3053 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 4306 # number of overall misses -system.cpu.l2cache.overall_misses::total 7359 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 214550000 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.813501 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250960 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.916667 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.916667 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994378 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994378 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188363 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.925555 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.355169 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188363 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.925555 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.355169 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57247.127408 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60975.386779 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58457.258617 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10182.636364 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10182.636364 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59183.127208 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59183.127208 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57247.127408 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59782.514111 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58742.130079 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57247.127408 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59782.514111 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58742.130079 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1426 # number of replacements -system.cpu.dcache.tags.tagsinuse 3109.599416 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 170089338 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4631 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 36728.425394 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1384 # number of replacements +system.cpu.dcache.tags.tagsinuse 3114.575432 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 161730326 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4594 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 35204.685677 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3109.599416 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.759180 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.759180 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3205 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 3114.575432 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.760394 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.760394 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3210 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 688 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 686 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2446 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.782471 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 340235219 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 340235219 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 88036573 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88036573 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82030829 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82030829 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11027 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11027 # number of LoadLockedReq hits +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2462 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.783691 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 323517792 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 323517792 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 79590771 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 79590771 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82030417 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82030417 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 87045 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 87045 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11127 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11127 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 170067402 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 170067402 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 170067402 # number of overall hits -system.cpu.dcache.overall_hits::total 170067402 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4132 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4132 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 21836 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 21836 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 161621188 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 161621188 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 161708233 # number of overall hits +system.cpu.dcache.overall_hits::total 161708233 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4059 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4059 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22243 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22243 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 40 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 40 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25968 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25968 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25968 # number of overall misses -system.cpu.dcache.overall_misses::total 25968 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 240617705 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 240617705 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1280155018 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1280155018 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 26302 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 26302 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 26342 # number of overall misses +system.cpu.dcache.overall_misses::total 26342 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 234715222 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 234715222 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1291834537 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1291834537 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170250 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 170250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1520772723 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1520772723 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1520772723 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1520772723 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88040705 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88040705 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11029 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11029 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 1526549759 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1526549759 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1526549759 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1526549759 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 79594830 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 79594830 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 82052660 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 82052660 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 87085 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 87085 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11129 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11129 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 170093370 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 170093370 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 170093370 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 170093370 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000266 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000266 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000181 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000181 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000153 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000153 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000153 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000153 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58232.745644 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58232.745644 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58625.893845 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 58625.893845 # average WriteReq miss latency +system.cpu.dcache.demand_accesses::cpu.data 161647490 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 161647490 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 161734575 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 161734575 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000051 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000271 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000271 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000459 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000459 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000180 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000180 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000163 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000163 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000163 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000163 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57825.873861 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 57825.873861 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58078.251000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 58078.251000 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 58563.336530 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 58563.336530 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 58563.336530 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 58563.336530 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 30153 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1162 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 553 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.526221 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 96.833333 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 58039.303437 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 58039.303437 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 57951.171475 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 57951.171475 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32404 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1444 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 548 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 59.131387 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 103.142857 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1042 # number of writebacks -system.cpu.dcache.writebacks::total 1042 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2339 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2339 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18995 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18995 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1022 # number of writebacks +system.cpu.dcache.writebacks::total 1022 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2332 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2332 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19388 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 19388 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 21334 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 21334 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 21334 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 21334 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1793 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1793 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2841 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2841 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4634 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4634 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4634 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4634 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 115097041 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 115097041 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 203424247 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 203424247 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 318521288 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 318521288 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 318521288 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 318521288 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 21720 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 21720 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 21720 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 21720 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1727 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2855 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2855 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 24 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 24 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4582 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4582 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4606 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4606 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109924790 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 109924790 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 205574740 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 205574740 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1745000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1745000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 315499530 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 315499530 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 317244530 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 317244530 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64192.437814 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64192.437814 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71603.043647 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71603.043647 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68735.711696 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68735.711696 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68735.711696 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68735.711696 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000276 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000276 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000028 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000028 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63650.718008 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63650.718008 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72005.162872 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72005.162872 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 72708.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 72708.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68856.292012 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68856.292012 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68876.363439 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68876.363439 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index edb370512..d78fd5112 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.212344 # Number of seconds simulated -sim_ticks 212344043000 # Number of ticks simulated -final_tick 212344043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.201717 # Number of seconds simulated +sim_ticks 201717313500 # Number of ticks simulated +final_tick 201717313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1152169 # Simulator instruction rate (inst/s) -host_op_rate 1472992 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 896053064 # Simulator tick rate (ticks/s) -host_mem_usage 309060 # Number of bytes of host memory used -host_seconds 236.98 # Real time elapsed on the host -sim_insts 273037663 # Number of instructions simulated -sim_ops 349065399 # Number of ops (including micro ops) simulated +host_inst_rate 1169681 # Simulator instruction rate (inst/s) +host_op_rate 1404332 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 864148101 # Simulator tick rate (ticks/s) +host_mem_usage 314684 # Number of bytes of host memory used +host_seconds 233.43 # Real time elapsed on the host +sim_insts 273037594 # Number of instructions simulated +sim_ops 327811949 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 1394641404 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 480709268 # Number of bytes read from this memory -system.physmem.bytes_read::total 1875350672 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1394641404 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1394641404 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 400047783 # Number of bytes written to this memory -system.physmem.bytes_written::total 400047783 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 348660351 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 94582505 # Number of read requests responded to by this memory -system.physmem.num_reads::total 443242856 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 82063572 # Number of write requests responded to by this memory -system.physmem.num_writes::total 82063572 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6567838609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2263822715 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8831661324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6567838609 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6567838609 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1883960470 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1883960470 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6567838609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4147783185 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10715621794 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 10715621794 # Throughput (bytes/s) -system.membus.data_through_bus 2275398455 # Total data (bytes) +system.physmem.bytes_read::cpu.inst 1394641092 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 480709216 # Number of bytes read from this memory +system.physmem.bytes_read::total 1875350308 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1394641092 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1394641092 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 400047763 # Number of bytes written to this memory +system.physmem.bytes_written::total 400047763 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 348660273 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 86300511 # Number of read requests responded to by this memory +system.physmem.num_reads::total 434960784 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 82063567 # Number of write requests responded to by this memory +system.physmem.num_writes::total 82063567 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 6913839312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2383083572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9296922884 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6913839312 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6913839312 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1983209850 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1983209850 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6913839312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4366293422 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11280132734 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 11280132734 # Throughput (bytes/s) +system.membus.data_through_bus 2275398071 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -124,63 +124,65 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 424688087 # number of cpu cycles simulated +system.cpu.numCycles 403434628 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 273037663 # Number of instructions committed -system.cpu.committedOps 349065399 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 279584918 # Number of integer alu accesses +system.cpu.committedInsts 273037594 # Number of instructions committed +system.cpu.committedOps 327811949 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 258331481 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses system.cpu.num_func_calls 12448615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18105897 # number of instructions that are conditional controls -system.cpu.num_int_insts 279584918 # number of integer instructions +system.cpu.num_conditional_control_insts 15799338 # number of instructions that are conditional controls +system.cpu.num_int_insts 258331481 # number of integer instructions system.cpu.num_fp_insts 114216705 # number of float instructions -system.cpu.num_int_register_reads 2254222459 # number of times the integer registers were read -system.cpu.num_int_register_writes 251197905 # number of times the integer registers were written +system.cpu.num_int_register_reads 1174407516 # number of times the integer registers were read +system.cpu.num_int_register_writes 162499657 # number of times the integer registers were written system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written -system.cpu.num_mem_refs 177024356 # number of memory refs -system.cpu.num_load_insts 94648757 # Number of load instructions -system.cpu.num_store_insts 82375599 # Number of store instructions +system.cpu.num_cc_register_reads 985884623 # number of times the CC registers were read +system.cpu.num_cc_register_writes 76361749 # number of times the CC registers were written +system.cpu.num_mem_refs 168107829 # number of memory refs +system.cpu.num_load_insts 85732235 # Number of load instructions +system.cpu.num_store_insts 82375594 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 424688087 # Number of busy cycles +system.cpu.num_busy_cycles 403434628 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 30563502 # Number of branches fetched +system.cpu.Branches 30563490 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 116649415 33.42% 33.42% # Class of executed instruction -system.cpu.op_class::IntMult 2145905 0.61% 34.03% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 6594343 1.89% 35.92% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 35.92% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 7943502 2.28% 38.20% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 3118180 0.89% 39.09% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 1563217 0.45% 39.54% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 19652356 5.63% 45.17% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 7136937 2.04% 47.21% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 7062098 2.02% 49.24% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 175285 0.05% 49.29% # Class of executed instruction -system.cpu.op_class::MemRead 94648757 27.11% 76.40% # Class of executed instruction -system.cpu.op_class::MemWrite 82375599 23.60% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 104312492 31.82% 31.82% # Class of executed instruction +system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction +system.cpu.op_class::MemRead 85732235 26.15% 74.87% # Class of executed instruction +system.cpu.op_class::MemWrite 82375594 25.13% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 349065594 # Class of executed instruction +system.cpu.op_class::total 327812144 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 23ba68f1d..57cca8ea4 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.525834 # Number of seconds simulated -sim_ticks 525834342000 # Number of ticks simulated -final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.517235 # Number of seconds simulated +sim_ticks 517235411000 # Number of ticks simulated +final_tick 517235411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 605985 # Simulator instruction rate (inst/s) -host_op_rate 774729 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1168322503 # Simulator tick rate (ticks/s) -host_mem_usage 318808 # Number of bytes of host memory used -host_seconds 450.08 # Real time elapsed on the host -sim_insts 272739283 # Number of instructions simulated -sim_ops 348687122 # Number of ops (including micro ops) simulated +host_inst_rate 749544 # Simulator instruction rate (inst/s) +host_op_rate 899855 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1421469107 # Simulator tick rate (ticks/s) +host_mem_usage 324416 # Number of bytes of host memory used +host_seconds 363.87 # Real time elapsed on the host +sim_insts 272739285 # Number of instructions simulated +sim_ops 327433743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory @@ -21,15 +21,15 @@ system.physmem.bytes_inst_read::total 166976 # Nu system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 317545 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 513987 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 831532 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 317545 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317545 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 317545 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 513987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 831532 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 831532 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 322824 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 522532 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 845356 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 322824 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 322824 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 322824 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 522532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 845356 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3976 # Transaction distribution system.membus.trans_dist::ReadResp 3976 # Transaction distribution system.membus.trans_dist::ReadExReq 2856 # Transaction distribution @@ -40,9 +40,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 437248 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6832000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 61488000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -130,73 +130,75 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 1051668684 # number of cpu cycles simulated +system.cpu.numCycles 1034470822 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 272739283 # Number of instructions committed -system.cpu.committedOps 348687122 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 279584917 # Number of integer alu accesses +system.cpu.committedInsts 272739285 # Number of instructions committed +system.cpu.committedOps 327433743 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses system.cpu.num_func_calls 12448615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18105896 # number of instructions that are conditional controls -system.cpu.num_int_insts 279584917 # number of integer instructions +system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls +system.cpu.num_int_insts 258331537 # number of integer instructions system.cpu.num_fp_insts 114216705 # number of float instructions -system.cpu.num_int_register_reads 2579483474 # number of times the integer registers were read -system.cpu.num_int_register_writes 251197902 # number of times the integer registers were written +system.cpu.num_int_register_reads 1215888421 # number of times the integer registers were read +system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written -system.cpu.num_mem_refs 177024356 # number of memory refs -system.cpu.num_load_insts 94648757 # Number of load instructions +system.cpu.num_cc_register_reads 1242915500 # number of times the CC registers were read +system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written +system.cpu.num_mem_refs 168107847 # number of memory refs +system.cpu.num_load_insts 85732248 # Number of load instructions system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1051668684 # Number of busy cycles +system.cpu.num_busy_cycles 1034470822 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 30563501 # Number of branches fetched +system.cpu.Branches 30563502 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 116649413 33.42% 33.42% # Class of executed instruction -system.cpu.op_class::IntMult 2145905 0.61% 34.03% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 6594343 1.89% 35.92% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 35.92% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 7943502 2.28% 38.20% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 3118180 0.89% 39.09% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 1563217 0.45% 39.54% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 19652356 5.63% 45.17% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 7136937 2.04% 47.21% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 7062098 2.02% 49.24% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 175285 0.05% 49.29% # Class of executed instruction -system.cpu.op_class::MemRead 94648757 27.11% 76.40% # Class of executed instruction -system.cpu.op_class::MemWrite 82375599 23.60% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 104312543 31.82% 31.82% # Class of executed instruction +system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction +system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction +system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 349065592 # Class of executed instruction +system.cpu.op_class::total 327812213 # Class of executed instruction system.cpu.icache.tags.replacements 13796 # number of replacements -system.cpu.icache.tags.tagsinuse 1765.993223 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 348644747 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1766.007645 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 348644749 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22344.725181 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 22344.725309 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1765.993223 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.862301 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.862301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007645 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id @@ -204,44 +206,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 26 system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 697336303 # Number of tag accesses -system.cpu.icache.tags.data_accesses 697336303 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 348644747 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 348644747 # number of overall hits -system.cpu.icache.overall_hits::total 348644747 # number of overall hits +system.cpu.icache.tags.tag_accesses 697336307 # Number of tag accesses +system.cpu.icache.tags.data_accesses 697336307 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 348644749 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 348644749 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 348644749 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 348644749 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 348644749 # number of overall hits +system.cpu.icache.overall_hits::total 348644749 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses system.cpu.icache.overall_misses::total 15603 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 312417000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 312417000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 312417000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 312417000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 312417000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 312417000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 348660350 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 348660350 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 348660350 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 348660350 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 348660350 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 348660350 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 312527500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 312527500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 312527500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 312527500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 312527500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 312527500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 348660352 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 348660352 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 348660352 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 348660352 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 348660352 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 348660352 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20022.880215 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20022.880215 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20022.880215 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20022.880215 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.962187 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20029.962187 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20029.962187 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20029.962187 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -256,38 +258,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603 system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281211000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281211000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281211000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281211000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281211000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281211000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281321500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 281321500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281321500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 281321500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281321500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 281321500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18022.880215 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18022.880215 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18029.962187 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18029.962187 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3487.723791 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3487.764987 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 341.616093 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.399470 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 737.708228 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 341.623056 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.427143 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 737.714788 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.010426 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.106437 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.106438 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id @@ -321,17 +323,17 @@ system.cpu.l2cache.demand_misses::total 6832 # nu system.cpu.l2cache.overall_misses::cpu.inst 2609 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4223 # number of overall misses system.cpu.l2cache.overall_misses::total 6832 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135668000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71084000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 206752000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148512000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 148512000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 135668000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 219596000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 355264000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 135668000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 219596000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 355264000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135778500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71271000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 207049500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148649500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 148649500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 135778500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 219920500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 355699000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 135778500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 219920500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 355699000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses) @@ -356,17 +358,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.340222 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167211 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52042.353392 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52136.795903 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52074.823944 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52048.144258 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52048.144258 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52063.670960 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52063.670960 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -386,17 +388,17 @@ system.cpu.l2cache.demand_mshr_misses::total 6832 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104360000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104365000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159040000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104360000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168920000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 273280000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104360000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168920000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 273280000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159045000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114243000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114243000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104365000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168923000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 273288000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104365000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168923000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 273288000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231042 # mshr miss rate for ReadReq accesses @@ -408,92 +410,100 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.916443 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.257545 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.050420 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.050420 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 1332 # number of replacements -system.cpu.dcache.tags.tagsinuse 3078.412981 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 176641599 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3078.445016 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 39446.538410 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.751566 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445016 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 353296632 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 353296632 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 176619809 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 176619809 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 176619809 # number of overall hits -system.cpu.dcache.overall_hits::total 176619809 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1606 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1606 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits +system.cpu.dcache.overall_hits::total 168337827 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 4478 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4478 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4478 # number of overall misses -system.cpu.dcache.overall_misses::total 4478 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 78292000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 78292000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 157288000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 157288000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 235580000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 235580000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 235580000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 235580000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 94571610 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94571610 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses +system.cpu.dcache.overall_misses::total 4479 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 78354000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 78354000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 157425500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 157425500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 235779500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 235779500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 235779500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 235779500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 176624287 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 176624287 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 176624287 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 176624287 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48749.688667 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 48749.688667 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54766.016713 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54766.016713 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52608.307280 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52608.307280 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52676.385165 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52641.102925 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -504,40 +514,54 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 998 # number of writebacks system.cpu.dcache.writebacks::total 998 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1606 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1606 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4478 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4478 # number of demand (read+write) MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75080000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75080000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151544000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 151544000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226624000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 226624000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226624000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 226624000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000017 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75108000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75108000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151681500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 151681500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 159000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 159000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226789500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 226789500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226948500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 226948500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46749.688667 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52766.016713 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 2565553 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 2608205 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution |