diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:53 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:53 -0400 |
| commit | c4e91289ae8806eb051fb1f41ece8be308f0ff85 (patch) | |
| tree | 6f35a7725cfd4072c8516ee0bb2ae799d48ce896 /tests/long/se/30.eon/ref | |
| parent | cc6523e2d686447f90acccac20c0fb2940dc3e3b (diff) | |
| download | gem5-c4e91289ae8806eb051fb1f41ece8be308f0ff85.tar.xz | |
stats: Bump stats for filter, crossbar and config changes
This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
Diffstat (limited to 'tests/long/se/30.eon/ref')
8 files changed, 1474 insertions, 1280 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index 2ad80aa5a..e79be71e4 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.220941 # Nu sim_ticks 220941341500 # Number of ticks simulated final_tick 220941341500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 303038 # Simulator instruction rate (inst/s) -host_op_rate 303038 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 167944827 # Simulator tick rate (ticks/s) -host_mem_usage 273400 # Number of bytes of host memory used -host_seconds 1315.56 # Real time elapsed on the host +host_inst_rate 328458 # Simulator instruction rate (inst/s) +host_op_rate 328458 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 182032431 # Simulator tick rate (ticks/s) +host_mem_usage 297876 # Number of bytes of host memory used +host_seconds 1213.75 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -86,8 +86,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6820 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 972 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6821 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 971 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895 37 2.44% 85.64% # By system.physmem.bytesPerActivate::896-1023 28 1.84% 87.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 190 12.52% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1518 # Bytes accessed per row activation -system.physmem.totQLat 52730250 # Total ticks spent queuing -system.physmem.totMemAccLat 200386500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 53358500 # Total ticks spent queuing +system.physmem.totMemAccLat 201014750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 39375000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6695.90 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6775.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25445.90 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25525.68 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.28 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.28 # Average system read bandwidth in MiByte/s @@ -223,20 +223,28 @@ system.physmem.memoryStateTime::REF 7377500000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 1721627750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 2281148 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 4737 # Transaction distribution system.membus.trans_dist::ReadResp 4737 # Transaction distribution system.membus.trans_dist::ReadExReq 3138 # Transaction distribution system.membus.trans_dist::ReadExResp 3138 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15750 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 15750 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 504000 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 504000 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 504000 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 9511500 # Layer occupancy (ticks) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 504000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 504000 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7875 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 7875 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 7875 # Request fanout histogram +system.membus.reqLayer0.occupancy 9512000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 74010500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 74011500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 46221231 # Number of BP lookups @@ -290,15 +298,15 @@ system.cpu.discardedOps 4446127 # Nu system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.108407 # CPI: cycles per instruction system.cpu.ipc 0.902196 # IPC: instructions per cycle -system.cpu.tickCycles 437732113 # Number of cycles that the object actually ticked -system.cpu.idleCycles 4150570 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 437732110 # Number of cycles that the object actually ticked +system.cpu.idleCycles 4150573 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 3195 # number of replacements -system.cpu.icache.tags.tagsinuse 1919.708567 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1919.708570 # Cycle average of tags in use system.cpu.icache.tags.total_refs 98237130 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 5173 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18990.359559 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1919.708567 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1919.708570 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.937358 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.937358 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id @@ -321,12 +329,12 @@ system.cpu.icache.demand_misses::cpu.inst 5173 # n system.cpu.icache.demand_misses::total 5173 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5173 # number of overall misses system.cpu.icache.overall_misses::total 5173 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 293554750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 293554750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 293554750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 293554750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 293554750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 293554750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 293560000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 293560000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 293560000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 293560000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 293560000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 293560000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 98242303 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 98242303 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 98242303 # number of demand (read+write) accesses @@ -339,12 +347,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000053 system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000053 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56747.486951 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56747.486951 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56747.486951 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56747.486951 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56747.486951 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56747.486951 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56748.501836 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56748.501836 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56748.501836 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56748.501836 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56748.501836 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56748.501836 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -359,26 +367,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 5173 system.cpu.icache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 5173 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 5173 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281585250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281585250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281585250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281585250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281585250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281585250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281592000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 281592000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281592000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 281592000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281592000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 281592000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54433.645853 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54433.645853 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54433.645853 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54433.645853 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54433.645853 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54433.645853 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54434.950706 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54434.950706 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54434.950706 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54434.950706 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54434.950706 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54434.950706 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 2894379 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 6139 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 6139 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution @@ -387,25 +394,35 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 3199 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10346 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8984 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 19330 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 331072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 639488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 639488 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 331072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 639488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 9992 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 9992 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 9992 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 5650000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8571250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 8570500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6974750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6975500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4427.627395 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4427.627399 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1491 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5274 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.282708 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 373.083919 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4054.543476 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4054.543479 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011386 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123735 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.135120 # Average percentage of cache occupancy @@ -435,14 +452,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 7875 # system.cpu.l2cache.demand_misses::total 7875 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 7875 # number of overall misses system.cpu.l2cache.overall_misses::total 7875 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 325767500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 325767500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 212904500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 212904500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 538672000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 538672000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 538672000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 538672000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 325756750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 325756750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 212895750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 212895750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 538652500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 538652500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 538652500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 538652500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 6139 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 6139 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 654 # number of Writeback accesses(hits+misses) @@ -461,14 +478,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.843328 system.cpu.l2cache.demand_miss_rate::total 0.843328 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.843328 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.843328 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68770.846527 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68770.846527 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67847.195666 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67847.195666 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68402.793651 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68402.793651 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68402.793651 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68402.793651 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68768.577159 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68768.577159 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67844.407266 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67844.407266 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68400.317460 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68400.317460 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68400.317460 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68400.317460 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -485,14 +502,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 7875 system.cpu.l2cache.demand_mshr_misses::total 7875 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 7875 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7875 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266387000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266387000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 173110500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 173110500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 439497500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 439497500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 439497500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 439497500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266376250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266376250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 173100750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 173100750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 439477000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 439477000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 439477000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 439477000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.771624 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771624 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.980932 # mshr miss rate for ReadExReq accesses @@ -501,22 +518,22 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.843328 system.cpu.l2cache.demand_mshr_miss_rate::total 0.843328 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.843328 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.843328 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56235.381043 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56235.381043 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55165.869981 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55165.869981 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55809.206349 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55809.206349 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55809.206349 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55809.206349 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56233.111674 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56233.111674 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55162.762906 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55162.762906 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55806.603175 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55806.603175 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55806.603175 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55806.603175 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.748201 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3291.748199 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168007181 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 40337.858583 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.748201 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.748199 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.803649 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.803649 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id @@ -544,14 +561,14 @@ system.cpu.dcache.demand_misses::cpu.inst 7119 # n system.cpu.dcache.demand_misses::total 7119 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 7119 # number of overall misses system.cpu.dcache.overall_misses::total 7119 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 81035500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 81035500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 393767750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 393767750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 474803250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 474803250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 474803250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 474803250 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 81019000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 81019000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 393760000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 393760000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 474779000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 474779000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 474779000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 474779000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 94493570 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94493570 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 73520730 # number of WriteReq accesses(hits+misses) @@ -568,14 +585,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.000042 system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68907.738095 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68907.738095 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66257.403668 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66257.403668 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66695.217025 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66695.217025 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66695.217025 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66695.217025 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68893.707483 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68893.707483 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66256.099613 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66256.099613 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66691.810648 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66691.810648 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66691.810648 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66691.810648 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -602,14 +619,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 4165 system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 64480250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 64480250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 216613000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 216613000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 281093250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 281093250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 281093250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 281093250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 64462750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 64462750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 216604250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 216604250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 281067000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 281067000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 281067000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 281067000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for WriteReq accesses @@ -618,14 +635,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66611.828512 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66611.828512 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67755.082890 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67755.082890 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67489.375750 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67489.375750 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67489.375750 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67489.375750 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66593.750000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66593.750000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67752.345949 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67752.345949 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67483.073229 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67483.073229 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67483.073229 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67483.073229 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 0f0c79704..7fec5fb4b 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.069652 # Nu sim_ticks 69651704000 # Number of ticks simulated final_tick 69651704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 185769 # Simulator instruction rate (inst/s) -host_op_rate 185769 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34451530 # Simulator tick rate (ticks/s) -host_mem_usage 243176 # Number of bytes of host memory used -host_seconds 2021.73 # Real time elapsed on the host +host_inst_rate 258321 # Simulator instruction rate (inst/s) +host_op_rate 258321 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47906543 # Simulator tick rate (ticks/s) +host_mem_usage 298148 # Number of bytes of host memory used +host_seconds 1453.91 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4229 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4226 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1956 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 918 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 291 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 63 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1354 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 350.251108 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 208.626324 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 348.782669 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 425 31.39% 31.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 330 24.37% 55.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 151 11.15% 66.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 84 6.20% 73.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 54 3.99% 77.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 42 3.10% 80.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 39 2.88% 83.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 25 1.85% 84.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 204 15.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1354 # Bytes accessed per row activation -system.physmem.totQLat 65436750 # Total ticks spent queuing -system.physmem.totMemAccLat 205274250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1353 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 350.509978 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 208.823320 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 348.868335 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 424 31.34% 31.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 330 24.39% 55.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 151 11.16% 66.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 84 6.21% 73.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 54 3.99% 77.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 42 3.10% 80.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 39 2.88% 83.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 25 1.85% 84.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 204 15.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1353 # Bytes accessed per row activation +system.physmem.totQLat 66704750 # Total ticks spent queuing +system.physmem.totMemAccLat 206542250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37290000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8774.03 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8944.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27524.03 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27694.05 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.85 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.85 # Average system read bandwidth in MiByte/s @@ -216,31 +216,39 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6095 # Number of row buffer hits during reads +system.physmem.readRowHits 6096 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.72 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.74 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 9339181.35 # Average gap between requests -system.physmem.pageHitRate 81.72 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 66207100500 # Time in different power states +system.physmem.pageHitRate 81.74 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 66207575500 # Time in different power states system.physmem.memoryStateTime::REF 2325700000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1115479500 # Time in different power states +system.physmem.memoryStateTime::ACT 1115004500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 6852840 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 4328 # Transaction distribution system.membus.trans_dist::ReadResp 4328 # Transaction distribution system.membus.trans_dist::ReadExReq 3130 # Transaction distribution system.membus.trans_dist::ReadExResp 3130 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14916 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 14916 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477312 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 477312 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 477312 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 9424500 # Layer occupancy (ticks) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 477312 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7458 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 7458 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 7458 # Request fanout histogram +system.membus.reqLayer0.occupancy 9424000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 69714000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 69710500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 51167476 # Number of BP lookups @@ -288,11 +296,11 @@ system.cpu.workload.num_syscalls 215 # Nu system.cpu.numCycles 139303411 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 52063836 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 52063861 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 457094552 # Number of instructions fetch has processed system.cpu.fetch.Branches 51167476 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 32952094 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 85692293 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 85692225 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 2532764 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb system.cpu.fetch.MiscStallCycles 174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs @@ -300,11 +308,11 @@ system.cpu.fetch.PendingTrapStallCycles 13783 # Nu system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 51277823 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 545280 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 139036498 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.287587 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 139036455 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.287588 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.344928 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 58307253 41.94% 41.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58307210 41.94% 41.94% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 4519217 3.25% 45.19% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 7280822 5.24% 50.42% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 5545601 3.99% 54.41% # Number of instructions fetched each cycle (Total) @@ -316,11 +324,11 @@ system.cpu.fetch.rateDist::8 35575531 25.59% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 139036498 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 139036455 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.367310 # Number of branch fetches per cycle system.cpu.fetch.rate 3.281288 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45112294 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16348159 # Number of cycles decode is blocked +system.cpu.decode.IdleCycles 45112319 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16348091 # Number of cycles decode is blocked system.cpu.decode.RunCycles 71786999 # Number of cycles decode is running system.cpu.decode.UnblockCycles 4526862 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1262184 # Number of cycles decode is squashing @@ -329,16 +337,16 @@ system.cpu.decode.BranchMispred 4245 # Nu system.cpu.decode.DecodedInsts 451283163 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 14200 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 1262184 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 47010937 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5663540 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 519055 # count of cycles rename stalled for serializing inst +system.cpu.rename.IdleCycles 47010962 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5663544 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 518995 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 74309214 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10271568 # Number of cycles rename is unblocking +system.cpu.rename.UnblockCycles 10271556 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 447721649 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 439815 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 2540100 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 2926498 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 3600584 # Number of times rename has blocked due to SQ full +system.cpu.rename.SQFullEvents 3600572 # Number of times rename has blocked due to SQ full system.cpu.rename.RenamedOperands 292278306 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 589607782 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 419965282 # Number of integer rename lookups @@ -359,23 +367,23 @@ system.cpu.iq.iqSquashedInstsIssued 484036 # Nu system.cpu.iq.iqSquashedInstsExamined 38878487 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 18208108 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 91 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 139036498 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.926684 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.221929 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 139036455 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.926685 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.221928 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23891417 17.18% 17.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19616673 14.11% 31.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22677490 16.31% 47.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23891375 17.18% 17.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19616672 14.11% 31.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22677489 16.31% 47.60% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 18900240 13.59% 61.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 19609415 14.10% 75.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14153869 10.18% 85.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9626408 6.92% 92.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 19609416 14.10% 75.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14153870 10.18% 85.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9626407 6.92% 92.40% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 6209798 4.47% 96.87% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 4351188 3.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 139036498 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 139036455 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 258477 1.29% 1.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 1 0.00% 1.29% # attempts to use FU when none available @@ -448,7 +456,7 @@ system.cpu.iq.FU_type_0::total 406915916 # Ty system.cpu.iq.rate 2.921076 # Inst issue rate system.cpu.iq.fu_busy_cnt 19986240 # FU busy when requested system.cpu.iq.fu_busy_rate 0.049116 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 625896967 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 625896924 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 265989715 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 237228630 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 347441639 # Number of floating instruction queue reads @@ -468,7 +476,7 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 381699 # system.cpu.iew.lsq.thread0.cacheBlocked 4486 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 1262184 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4471522 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 4471526 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 139226 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 439574480 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 145285 # Number of squashed instructions skipped by dispatch @@ -492,8 +500,8 @@ system.cpu.iew.exec_stores 79416096 # Nu system.cpu.iew.exec_rate 2.894098 # Inst execution rate system.cpu.iew.wb_sent 401401506 # cumulative count of insts sent to commit system.cpu.iew.wb_count 400567895 # cumulative count of insts written-back -system.cpu.iew.wb_producers 198000447 # num instructions producing a value -system.cpu.iew.wb_consumers 283955601 # num instructions consuming a value +system.cpu.iew.wb_producers 198000445 # num instructions producing a value +system.cpu.iew.wb_consumers 283955599 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.875507 # insts written-back per cycle system.cpu.iew.wb_fanout 0.697294 # average fanout of values written-back @@ -501,23 +509,23 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 40912072 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1208897 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 133310645 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.990493 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 133310602 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.990494 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 3.213946 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 48555640 36.42% 36.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18055919 13.54% 49.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 9630862 7.22% 57.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 48555591 36.42% 36.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18055922 13.54% 49.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 9630864 7.22% 57.19% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 8737321 6.55% 63.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6426213 4.82% 68.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6426217 4.82% 68.57% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 4404757 3.30% 71.87% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 4988495 3.74% 75.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2616134 1.96% 77.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29895304 22.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2616133 1.96% 77.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29895302 22.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 133310645 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 133310602 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -563,12 +571,12 @@ system.cpu.commit.op_class_0::MemWrite 73520729 18.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 398664583 # Class of committed instruction -system.cpu.commit.bw_lim_events 29895304 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29895302 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 542989019 # The number of ROB reads +system.cpu.rob.rob_reads 542988978 # The number of ROB reads system.cpu.rob.rob_writes 884890973 # The number of ROB writes -system.cpu.timesIdled 3471 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 266913 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.timesIdled 3472 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 266956 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.cpi 0.370907 # CPI: Cycles Per Instruction @@ -581,7 +589,6 @@ system.cpu.fp_regfile_reads 157938395 # nu system.cpu.fp_regfile_writes 105579710 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 8238478 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 5089 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 5089 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 674 # Transaction distribution @@ -590,24 +597,34 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 3203 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8182 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9076 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 17258 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 573824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 573824 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 573824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 8966 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 8966 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 8966 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 5157000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6787250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6787000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6699750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6700000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.icache.tags.replacements 2164 # number of replacements -system.cpu.icache.tags.tagsinuse 1832.364341 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1832.364308 # Cycle average of tags in use system.cpu.icache.tags.total_refs 51272145 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4091 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 12532.912491 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1832.364341 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1832.364308 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.894709 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.894709 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1927 # Occupied blocks per task id @@ -630,12 +647,12 @@ system.cpu.icache.demand_misses::cpu.inst 5678 # n system.cpu.icache.demand_misses::total 5678 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5678 # number of overall misses system.cpu.icache.overall_misses::total 5678 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 339990499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 339990499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 339990499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 339990499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 339990499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 339990499 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 340036249 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 340036249 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 340036249 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 340036249 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 340036249 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 340036249 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 51277823 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 51277823 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 51277823 # number of demand (read+write) accesses @@ -648,12 +665,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000111 system.cpu.icache.demand_miss_rate::total 0.000111 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000111 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000111 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59878.566221 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 59878.566221 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 59878.566221 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 59878.566221 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 59878.566221 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 59878.566221 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59886.623635 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 59886.623635 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 59886.623635 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 59886.623635 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 59886.623635 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 59886.623635 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 528 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked @@ -674,34 +691,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4091 system.cpu.icache.demand_mshr_misses::total 4091 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4091 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4091 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249912250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 249912250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249912250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 249912250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249912250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 249912250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249962500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 249962500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249962500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 249962500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249962500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 249962500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61088.303593 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61088.303593 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61088.303593 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61088.303593 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61088.303593 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61088.303593 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61100.586654 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61100.586654 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61100.586654 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61100.586654 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61100.586654 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61100.586654 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4021.632114 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4021.632026 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 866 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4864 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.178043 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 371.133815 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2983.663024 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 666.835276 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 371.133812 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2983.662944 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 666.835269 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011326 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.091054 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.020350 # Average percentage of cache occupancy @@ -738,17 +755,17 @@ system.cpu.l2cache.demand_misses::total 7458 # nu system.cpu.l2cache.overall_misses::cpu.inst 3462 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3996 # number of overall misses system.cpu.l2cache.overall_misses::total 7458 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 239520750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 65288250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 304809000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 231991500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 231991500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 239520750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 297279750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 536800500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 239520750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 297279750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 536800500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 239571000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 65252750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 304823750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 231908750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 231908750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 239571000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 297161500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 536732500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 239571000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 297161500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 536732500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 4091 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 998 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 5089 # number of ReadReq accesses(hits+misses) @@ -773,17 +790,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.899421 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.846248 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.951202 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.899421 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69185.658579 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75390.588915 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70427.218115 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74118.690096 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74118.690096 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69185.658579 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74394.331832 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71976.468222 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69185.658579 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74394.331832 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71976.468222 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69200.173310 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75349.595843 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70430.626155 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74092.252396 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74092.252396 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69200.173310 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74364.739740 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71967.350496 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69200.173310 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74364.739740 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71967.350496 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -803,17 +820,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7458 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3462 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3996 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7458 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 195634750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54618250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 250253000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 193410500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 193410500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195634750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 248028750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 443663500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195634750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 248028750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 443663500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 195687500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54580750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 250268250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 193330750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 193330750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195687500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 247911500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 443599000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195687500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 247911500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 443599000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867735 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.850462 # mshr miss rate for ReadReq accesses @@ -825,25 +842,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899421 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.951202 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899421 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56509.170999 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63069.572748 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57821.857671 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61792.492013 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61792.492013 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56509.170999 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62069.256757 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59488.267632 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56509.170999 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62069.256757 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59488.267632 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56524.407857 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63026.270208 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57825.381238 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61767.012780 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61767.012780 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56524.407857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62039.914915 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59479.619201 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56524.407857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62039.914915 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59479.619201 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 798 # number of replacements -system.cpu.dcache.tags.tagsinuse 3297.113069 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3297.113011 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 156873476 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4201 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37341.936682 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3297.113069 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 3297.113011 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.804959 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.804959 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3403 # Occupied blocks per task id @@ -873,14 +890,14 @@ system.cpu.dcache.demand_misses::cpu.data 21715 # n system.cpu.dcache.demand_misses::total 21715 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 21715 # number of overall misses system.cpu.dcache.overall_misses::total 21715 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 114614250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 114614250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1125204835 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1125204835 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1239819085 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1239819085 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1239819085 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1239819085 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 114579750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 114579750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1125182835 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1125182835 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1239762585 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1239762585 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1239762585 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1239762585 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 83374455 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 83374455 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -899,19 +916,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000138 system.cpu.dcache.demand_miss_rate::total 0.000138 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000138 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000138 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62905.735456 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62905.735456 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56562.853014 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56562.853014 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 57095.053419 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 57095.053419 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 57095.053419 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 57095.053419 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 46429 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62886.800220 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62886.800220 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56561.747097 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56561.747097 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 57092.451531 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 57092.451531 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 57092.451531 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 57092.451531 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 46428 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 61 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 948 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 947 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.975738 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.026399 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 61 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -933,14 +950,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4201 system.cpu.dcache.demand_mshr_misses::total 4201 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4201 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4201 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67699250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 67699250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 236024500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 236024500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 303723750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 303723750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 303723750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 303723750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67663750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 67663750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 235941750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 235941750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 303605500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 303605500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 303605500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 303605500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -949,14 +966,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67834.919840 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67834.919840 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73688.573213 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73688.573213 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72297.964770 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72297.964770 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72297.964770 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72297.964770 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67799.348697 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67799.348697 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73662.738058 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73662.738058 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72269.816710 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72269.816710 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72269.816710 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72269.816710 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt index bde0ba631..7803b8dd6 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.199332 # Nu sim_ticks 199332411500 # Number of ticks simulated final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3159999 # Simulator instruction rate (inst/s) -host_op_rate 3159998 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1579999901 # Simulator tick rate (ticks/s) -host_mem_usage 261616 # Number of bytes of host memory used -host_seconds 126.16 # Real time elapsed on the host +host_inst_rate 2820224 # Simulator instruction rate (inst/s) +host_op_rate 2820224 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1410112599 # Simulator tick rate (ticks/s) +host_mem_usage 285836 # Number of bytes of host memory used +host_seconds 141.36 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,27 @@ system.physmem.bw_write::total 2470028804 # Wr system.physmem.bw_total::cpu.inst 7999996548 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5793368275 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13793364824 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 13793364824 # Throughput (bytes/s) -system.membus.data_through_bus 2749464673 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 493419140 # Transaction distribution +system.membus.trans_dist::ReadResp 493419140 # Transaction distribution +system.membus.trans_dist::WriteReq 73520729 # Transaction distribution +system.membus.trans_dist::WriteResp 73520729 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 797329302 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336550436 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1133879738 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1594658604 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1154806069 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 2749464673 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 566939869 # Request fanout histogram +system.membus.snoop_fanout::mean 0.703187 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.456853 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 168275218 29.68% 29.68% # Request fanout histogram +system.membus.snoop_fanout::1 398664651 70.32% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 566939869 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index f8ab96a0a..01baacd99 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.567335 # Nu sim_ticks 567335093000 # Number of ticks simulated final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1556013 # Simulator instruction rate (inst/s) -host_op_rate 1556013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2214344764 # Simulator tick rate (ticks/s) -host_mem_usage 270340 # Number of bytes of host memory used -host_seconds 256.21 # Real time elapsed on the host +host_inst_rate 1606485 # Simulator instruction rate (inst/s) +host_op_rate 1606484 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2286169690 # Simulator tick rate (ticks/s) +host_mem_usage 295576 # Number of bytes of host memory used +host_seconds 248.16 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 361550 # In system.physmem.bw_total::cpu.inst 361550 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 447735 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 809285 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 809285 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 4032 # Transaction distribution system.membus.trans_dist::ReadResp 4032 # Transaction distribution system.membus.trans_dist::ReadExReq 3142 # Transaction distribution system.membus.trans_dist::ReadExResp 3142 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14348 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 14348 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 459136 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 459136 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 459136 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7174 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 7174 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 7174 # Request fanout histogram system.membus.reqLayer0.occupancy 7174000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 64566000 # Layer occupancy (ticks) @@ -477,7 +485,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 51148.843931 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 955936 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 4623 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution @@ -486,11 +493,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 3202 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7346 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8953 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 16299 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 235072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 542336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 542336 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 235072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 542336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 8474 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 8474 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 8474 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4886000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 5509500 # Layer occupancy (ticks) diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 73979cce4..b4d2bc6bd 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.212377 # Nu sim_ticks 212377413000 # Number of ticks simulated final_tick 212377413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 166098 # Simulator instruction rate (inst/s) -host_op_rate 199419 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 129195965 # Simulator tick rate (ticks/s) -host_mem_usage 326468 # Number of bytes of host memory used -host_seconds 1643.84 # Real time elapsed on the host +host_inst_rate 164145 # Simulator instruction rate (inst/s) +host_op_rate 197075 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 127677508 # Simulator tick rate (ticks/s) +host_mem_usage 316656 # Number of bytes of host memory used +host_seconds 1663.39 # Real time elapsed on the host sim_insts 273037856 # Number of instructions simulated sim_ops 327812213 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895 43 2.87% 86.11% # By system.physmem.bytesPerActivate::896-1023 33 2.20% 88.32% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 175 11.68% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1498 # Bytes accessed per row activation -system.physmem.totQLat 52122500 # Total ticks spent queuing -system.physmem.totMemAccLat 194303750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 52768250 # Total ticks spent queuing +system.physmem.totMemAccLat 194949500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37915000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6873.60 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6958.76 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25623.60 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25708.76 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s @@ -223,29 +223,37 @@ system.physmem.memoryStateTime::REF 7091500000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 2441586750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 2285139 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 4730 # Transaction distribution system.membus.trans_dist::ReadResp 4730 # Transaction distribution system.membus.trans_dist::ReadExReq 2853 # Transaction distribution system.membus.trans_dist::ReadExResp 2853 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15166 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 15166 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 485312 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8812000 # Layer occupancy (ticks) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7583 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 7583 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 7583 # Request fanout histogram +system.membus.reqLayer0.occupancy 8812500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 70869000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 70869750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 33146135 # Number of BP lookups +system.cpu.branchPred.lookups 33146132 # Number of BP lookups system.cpu.branchPred.condPredicted 17115100 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1582628 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18038083 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 18038080 # Number of BTB lookups system.cpu.branchPred.BTBHits 15622031 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 86.605827 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 86.605842 # BTB Hit Percentage system.cpu.branchPred.usedRAS 6627212 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -338,19 +346,19 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 273037856 # Number of instructions committed system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4318160 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 4318159 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.555663 # CPI: cycles per instruction system.cpu.ipc 0.642813 # IPC: instructions per cycle -system.cpu.tickCycles 420995897 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3758929 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 420995875 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3758951 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 36952 # number of replacements -system.cpu.icache.tags.tagsinuse 1924.941242 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 73208047 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1924.941243 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 73208046 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 38889 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1882.487259 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1882.487233 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1924.941242 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.941243 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.939913 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.939913 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id @@ -360,44 +368,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 33 system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1488 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146532763 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146532763 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 73208047 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 73208047 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 73208047 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 73208047 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 73208047 # number of overall hits -system.cpu.icache.overall_hits::total 73208047 # number of overall hits +system.cpu.icache.tags.tag_accesses 146532761 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146532761 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 73208046 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 73208046 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 73208046 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 73208046 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 73208046 # number of overall hits +system.cpu.icache.overall_hits::total 73208046 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 38890 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 38890 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 38890 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 38890 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 38890 # number of overall misses system.cpu.icache.overall_misses::total 38890 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 704978746 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 704978746 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 704978746 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 704978746 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 704978746 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 704978746 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 73246937 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 73246937 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 73246937 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 73246937 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 73246937 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 73246937 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 705005996 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 705005996 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 705005996 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 705005996 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 705005996 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 705005996 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 73246936 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 73246936 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 73246936 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 73246936 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 73246936 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 73246936 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000531 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000531 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000531 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000531 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000531 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000531 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18127.506968 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18127.506968 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18127.506968 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18127.506968 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18127.506968 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18127.506968 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18128.207663 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18128.207663 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18128.207663 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18128.207663 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18128.207663 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18128.207663 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,26 +420,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 38890 system.cpu.icache.demand_mshr_misses::total 38890 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 38890 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 38890 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 625804254 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 625804254 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 625804254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 625804254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 625804254 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 625804254 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 625833004 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 625833004 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 625833004 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 625833004 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 625833004 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 625833004 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000531 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000531 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000531 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16091.649627 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16091.649627 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16091.649627 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16091.649627 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16091.649627 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16091.649627 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16092.388892 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16092.388892 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16092.388892 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16092.388892 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16092.388892 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16092.388892 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 13382365 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 40531 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 40530 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1009 # Transaction distribution @@ -440,25 +447,39 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 2869 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77779 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10029 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 87808 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2488896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 2842112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 2842112 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2488896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2842112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 44409 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 44409 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 44409 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 23213500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 59031746 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 59030996 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7495460 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7495960 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4198.136947 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4198.136942 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 35837 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5644 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 6.349575 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 353.492029 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.644919 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 353.492030 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.644913 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010788 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117329 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.128117 # Average percentage of cache occupancy @@ -489,14 +510,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 7626 # system.cpu.l2cache.demand_misses::total 7626 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 7626 # number of overall misses system.cpu.l2cache.overall_misses::total 7626 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 328392750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 328392750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194194500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 194194500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 522587250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 522587250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 522587250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 522587250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 328394750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 328394750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194183750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 194183750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 522578500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 522578500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 522578500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 522578500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 40531 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 40531 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 1009 # number of Writeback accesses(hits+misses) @@ -515,14 +536,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.175714 system.cpu.l2cache.demand_miss_rate::total 0.175714 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.175714 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.175714 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68802.168448 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68802.168448 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68066.771819 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68066.771819 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68527.045633 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68527.045633 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68527.045633 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68527.045633 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68802.587471 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68802.587471 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68063.003856 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68063.003856 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68525.898243 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68525.898243 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68525.898243 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68525.898243 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -545,14 +566,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 7583 system.cpu.l2cache.demand_mshr_misses::total 7583 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 7583 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7583 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266719500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266719500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158382000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158382000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425101500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 425101500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425101500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 425101500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266721500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266721500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158370750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158370750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425092250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 425092250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425092250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 425092250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.116701 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116701 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994423 # mshr miss rate for ReadExReq accesses @@ -561,22 +582,22 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174724 system.cpu.l2cache.demand_mshr_miss_rate::total 0.174724 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174724 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.174724 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56388.900634 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56388.900634 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55514.195584 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55514.195584 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56059.804827 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56059.804827 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56059.804827 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56059.804827 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56389.323467 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56389.323467 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55510.252366 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55510.252366 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56058.584993 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56058.584993 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56058.584993 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56058.584993 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 1353 # number of replacements -system.cpu.dcache.tags.tagsinuse 3085.890933 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3085.890938 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168774540 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4510 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37422.292683 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 3085.890933 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 3085.890938 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.753391 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.753391 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id @@ -608,14 +629,14 @@ system.cpu.dcache.demand_misses::cpu.inst 7291 # n system.cpu.dcache.demand_misses::total 7291 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 7291 # number of overall misses system.cpu.dcache.overall_misses::total 7291 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 127204208 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 127204208 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 358851000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 358851000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 486055208 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 486055208 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 486055208 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 486055208 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 127168958 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 127168958 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 358839500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 358839500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 486008458 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 486008458 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 486008458 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 486008458 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 86707364 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 86707364 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses) @@ -636,14 +657,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61600.100726 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61600.100726 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68666.475316 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 68666.475316 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66665.095049 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66665.095049 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66665.095049 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66665.095049 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61583.030508 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61583.030508 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68664.274780 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 68664.274780 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66658.683034 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66658.683034 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66658.683034 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66658.683034 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -670,14 +691,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 4510 system.cpu.dcache.demand_mshr_misses::total 4510 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 4510 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4510 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100713040 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 100713040 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197262500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 197262500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297975540 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 297975540 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297975540 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 297975540 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100686290 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 100686290 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197251750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 197251750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297938040 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 297938040 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297938040 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 297938040 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses @@ -686,14 +707,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61372.967703 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61372.967703 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68756.535378 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68756.535378 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66069.964523 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66069.964523 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66069.964523 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66069.964523 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61356.666667 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61356.666667 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68752.788428 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68752.788428 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66061.649667 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66061.649667 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66061.649667 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66061.649667 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 6d48708ce..f8fbd30b2 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,62 +1,66 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058843 # Number of seconds simulated -sim_ticks 58842982000 # Number of ticks simulated -final_tick 58842982000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.112541 # Number of seconds simulated +sim_ticks 112540655000 # Number of ticks simulated +final_tick 112540655000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 157851 # Simulator instruction rate (inst/s) -host_op_rate 189517 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34018873 # Simulator tick rate (ticks/s) -host_mem_usage 327492 # Number of bytes of host memory used -host_seconds 1729.72 # Real time elapsed on the host -sim_insts 273036656 # Number of instructions simulated -sim_ops 327810999 # Number of ops (including micro ops) simulated +host_inst_rate 123771 # Simulator instruction rate (inst/s) +host_op_rate 148600 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51015836 # Simulator tick rate (ticks/s) +host_mem_usage 322668 # Number of bytes of host memory used +host_seconds 2205.99 # Real time elapsed on the host +sim_insts 273037219 # Number of instructions simulated +sim_ops 327811601 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 189376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272128 # Number of bytes read from this memory -system.physmem.bytes_read::total 461504 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 189376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 189376 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2959 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4252 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7211 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3218328 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4624647 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7842974 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3218328 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3218328 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3218328 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4624647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7842974 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7211 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 30592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 80768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 512320 # Number of bytes read from this memory +system.physmem.bytes_read::total 623680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 30592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 30592 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 478 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1262 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 8005 # Number of read requests responded to by this memory +system.physmem.num_reads::total 9745 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 271831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 717678 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 4552310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 5541820 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 271831 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 271831 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 271831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 717678 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 4552310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5541820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 9745 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7211 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 9745 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 461504 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 623680 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 461504 # Total read bytes from the system interface side +system.physmem.bytesReadSys 623680 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 11 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 592 # Per bank write bursts -system.physmem.perBankRdBursts::1 792 # Per bank write bursts -system.physmem.perBankRdBursts::2 603 # Per bank write bursts -system.physmem.perBankRdBursts::3 519 # Per bank write bursts -system.physmem.perBankRdBursts::4 437 # Per bank write bursts -system.physmem.perBankRdBursts::5 342 # Per bank write bursts -system.physmem.perBankRdBursts::6 159 # Per bank write bursts -system.physmem.perBankRdBursts::7 228 # Per bank write bursts -system.physmem.perBankRdBursts::8 208 # Per bank write bursts -system.physmem.perBankRdBursts::9 292 # Per bank write bursts -system.physmem.perBankRdBursts::10 317 # Per bank write bursts -system.physmem.perBankRdBursts::11 409 # Per bank write bursts -system.physmem.perBankRdBursts::12 526 # Per bank write bursts -system.physmem.perBankRdBursts::13 671 # Per bank write bursts -system.physmem.perBankRdBursts::14 612 # Per bank write bursts -system.physmem.perBankRdBursts::15 504 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 803 # Per bank write bursts +system.physmem.perBankRdBursts::1 999 # Per bank write bursts +system.physmem.perBankRdBursts::2 769 # Per bank write bursts +system.physmem.perBankRdBursts::3 645 # Per bank write bursts +system.physmem.perBankRdBursts::4 618 # Per bank write bursts +system.physmem.perBankRdBursts::5 484 # Per bank write bursts +system.physmem.perBankRdBursts::6 251 # Per bank write bursts +system.physmem.perBankRdBursts::7 363 # Per bank write bursts +system.physmem.perBankRdBursts::8 300 # Per bank write bursts +system.physmem.perBankRdBursts::9 432 # Per bank write bursts +system.physmem.perBankRdBursts::10 486 # Per bank write bursts +system.physmem.perBankRdBursts::11 534 # Per bank write bursts +system.physmem.perBankRdBursts::12 696 # Per bank write bursts +system.physmem.perBankRdBursts::13 850 # Per bank write bursts +system.physmem.perBankRdBursts::14 782 # Per bank write bursts +system.physmem.perBankRdBursts::15 733 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58842848000 # Total gap between requests +system.physmem.totGap 112540488500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7211 # Read request sizes (log2) +system.physmem.readPktSize::6 9745 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,22 +94,22 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4240 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2012 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 646 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 244 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2266 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1763 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 847 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 758 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 667 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 603 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 95 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 46 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 25 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -186,74 +190,82 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1405 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 327.288256 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 191.332764 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.731237 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 492 35.02% 35.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 350 24.91% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 132 9.40% 69.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 82 5.84% 75.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 53 3.77% 78.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 47 3.35% 82.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 27 1.92% 84.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 22 1.57% 85.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 200 14.23% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1405 # Bytes accessed per row activation -system.physmem.totQLat 59614750 # Total ticks spent queuing -system.physmem.totMemAccLat 194821000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 36055000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8267.20 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1235 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 501.635628 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 310.924046 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 394.932906 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 290 23.48% 23.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 197 15.95% 39.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 103 8.34% 47.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 73 5.91% 53.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 78 6.32% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 75 6.07% 66.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 32 2.59% 68.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 38 3.08% 71.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 349 28.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1235 # Bytes accessed per row activation +system.physmem.totQLat 248191131 # Total ticks spent queuing +system.physmem.totMemAccLat 430909881 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 48725000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25468.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27017.20 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 7.84 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44218.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 5.54 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 7.84 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 5.54 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.busUtilRead 0.06 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5798 # Number of row buffer hits during reads +system.physmem.readRowHits 8500 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.40 # Row buffer hit rate for reads +system.physmem.readRowHitRate 87.22 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8160150.88 # Average gap between requests -system.physmem.pageHitRate 80.40 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 55121576750 # Time in different power states -system.physmem.memoryStateTime::REF 1964820000 # Time in different power states +system.physmem.avgGap 11548536.53 # Average gap between requests +system.physmem.pageHitRate 87.22 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 107209849499 # Time in different power states +system.physmem.memoryStateTime::REF 3757780000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1754568250 # Time in different power states +system.physmem.memoryStateTime::ACT 1567991501 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 7842974 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4381 # Transaction distribution -system.membus.trans_dist::ReadResp 4381 # Transaction distribution -system.membus.trans_dist::UpgradeReq 11 # Transaction distribution -system.membus.trans_dist::UpgradeResp 11 # Transaction distribution -system.membus.trans_dist::ReadExReq 2830 # Transaction distribution -system.membus.trans_dist::ReadExResp 2830 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14444 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14444 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 461504 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 461504 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 461504 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8714000 # Layer occupancy (ticks) +system.membus.trans_dist::ReadReq 9170 # Transaction distribution +system.membus.trans_dist::ReadResp 9170 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 575 # Transaction distribution +system.membus.trans_dist::ReadExResp 575 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 19492 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 19492 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 623680 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 623680 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 9746 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 9746 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 9746 # Request fanout histogram +system.membus.reqLayer0.occupancy 11064261 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 67059990 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 88934700 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 36678579 # Number of BP lookups -system.cpu.branchPred.condPredicted 19369962 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1628976 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19217639 # Number of BTB lookups -system.cpu.branchPred.BTBHits 17291098 # Number of BTB hits +system.cpu.branchPred.lookups 37763717 # Number of BP lookups +system.cpu.branchPred.condPredicted 20179624 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1746237 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18664531 # Number of BTB lookups +system.cpu.branchPred.BTBHits 17302092 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.975142 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7036393 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 5252 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.700384 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7228871 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -339,252 +351,248 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 117685965 # number of cpu cycles simulated +system.cpu.numCycles 225081311 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 40172132 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 329927106 # Number of instructions fetch has processed -system.cpu.fetch.Branches 36678579 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24327491 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 75600101 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3327960 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 175 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2800 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 38768855 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 530996 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 117439229 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.389931 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.437439 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12228964 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 334152318 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37763717 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24530963 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 210956137 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3511516 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 130 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 514 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 89111612 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 21313 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 224941514 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.801835 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.228393 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 46731814 39.79% 39.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 7329854 6.24% 46.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6574514 5.60% 51.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6398088 5.45% 57.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4252484 3.62% 60.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5520861 4.70% 65.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3987559 3.40% 68.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3254311 2.77% 71.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 33389744 28.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 51202945 22.76% 22.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42808370 19.03% 41.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 30291484 13.47% 55.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 100638715 44.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 117439229 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.311665 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.803453 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 34271331 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16148849 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 61039844 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4384832 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1594373 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7530126 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 70364 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 389722126 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 437543 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1594373 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37031203 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5569218 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 387986 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62601924 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10254525 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 382340457 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4583661 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2043172 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 2989050 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 65700 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 432935056 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2729953830 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 376601971 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 209126886 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 372229219 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 60705837 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 14453 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 15060 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 19856485 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 96101144 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 93882304 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9920575 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10878783 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 370378331 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25182 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 358744041 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1234352 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 42331510 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 132428138 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3062 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 117439229 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.054721 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.223263 # Number of insts issued each cycle +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 224941514 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.167778 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.484585 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 27726149 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64007988 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108311612 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 23274772 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1620993 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6880386 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 135232 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 363491063 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6273375 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1620993 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 45185790 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13191872 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 337791 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 113472399 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 51132669 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 355733781 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 2913620 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 6683703 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 151097 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7653475 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 21162184 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 7934136 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 403386511 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2533827094 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 350198229 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 194873795 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 31156460 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 17017 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 17054 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 55398119 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 92429190 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 88465233 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1673754 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1845335 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 353207304 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 28026 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 346267862 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 2344729 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24807728 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 73571108 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 5906 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 224941514 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.539368 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.101787 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 21274018 18.11% 18.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14280801 12.16% 30.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 14869023 12.66% 42.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13830819 11.78% 54.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 20620243 17.56% 72.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15076681 12.84% 85.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10030176 8.54% 93.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4472440 3.81% 97.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2985028 2.54% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 40716883 18.10% 18.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 78348178 34.83% 52.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 60751241 27.01% 79.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34738398 15.44% 95.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9740749 4.33% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 637378 0.28% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8687 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 117439229 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 224941514 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 30566 0.13% 0.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5035 0.02% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 218902 0.91% 1.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 207576 0.86% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 15328 0.06% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 1824 0.01% 1.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 338916 1.41% 3.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 30886 0.13% 3.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 130712 0.54% 4.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 13684069 56.78% 60.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9438097 39.16% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9315738 7.51% 7.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7336 0.01% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 233465 0.19% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 152519 0.12% 7.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 103426 0.08% 7.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 37180 0.03% 7.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 820096 0.66% 8.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 318386 0.26% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 687826 0.55% 9.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 53407084 43.05% 52.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 58973857 47.54% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 114997382 32.06% 32.06% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2177572 0.61% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6789188 1.89% 34.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8562613 2.39% 36.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3491505 0.97% 37.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1605361 0.45% 38.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21185799 5.91% 44.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7196318 2.01% 46.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147739 1.99% 48.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 183217 0.05% 48.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 95472748 26.61% 74.93% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 89934599 25.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 110648843 31.95% 31.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148167 0.62% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6796997 1.96% 34.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8667397 2.50% 37.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3331873 0.96% 38.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592437 0.46% 38.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20937214 6.05% 44.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7180794 2.07% 46.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147102 2.06% 48.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 91783348 26.51% 75.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 85858404 24.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 358744041 # Type of FU issued -system.cpu.iq.rate 3.048316 # Inst issue rate -system.cpu.iq.fu_busy_cnt 24101911 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.067184 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 600140343 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 274631052 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 231134438 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 260123231 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 138160310 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 119811956 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 246702850 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 136143102 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 13691987 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 346267862 # Type of FU issued +system.cpu.iq.rate 1.538412 # Inst issue rate +system.cpu.iq.fu_busy_cnt 124056913 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.358269 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 756613481 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 251259921 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 223227498 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 287265399 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 126793827 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 117417697 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 302953956 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 167370819 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5034316 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10368919 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 114059 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 68397 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11506726 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6696915 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13655 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 10694 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6089616 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1395971 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 850 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 151174 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 488913 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1594373 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4558099 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 129859 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 370404619 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1080086 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 96101144 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 93882304 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 14149 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 21825 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 109033 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 68397 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1241378 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 435662 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1677040 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 354745077 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 94263609 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3998964 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1620993 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2123091 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 319754 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 353236194 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 92429190 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 88465233 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 16993 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 8080 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 327488 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 10694 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1220289 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 438322 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1658611 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 342304940 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 90585369 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3962922 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1106 # number of nop insts executed -system.cpu.iew.exec_refs 182843438 # number of memory reference insts executed -system.cpu.iew.exec_branches 32405794 # Number of branches executed -system.cpu.iew.exec_stores 88579829 # Number of stores executed -system.cpu.iew.exec_rate 3.014336 # Inst execution rate -system.cpu.iew.wb_sent 352024494 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 350946394 # cumulative count of insts written-back -system.cpu.iew.wb_producers 175212964 # num instructions producing a value -system.cpu.iew.wb_consumers 355804607 # num instructions consuming a value +system.cpu.iew.exec_nop 864 # number of nop insts executed +system.cpu.iew.exec_refs 175168098 # number of memory reference insts executed +system.cpu.iew.exec_branches 31752179 # Number of branches executed +system.cpu.iew.exec_stores 84582729 # Number of stores executed +system.cpu.iew.exec_rate 1.520806 # Inst execution rate +system.cpu.iew.wb_sent 340904975 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 340645195 # cumulative count of insts written-back +system.cpu.iew.wb_producers 153543382 # num instructions producing a value +system.cpu.iew.wb_consumers 265817565 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.982058 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.492442 # average fanout of values written-back +system.cpu.iew.wb_rate 1.513432 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.577627 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 42598489 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23000910 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1559369 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 111323846 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.944667 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.904010 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1611472 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 221213350 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.481883 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.053410 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 29334492 26.35% 26.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 21002495 18.87% 45.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 12438899 11.17% 56.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8843852 7.94% 64.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8943359 8.03% 72.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5286497 4.75% 77.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3580965 3.22% 80.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3438245 3.09% 83.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 18455042 16.58% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 87832177 39.70% 39.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 69867778 31.58% 71.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 20927331 9.46% 80.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13474141 6.09% 86.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8800060 3.98% 90.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4584952 2.07% 92.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2913270 1.32% 94.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2446398 1.11% 95.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10367243 4.69% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 111323846 # Number of insts commited each cycle -system.cpu.commit.committedInsts 273037268 # Number of instructions committed -system.cpu.commit.committedOps 327811611 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 221213350 # Number of insts commited each cycle +system.cpu.commit.committedInsts 273037831 # Number of instructions committed +system.cpu.commit.committedOps 327812213 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 168107803 # Number of memory references committed -system.cpu.commit.loads 85732225 # Number of loads committed +system.cpu.commit.refs 168107892 # Number of memory references committed +system.cpu.commit.loads 85732275 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 30563485 # Number of branches committed +system.cpu.commit.branches 30563525 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 258331174 # Number of committed integer instructions. -system.cpu.commit.function_calls 6225112 # Number of function calls committed. +system.cpu.commit.int_insts 258331704 # Number of committed integer instructions. +system.cpu.commit.function_calls 6225114 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 104312045 31.82% 31.82% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2145845 0.65% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 104312486 31.82% 31.82% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2145917 0.65% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction @@ -612,466 +620,514 @@ system.cpu.commit.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 85732225 26.15% 74.87% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 82375578 25.13% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 327811611 # Class of committed instruction -system.cpu.commit.bw_lim_events 18455042 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 327812213 # Class of committed instruction +system.cpu.commit.bw_lim_events 10367243 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 463276381 # The number of ROB reads -system.cpu.rob.rob_writes 746948197 # The number of ROB writes -system.cpu.timesIdled 5570 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 246736 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 273036656 # Number of Instructions Simulated -system.cpu.committedOps 327810999 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.431026 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.431026 # CPI: Total CPI of All Threads -system.cpu.ipc 2.320044 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.320044 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 344698387 # number of integer regfile reads -system.cpu.int_regfile_writes 141985623 # number of integer regfile writes -system.cpu.fp_regfile_reads 189510679 # number of floating regfile reads -system.cpu.fp_regfile_writes 134618624 # number of floating regfile writes -system.cpu.cc_regfile_reads 1340695625 # number of cc regfile reads -system.cpu.cc_regfile_writes 80827327 # number of cc regfile writes -system.cpu.misc_regfile_reads 1216328122 # number of misc regfile reads +system.cpu.rob.rob_reads 561656707 # The number of ROB reads +system.cpu.rob.rob_writes 705358338 # The number of ROB writes +system.cpu.timesIdled 49342 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 139797 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 273037219 # Number of Instructions Simulated +system.cpu.committedOps 327811601 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.824361 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.824361 # CPI: Total CPI of All Threads +system.cpu.ipc 1.213060 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.213060 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 331187238 # number of integer regfile reads +system.cpu.int_regfile_writes 136909181 # number of integer regfile writes +system.cpu.fp_regfile_reads 187100304 # number of floating regfile reads +system.cpu.fp_regfile_writes 132166714 # number of floating regfile writes +system.cpu.cc_regfile_reads 1296661589 # number of cc regfile reads +system.cpu.cc_regfile_writes 80246596 # number of cc regfile writes +system.cpu.misc_regfile_reads 1182269483 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.toL2Bus.throughput 23209157 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 17471 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 17471 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1022 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 12 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 12 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2846 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2846 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31432 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10234 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 41666 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1005376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 359424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 1364800 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 1364800 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 896 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 11697999 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24104992 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7380470 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 13841 # number of replacements -system.cpu.icache.tags.tagsinuse 1830.861112 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 38751311 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15711 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 2466.508243 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1830.861112 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.893975 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.893975 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1870 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1522 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.913086 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 77553427 # Number of tag accesses -system.cpu.icache.tags.data_accesses 77553427 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 38751328 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 38751328 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 38751328 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 38751328 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 38751328 # number of overall hits -system.cpu.icache.overall_hits::total 38751328 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17524 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17524 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17524 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17524 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17524 # number of overall misses -system.cpu.icache.overall_misses::total 17524 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 439561740 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 439561740 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 439561740 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 439561740 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 439561740 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 439561740 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 38768852 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 38768852 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 38768852 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 38768852 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 38768852 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 38768852 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000452 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000452 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000452 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000452 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000452 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000452 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25083.413604 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25083.413604 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25083.413604 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25083.413604 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25083.413604 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25083.413604 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 684 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.toL2Bus.trans_dist::ReadReq 2029653 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2029653 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 966282 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 49309 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 220486 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 220486 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1430858 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4034802 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5465660 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45758528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160034560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205793088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 50213 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3265775 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.015099 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.121946 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 3216466 98.49% 98.49% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 49309 1.51% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3265775 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2574531466 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1074172389 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2301537734 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) +system.cpu.icache.tags.replacements 715368 # number of replacements +system.cpu.icache.tags.tagsinuse 511.871967 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 88391816 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 715880 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 123.472951 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 275609500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.871967 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999750 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999750 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 66 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 178939093 # Number of tag accesses +system.cpu.icache.tags.data_accesses 178939093 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 88391816 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 88391816 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 88391816 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 88391816 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 88391816 # number of overall hits +system.cpu.icache.overall_hits::total 88391816 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 719790 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 719790 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 719790 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 719790 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 719790 # number of overall misses +system.cpu.icache.overall_misses::total 719790 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 5791847611 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 5791847611 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 5791847611 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 5791847611 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 5791847611 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 5791847611 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 89111606 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 89111606 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 89111606 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 89111606 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 89111606 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 89111606 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008077 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008077 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008077 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008077 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008077 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008077 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8046.579712 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8046.579712 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8046.579712 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8046.579712 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8046.579712 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8046.579712 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 12631 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 17 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1514 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 8.342801 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 17 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1801 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1801 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1801 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1801 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1801 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1801 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15723 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15723 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15723 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15723 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15723 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15723 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 350218008 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 350218008 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 350218008 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 350218008 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 350218008 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 350218008 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000406 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000406 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000406 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000406 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000406 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000406 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22274.248426 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22274.248426 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22274.248426 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22274.248426 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22274.248426 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22274.248426 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3909 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3909 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3909 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3909 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3909 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3909 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 715881 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 715881 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 715881 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 715881 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 715881 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 715881 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 4688303087 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 4688303087 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 4688303087 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 4688303087 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 4688303087 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 4688303087 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008034 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.008034 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.008034 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6548.997790 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6548.997790 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6548.997790 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 6548.997790 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6548.997790 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 6548.997790 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 6641923 # number of hwpf identified +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 7386 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6574564 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 13578 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2097 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 44298 # number of hwpf issued +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 135685 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3837.051468 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 13121 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5294 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.478466 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 8320.579960 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2794148 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 9718 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 287.522947 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 357.151307 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2707.112582 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 772.787579 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.010899 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.082615 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.023584 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.117098 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5294 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1246 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3911 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.161560 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 178837 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 178837 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 12742 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 286 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13028 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1022 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1022 # number of Writeback hits +system.cpu.l2cache.tags.occ_blocks::writebacks 2574.248018 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 441.129211 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 367.415546 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 4937.787185 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.157120 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.026924 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.022425 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.301379 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.507848 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 5676 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 4042 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 59 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 84 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 572 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4961 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 626 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 123 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3234 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.346436 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.246704 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 51678510 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 51678510 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 714431 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1313042 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2027473 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 966282 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 966282 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12742 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 302 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13044 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12742 # 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number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 4292 # number of overall misses -system.cpu.l2cache.overall_misses::total 7259 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 207032250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 106837750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 313870000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 202417250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 202417250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 207032250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 309255000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 516287250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 207032250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 309255000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 516287250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 15709 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1748 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 17457 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1022 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1022 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 12 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 12 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2846 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2846 # 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average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59940.434783 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59940.434783 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68184.623431 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61138.865293 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63074.424138 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68184.623431 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61138.865293 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 15118.226150 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 16930.724184 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1384 # number of replacements -system.cpu.dcache.tags.tagsinuse 3114.575432 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 161730326 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4594 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 35204.685677 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3114.575432 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.760394 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.760394 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3210 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 686 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2462 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.783691 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 323517792 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 323517792 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 79590771 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 79590771 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82030417 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82030417 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 87045 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 87045 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11127 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11127 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 1533746 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.875745 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 163803379 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1534258 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 106.763907 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 61007500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.875745 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999757 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 336684382 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336684382 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 82726080 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 82726080 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80985064 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80985064 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 70429 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 70429 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 161621188 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 161621188 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 161708233 # number of overall hits -system.cpu.dcache.overall_hits::total 161708233 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4059 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4059 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22243 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22243 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 40 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 40 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 26302 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 26302 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 26342 # number of overall misses -system.cpu.dcache.overall_misses::total 26342 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 234715222 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 234715222 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1291834537 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1291834537 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 170250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1526549759 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1526549759 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1526549759 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1526549759 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 79594830 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 79594830 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 82052660 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 82052660 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 87085 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 87085 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11129 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11129 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 163711144 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 163711144 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 163781573 # number of overall hits +system.cpu.dcache.overall_hits::total 163781573 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2704026 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2704026 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1067635 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1067635 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 19 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 19 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 3771661 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3771661 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3771680 # number of overall misses +system.cpu.dcache.overall_misses::total 3771680 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 21403617484 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 21403617484 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8344449821 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8344449821 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 164500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 164500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29748067305 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29748067305 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29748067305 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29748067305 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 85430106 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 85430106 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 70448 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 70448 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 161647490 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 161647490 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 161734575 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 161734575 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000051 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000271 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000271 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000459 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.000459 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000180 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000180 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000163 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000163 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000163 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000163 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57825.873861 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 57825.873861 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58078.251000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 58078.251000 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 58039.303437 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 58039.303437 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 57951.171475 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 57951.171475 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32404 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1444 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 548 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 59.131387 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 103.142857 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 167482805 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 167482805 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 167553253 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 167553253 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.031652 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.031652 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013012 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013012 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000270 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000270 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.022520 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.022520 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.022510 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.022510 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7915.462900 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 7915.462900 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7815.826402 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7815.826402 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32900 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 32900 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 7887.259037 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 7887.259037 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 7887.219304 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 7887.219304 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 761243 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 111844 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 6.806293 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1022 # number of writebacks -system.cpu.dcache.writebacks::total 1022 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2332 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2332 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19388 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 19388 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 21720 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 21720 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 21720 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 21720 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1727 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2855 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2855 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 24 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 24 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4582 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4582 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4606 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4606 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109924790 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 109924790 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 205574740 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 205574740 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1745000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1745000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 315499530 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 315499530 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 317244530 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 317244530 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000276 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000276 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000028 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000028 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63650.718008 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63650.718008 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72005.162872 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72005.162872 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 72708.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 72708.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68856.292012 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68856.292012 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68876.363439 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68876.363439 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 966282 # number of writebacks +system.cpu.dcache.writebacks::total 966282 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1390265 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1390265 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 847147 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 847147 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2237412 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2237412 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2237412 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2237412 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313761 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1313761 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220488 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 220488 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1534249 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1534249 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1534260 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1534260 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9295842016 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9295842016 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1592020910 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1592020910 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 638250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 638250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10887862926 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10887862926 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10888501176 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10888501176 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015378 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015378 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002687 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002687 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000156 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000156 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009161 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.009161 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009157 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.009157 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7075.748189 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7075.748189 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7220.442428 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7220.442428 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58022.727273 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58022.727273 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7096.542299 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 7096.542299 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7096.907419 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 7096.907419 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index d78fd5112..2a622c7e9 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.201717 # Nu sim_ticks 201717313500 # Number of ticks simulated final_tick 201717313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1169681 # Simulator instruction rate (inst/s) -host_op_rate 1404332 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 864148101 # Simulator tick rate (ticks/s) -host_mem_usage 314684 # Number of bytes of host memory used -host_seconds 233.43 # Real time elapsed on the host +host_inst_rate 1306299 # Simulator instruction rate (inst/s) +host_op_rate 1568357 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 965080142 # Simulator tick rate (ticks/s) +host_mem_usage 305108 # Number of bytes of host memory used +host_seconds 209.02 # Real time elapsed on the host sim_insts 273037594 # Number of instructions simulated sim_ops 327811949 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,36 @@ system.physmem.bw_write::total 1983209850 # Wr system.physmem.bw_total::cpu.inst 6913839312 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4366293422 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11280132734 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 11280132734 # Throughput (bytes/s) -system.membus.data_through_bus 2275398071 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 434895827 # Transaction distribution +system.membus.trans_dist::ReadResp 434906722 # Transaction distribution +system.membus.trans_dist::WriteReq 82052672 # Transaction distribution +system.membus.trans_dist::WriteResp 82052672 # Transaction distribution +system.membus.trans_dist::SoftPFReq 54062 # Transaction distribution +system.membus.trans_dist::SoftPFResp 54062 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 10895 # Transaction distribution +system.membus.trans_dist::StoreCondReq 10895 # Transaction distribution +system.membus.trans_dist::StoreCondResp 10895 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 697320546 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336728156 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1034048702 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1394641092 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 2275398071 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 517024351 # Request fanout histogram +system.membus.snoop_fanout::mean 4.674359 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 168364078 32.56% 32.56% # Request fanout histogram +system.membus.snoop_fanout::5 348660273 67.44% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 517024351 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 57cca8ea4..46629c208 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.517235 # Nu sim_ticks 517235411000 # Number of ticks simulated final_tick 517235411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 749544 # Simulator instruction rate (inst/s) -host_op_rate 899855 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1421469107 # Simulator tick rate (ticks/s) -host_mem_usage 324416 # Number of bytes of host memory used -host_seconds 363.87 # Real time elapsed on the host +host_inst_rate 795879 # Simulator instruction rate (inst/s) +host_op_rate 955482 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1509341441 # Simulator tick rate (ticks/s) +host_mem_usage 314596 # Number of bytes of host memory used +host_seconds 342.69 # Real time elapsed on the host sim_insts 272739285 # Number of instructions simulated sim_ops 327433743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 322824 # In system.physmem.bw_total::cpu.inst 322824 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 522532 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 845356 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3976 # Transaction distribution system.membus.trans_dist::ReadResp 3976 # Transaction distribution system.membus.trans_dist::ReadExReq 2856 # Transaction distribution system.membus.trans_dist::ReadExResp 2856 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 437248 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 6833 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 6833 # Request fanout histogram system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks) @@ -561,7 +569,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 2608205 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution @@ -570,11 +577,25 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31206 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9954 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 41160 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 998592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 1349056 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 998592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 21079 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 21079 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 21079 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks) |