diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:34 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:34 -0600 |
| commit | cfb805cc71bd1c4b72691b69faa879663e548c11 (patch) | |
| tree | 4ef4be8b34eb3722e303546a96956b1adaa3315b /tests/long/se/30.eon/ref | |
| parent | 612f8f074fa1099cf70faf495d46cc647762a031 (diff) | |
| download | gem5-cfb805cc71bd1c4b72691b69faa879663e548c11.tar.xz | |
stats: update stats for ARMv8 changes
Diffstat (limited to 'tests/long/se/30.eon/ref')
9 files changed, 1006 insertions, 676 deletions
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index 9e26a822b..2cd58faa0 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -67,6 +68,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fetchBufferSize=64 @@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -179,10 +182,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -190,6 +218,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -544,24 +573,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -569,6 +634,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -617,7 +683,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index 704a64531..d9e911681 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 22:48:11 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:23:42 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x4718040 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 @@ -13,4 +14,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.060000 -Exiting @ tick 68509635500 because target called exit() +Exiting @ tick 68503867000 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index d1e8937b6..634fe5f9a 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,58 +1,58 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068510 # Number of seconds simulated -sim_ticks 68509635500 # Number of ticks simulated -final_tick 68509635500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.068504 # Number of seconds simulated +sim_ticks 68503867000 # Number of ticks simulated +final_tick 68503867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 157844 # Simulator instruction rate (inst/s) -host_op_rate 201796 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39605771 # Simulator tick rate (ticks/s) -host_mem_usage 257252 # Number of bytes of host memory used -host_seconds 1729.79 # Real time elapsed on the host +host_inst_rate 147835 # Simulator instruction rate (inst/s) +host_op_rate 189000 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37091215 # Simulator tick rate (ticks/s) +host_mem_usage 278164 # Number of bytes of host memory used +host_seconds 1846.90 # Real time elapsed on the host sim_insts 273036725 # Number of instructions simulated sim_ops 349064449 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 194560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272384 # Number of bytes read from this memory -system.physmem.bytes_read::total 466944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 194560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 194560 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3040 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4256 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7296 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2839892 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3975849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6815742 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2839892 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2839892 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2839892 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3975849 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6815742 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7296 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 193984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272256 # Number of bytes read from this memory +system.physmem.bytes_read::total 466240 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 193984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 193984 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3031 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4254 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7285 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2831723 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3974316 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6806039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2831723 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2831723 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2831723 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3974316 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6806039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7286 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7296 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7286 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 466944 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 466304 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 466944 # Total read bytes from the system interface side +system.physmem.bytesReadSys 466304 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 607 # Per bank write bursts -system.physmem.perBankRdBursts::1 801 # Per bank write bursts +system.physmem.perBankRdBursts::0 606 # Per bank write bursts +system.physmem.perBankRdBursts::1 800 # Per bank write bursts system.physmem.perBankRdBursts::2 608 # Per bank write bursts system.physmem.perBankRdBursts::3 526 # Per bank write bursts -system.physmem.perBankRdBursts::4 444 # Per bank write bursts -system.physmem.perBankRdBursts::5 356 # Per bank write bursts -system.physmem.perBankRdBursts::6 162 # Per bank write bursts -system.physmem.perBankRdBursts::7 220 # Per bank write bursts +system.physmem.perBankRdBursts::4 443 # Per bank write bursts +system.physmem.perBankRdBursts::5 354 # Per bank write bursts +system.physmem.perBankRdBursts::6 164 # Per bank write bursts +system.physmem.perBankRdBursts::7 219 # Per bank write bursts system.physmem.perBankRdBursts::8 207 # Per bank write bursts -system.physmem.perBankRdBursts::9 294 # Per bank write bursts -system.physmem.perBankRdBursts::10 324 # Per bank write bursts -system.physmem.perBankRdBursts::11 416 # Per bank write bursts +system.physmem.perBankRdBursts::9 291 # Per bank write bursts +system.physmem.perBankRdBursts::10 322 # Per bank write bursts +system.physmem.perBankRdBursts::11 415 # Per bank write bursts system.physmem.perBankRdBursts::12 529 # Per bank write bursts system.physmem.perBankRdBursts::13 687 # Per bank write bursts system.physmem.perBankRdBursts::14 611 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 68509447000 # Total gap between requests +system.physmem.totGap 68503846500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7296 # Read request sizes (log2) +system.physmem.readPktSize::6 7286 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4373 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 2103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 570 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 177 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 567 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 176 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 66 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -154,80 +154,83 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1278 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 364.419405 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 165.521659 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 755.556461 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 528 41.31% 41.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 217 16.98% 58.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 132 10.33% 68.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 73 5.71% 74.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 38 2.97% 77.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 36 2.82% 80.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 30 2.35% 82.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 40 3.13% 85.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 15 1.17% 86.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 24 1.88% 88.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 7 0.55% 89.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 13 1.02% 90.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 4 0.31% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 10 0.78% 91.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 5 0.39% 91.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 6 0.47% 92.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 7 0.55% 92.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 7 0.55% 93.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 3 0.23% 93.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 4 0.31% 93.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 3 0.23% 94.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 6 0.47% 94.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 5 0.39% 94.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 5 0.39% 95.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 2 0.16% 95.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 5 0.39% 95.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 4 0.31% 96.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 2 0.16% 96.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 2 0.16% 96.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 3 0.23% 96.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 4 0.31% 97.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 2 0.16% 97.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.08% 97.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 2 0.16% 97.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.08% 97.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 2 0.16% 97.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.08% 97.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.08% 97.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.08% 97.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 2 0.16% 98.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.08% 98.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 2 0.16% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 2 0.16% 98.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 2 0.16% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.08% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 2 0.16% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.08% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.08% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 1286 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 361.604977 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 163.647663 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 753.981601 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 537 41.76% 41.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 220 17.11% 58.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 131 10.19% 69.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 77 5.99% 75.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 39 3.03% 78.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 38 2.95% 81.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 26 2.02% 83.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 31 2.41% 85.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 17 1.32% 86.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 23 1.79% 88.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 6 0.47% 89.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 16 1.24% 90.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 3 0.23% 90.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 8 0.62% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 7 0.54% 91.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 7 0.54% 92.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 5 0.39% 92.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 8 0.62% 93.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 5 0.39% 93.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 6 0.47% 94.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 1 0.08% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 4 0.31% 94.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 4 0.31% 94.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 6 0.47% 95.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.23% 95.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 3 0.23% 95.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 3 0.23% 95.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 4 0.31% 96.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 2 0.16% 96.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 3 0.23% 96.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 2 0.16% 96.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 4 0.31% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 2 0.16% 97.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.08% 97.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 2 0.16% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 1 0.08% 97.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 1 0.08% 97.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.08% 97.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.08% 97.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.08% 97.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 2 0.16% 98.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.08% 98.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 2 0.16% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 1 0.08% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 1 0.08% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.08% 98.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.08% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 2 0.16% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.08% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 1 0.08% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.08% 99.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::4096-4097 1 0.08% 99.14% # Bytes accessed per row activation system.physmem.bytesPerActivate::4160-4161 1 0.08% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 3 0.23% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 3 0.23% 99.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::4736-4737 1 0.08% 99.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::6464-6465 1 0.08% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::6528-6529 1 0.08% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.08% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 1 0.08% 99.77% # Bytes accessed per row activation system.physmem.bytesPerActivate::7552-7553 1 0.08% 99.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 2 0.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1278 # Bytes accessed per row activation -system.physmem.totQLat 61296000 # Total ticks spent queuing -system.physmem.totMemAccLat 197202250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 36480000 # Total ticks spent in databus transfers -system.physmem.totBankLat 99426250 # Total ticks spent accessing banks -system.physmem.avgQLat 8401.32 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13627.50 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::total 1286 # Bytes accessed per row activation +system.physmem.totQLat 62980000 # Total ticks spent queuing +system.physmem.totMemAccLat 198080000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36430000 # Total ticks spent in databus transfers +system.physmem.totBankLat 98670000 # Total ticks spent accessing banks +system.physmem.avgQLat 8643.97 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13542.41 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27028.82 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.82 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27186.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.81 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.82 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.81 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage @@ -235,40 +238,61 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6018 # Number of row buffer hits during reads +system.physmem.readRowHits 6000 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.48 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.35 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9390000.96 # Average gap between requests -system.physmem.pageHitRate 82.48 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.14 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 6815742 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4471 # Transaction distribution -system.membus.trans_dist::ReadResp 4471 # Transaction distribution +system.physmem.avgGap 9402120.02 # Average gap between requests +system.physmem.pageHitRate 82.35 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.05 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 6806039 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4462 # Transaction distribution +system.membus.trans_dist::ReadResp 4461 # Transaction distribution system.membus.trans_dist::UpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 2825 # Transaction distribution -system.membus.trans_dist::ReadExResp 2825 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14596 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14596 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466944 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 466944 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 466944 # Total data (bytes) +system.membus.trans_dist::ReadExReq 2824 # Transaction distribution +system.membus.trans_dist::ReadExResp 2824 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14575 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14575 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466240 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 466240 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 466240 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8937500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8931500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 67899498 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 67747998 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 35425567 # Number of BP lookups -system.cpu.branchPred.condPredicted 21222314 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1660593 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19605313 # Number of BTB lookups -system.cpu.branchPred.BTBHits 16823422 # Number of BTB hits +system.cpu.branchPred.lookups 35407535 # Number of BP lookups +system.cpu.branchPred.condPredicted 21210003 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1658535 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19582924 # Number of BTB lookups +system.cpu.branchPred.BTBHits 16814113 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 85.810525 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6781780 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 8434 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 85.861095 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6780652 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 8453 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -290,6 +314,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -312,100 +357,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 137019272 # number of cpu cycles simulated +system.cpu.numCycles 137007735 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39008530 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 318058207 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35425567 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23605202 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70950828 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6887573 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 21494775 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 105 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1573 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 38995510 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 317974758 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35407535 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23594765 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70934448 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6878177 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 21511393 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 109 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1738 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 61 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37609299 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 515132 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 136671204 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.983776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.454359 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 37596145 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 512137 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 136651264 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.983546 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.454335 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66353464 48.55% 48.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6794042 4.97% 53.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5704725 4.17% 57.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6102503 4.47% 62.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4920388 3.60% 65.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4084365 2.99% 68.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3186134 2.33% 71.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4139625 3.03% 74.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35385958 25.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66349844 48.55% 48.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6791529 4.97% 53.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5702360 4.17% 57.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6103499 4.47% 62.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4918940 3.60% 65.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4085838 2.99% 68.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3180821 2.33% 71.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4138782 3.03% 74.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35379651 25.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 136671204 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258544 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.321266 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45524127 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16648036 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 66820925 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2531461 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5146655 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7342433 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 69027 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401839978 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 214083 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5146655 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 51074305 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1910036 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 332499 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 63741314 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14466395 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 394244633 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 55 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1658642 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10186296 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1132 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 432779208 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2333721873 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1575557795 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 200430073 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 136651264 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258435 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.320853 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45513422 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16662187 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 66798256 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2538078 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5139321 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7340905 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69056 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401756741 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 208904 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5139321 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 51060721 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1905439 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 332675 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 63727748 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14485360 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 394162913 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 18 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1657895 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10187119 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 22377 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 432668253 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2737675688 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1575239963 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 200387111 # Number of floating rename lookups system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 48213015 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11816 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11815 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 36510705 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 103606610 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 91402094 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4304684 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5331956 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 384603029 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22794 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 374241110 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1211414 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 34812310 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 87759919 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 674 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 136671204 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.738259 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.024772 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 48102060 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11946 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11945 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 36528458 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 103595819 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 91394334 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4295156 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5297473 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 384542604 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22919 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 374214780 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1210476 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 34753044 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 100302329 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 799 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 136651264 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.738466 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.024544 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 25129949 18.39% 18.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19927179 14.58% 32.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20562891 15.05% 48.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18173263 13.30% 61.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24036101 17.59% 78.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15736190 11.51% 90.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8814920 6.45% 96.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3372202 2.47% 99.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 918509 0.67% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 25105050 18.37% 18.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19938594 14.59% 32.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20566375 15.05% 48.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18171632 13.30% 61.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 24028761 17.58% 78.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15737538 11.52% 90.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8814188 6.45% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3372330 2.47% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 916796 0.67% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 136671204 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 136651264 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8708 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4694 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8713 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4693 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -424,22 +469,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 46360 0.26% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 46317 0.26% 0.34% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7648 0.04% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 433 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 190801 1.08% 1.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 4328 0.02% 1.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 241338 1.36% 2.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9265240 52.28% 55.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7952555 44.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 3518 0.02% 0.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 440 0.00% 0.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 186929 1.05% 1.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 4248 0.02% 1.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241299 1.36% 2.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9275439 52.33% 55.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7953254 44.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 126474576 33.79% 33.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2175710 0.58% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 126461637 33.79% 33.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2175765 0.58% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.38% # Type of FU issued @@ -450,7 +495,7 @@ system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.38% # Ty system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 3 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 4 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.38% # Type of FU issued @@ -458,93 +503,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.38% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6781686 1.81% 36.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6779975 1.81% 36.19% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8476200 2.26% 38.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3430464 0.92% 39.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1596092 0.43% 39.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20867035 5.58% 45.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7174148 1.92% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7130628 1.91% 49.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101661693 27.16% 76.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88297588 23.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8474577 2.26% 38.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3430301 0.92% 39.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1595259 0.43% 39.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20865413 5.58% 45.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7172902 1.92% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7130224 1.91% 49.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101650995 27.16% 76.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88302442 23.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 374241110 # Type of FU issued -system.cpu.iq.rate 2.731303 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17722107 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047355 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654665747 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 289075917 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 250124446 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 249421198 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 130376340 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118073548 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 263342959 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 128620258 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11085750 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 374214780 # Type of FU issued +system.cpu.iq.rate 2.731341 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17724852 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047365 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654627146 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 288999508 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 250114053 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249389006 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 130333197 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118063719 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 263337797 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128601835 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11086522 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 8957862 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 109225 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14255 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9026511 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8947071 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 108758 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14277 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9018751 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 173986 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1905 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 174712 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1900 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5146655 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 274797 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 35672 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 384627381 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 873173 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 103606610 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 91402094 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11760 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 340 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 365 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14255 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1300817 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 370830 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1671647 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 370280641 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100372061 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3960469 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 5139321 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 272764 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 35129 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 384567184 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 874047 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 103595819 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 91394334 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11885 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 347 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 280 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14277 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1299093 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 369514 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1668607 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 370257441 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100364532 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3957339 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1558 # number of nop insts executed -system.cpu.iew.exec_refs 187586293 # number of memory reference insts executed -system.cpu.iew.exec_branches 32011507 # Number of branches executed -system.cpu.iew.exec_stores 87214232 # Number of stores executed -system.cpu.iew.exec_rate 2.702398 # Inst execution rate -system.cpu.iew.wb_sent 368867964 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 368197994 # cumulative count of insts written-back -system.cpu.iew.wb_producers 183086265 # num instructions producing a value -system.cpu.iew.wb_consumers 363871713 # num instructions consuming a value +system.cpu.iew.exec_nop 1661 # number of nop insts executed +system.cpu.iew.exec_refs 187583075 # number of memory reference insts executed +system.cpu.iew.exec_branches 32009347 # Number of branches executed +system.cpu.iew.exec_stores 87218543 # Number of stores executed +system.cpu.iew.exec_rate 2.702456 # Inst execution rate +system.cpu.iew.wb_sent 368846220 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 368177772 # cumulative count of insts written-back +system.cpu.iew.wb_producers 183055174 # num instructions producing a value +system.cpu.iew.wb_consumers 363803620 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.687199 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.503162 # average fanout of values written-back +system.cpu.iew.wb_rate 2.687277 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.503170 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 35562440 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 35502239 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1591916 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 131524549 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.653992 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.659233 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1589851 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 131511943 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.654246 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.658719 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 34720675 26.40% 26.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 28457654 21.64% 48.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13339371 10.14% 58.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11431101 8.69% 66.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13773309 10.47% 77.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7413510 5.64% 82.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3874860 2.95% 85.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3887136 2.96% 88.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14626933 11.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34696225 26.38% 26.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 28452590 21.63% 48.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13345612 10.15% 58.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11442919 8.70% 66.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13780020 10.48% 77.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7417113 5.64% 82.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3869989 2.94% 85.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3892889 2.96% 88.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14614586 11.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 131524549 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 131511943 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037337 # Number of instructions committed system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -555,238 +600,238 @@ system.cpu.commit.branches 30563497 # Nu system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14626933 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14614586 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 501522594 # The number of ROB reads -system.cpu.rob.rob_writes 774405807 # The number of ROB writes -system.cpu.timesIdled 6645 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 348068 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 501462134 # The number of ROB reads +system.cpu.rob.rob_writes 774278104 # The number of ROB writes +system.cpu.timesIdled 6640 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 356471 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273036725 # Number of Instructions Simulated system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated -system.cpu.cpi 0.501835 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.501835 # CPI: Total CPI of All Threads -system.cpu.ipc 1.992688 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.992688 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1769988396 # number of integer regfile reads -system.cpu.int_regfile_writes 233047297 # number of integer regfile writes -system.cpu.fp_regfile_reads 188164665 # number of floating regfile reads -system.cpu.fp_regfile_writes 132532739 # number of floating regfile writes -system.cpu.misc_regfile_reads 566941334 # number of misc regfile reads +system.cpu.cpi 0.501792 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.501792 # CPI: Total CPI of All Threads +system.cpu.ipc 1.992856 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.992856 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1769894079 # number of integer regfile reads +system.cpu.int_regfile_writes 233026497 # number of integer regfile writes +system.cpu.fp_regfile_reads 188140638 # number of floating regfile reads +system.cpu.fp_regfile_writes 132514898 # number of floating regfile writes +system.cpu.misc_regfile_reads 1201076625 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.toL2Bus.throughput 20093174 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 17631 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 17631 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1036 # Transaction distribution +system.cpu.toL2Bus.throughput 20069641 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 17607 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 17606 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1035 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2842 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2842 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31714 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10268 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 41982 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1014720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 1376320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 1376320 # Total data (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 2841 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2841 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31671 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10259 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 41930 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1013312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 1374592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 1374592 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 11791500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 11777500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24322738 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24288488 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7408962 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7388212 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 13968 # number of replacements -system.cpu.icache.tags.tagsinuse 1848.251388 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 37591948 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15858 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 2370.535250 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 13947 # number of replacements +system.cpu.icache.tags.tagsinuse 1848.346697 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 37578823 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15836 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2372.999684 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1848.251388 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.902466 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.902466 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1890 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 206 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1848.346697 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.902513 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.902513 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1889 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 205 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1526 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.922852 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 75234453 # Number of tag accesses -system.cpu.icache.tags.data_accesses 75234453 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 37591948 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37591948 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37591948 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37591948 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37591948 # number of overall hits -system.cpu.icache.overall_hits::total 37591948 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17349 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17349 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17349 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17349 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17349 # number of overall misses -system.cpu.icache.overall_misses::total 17349 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 451171984 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 451171984 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 451171984 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 451171984 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 451171984 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 451171984 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37609297 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37609297 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37609297 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37609297 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37609297 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37609297 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 1530 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.922363 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 75208123 # Number of tag accesses +system.cpu.icache.tags.data_accesses 75208123 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 37578823 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37578823 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37578823 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37578823 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37578823 # number of overall hits +system.cpu.icache.overall_hits::total 37578823 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17320 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17320 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17320 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17320 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17320 # number of overall misses +system.cpu.icache.overall_misses::total 17320 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 450229234 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 450229234 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 450229234 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 450229234 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 450229234 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 450229234 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37596143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37596143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37596143 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37596143 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37596143 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37596143 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000461 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000461 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000461 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000461 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000461 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000461 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26005.647818 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 26005.647818 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 26005.647818 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 26005.647818 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 26005.647818 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 26005.647818 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2002 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25994.759469 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25994.759469 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25994.759469 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25994.759469 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25994.759469 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25994.759469 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2351 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 25 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 87.043478 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 94.040000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1490 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1490 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1490 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1490 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1490 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1490 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15859 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15859 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15859 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15859 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15859 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15859 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 359132259 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 359132259 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 359132259 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 359132259 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 359132259 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 359132259 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000422 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000422 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000422 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22645.328142 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22645.328142 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22645.328142 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22645.328142 # average overall mshr miss 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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176370000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 254119500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 430489500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191738 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.807562 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253645 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 164034250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 164034250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 177153750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 254063250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 431217000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 177153750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 254063250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 431217000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191487 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.808366 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253480 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994018 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994018 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191738 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922410 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.356441 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191738 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922410 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.356441 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58016.447368 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62114.605171 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59328.114516 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994016 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994016 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191487 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922777 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.356388 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191487 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922777 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.356388 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58428.017810 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62957.342657 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59879.594352 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58489.734513 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58489.734513 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58016.447368 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59708.529135 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59003.495066 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58016.447368 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59708.529135 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59003.495066 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58085.782578 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58085.782578 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58428.017810 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59723.377997 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59184.326105 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58428.017810 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59723.377997 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59184.326105 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1417 # number of replacements -system.cpu.dcache.tags.tagsinuse 3102.941006 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 170982340 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4614 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37057.290854 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1413 # number of replacements +system.cpu.dcache.tags.tagsinuse 3103.986618 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 170973728 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4610 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37087.576573 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3102.941006 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.757554 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.757554 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3103.986618 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.757809 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.757809 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3197 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 684 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 682 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2446 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2449 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.780518 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 342019754 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 342019754 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 88929043 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88929043 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82031381 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82031381 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11009 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11009 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 342002086 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 342002086 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 88920204 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88920204 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82031597 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82031597 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11020 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11020 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 170960424 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 170960424 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 170960424 # number of overall hits -system.cpu.dcache.overall_hits::total 170960424 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3956 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3956 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 21284 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 21284 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 170951801 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 170951801 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 170951801 # number of overall hits +system.cpu.dcache.overall_hits::total 170951801 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3952 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3952 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 21068 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 21068 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25240 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25240 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25240 # number of overall misses -system.cpu.dcache.overall_misses::total 25240 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 235586955 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 235586955 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1260992389 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1260992389 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 25020 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25020 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25020 # number of overall misses +system.cpu.dcache.overall_misses::total 25020 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 237491705 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 237491705 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1258064893 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1258064893 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170250 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 170250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1496579344 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1496579344 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1496579344 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1496579344 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88932999 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88932999 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 1495556598 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1495556598 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1495556598 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1495556598 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88924156 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88924156 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11011 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11011 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11022 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11022 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 170985664 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 170985664 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 170985664 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 170985664 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 170976821 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 170976821 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 170976821 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 170976821 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000044 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000259 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000259 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000182 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000182 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000148 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000148 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000148 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000148 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59551.808645 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59551.808645 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59246.024666 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59246.024666 # average WriteReq miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000257 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000257 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000181 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000181 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000146 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000146 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000146 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000146 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60094.054909 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60094.054909 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59714.490839 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59714.490839 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59293.951823 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59293.951823 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59293.951823 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59293.951823 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 28312 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59774.444365 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59774.444365 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59774.444365 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59774.444365 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 27944 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1224 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 411 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 406 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 68.885645 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 68.827586 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 102 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1036 # number of writebacks -system.cpu.dcache.writebacks::total 1036 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2182 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2182 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18442 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18442 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1035 # number of writebacks +system.cpu.dcache.writebacks::total 1035 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2181 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2181 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18227 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18227 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20624 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20624 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20624 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20624 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1774 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1774 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2842 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2842 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4616 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4616 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4616 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4616 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 114384040 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 114384040 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 203208498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 203208498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 317592538 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 317592538 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 317592538 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 317592538 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 20408 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20408 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20408 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20408 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1771 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1771 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2841 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2841 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4612 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4612 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4612 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4612 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 115481540 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 115481540 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 201937248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 201937248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 317418788 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 317418788 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 317418788 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 317418788 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -983,14 +1028,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64478.038331 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64478.038331 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71501.934553 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71501.934553 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68802.542894 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68802.542894 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68802.542894 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68802.542894 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65206.967815 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65206.967815 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71079.636748 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71079.636748 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68824.542064 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68824.542064 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68824.542064 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68824.542064 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini index 098c10a60..d33135638 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=atomic mem_ranges= memories=system.physmem @@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain [system.cpu] type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload +children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fastmem=false @@ -55,6 +57,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -77,10 +80,35 @@ workload=system.cpu.workload dcache_port=system.membus.slave[2] icache_port=system.membus.slave[1] +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[6] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -88,6 +116,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -100,24 +129,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[5] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -125,6 +190,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -168,7 +234,7 @@ system=system use_default_range=false width=8 master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.physmem] type=SimpleMemory diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout index b3ebb4d02..563fc0af8 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 22:52:31 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:27:26 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x56d96c0 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index 02fd51087..b6b6bed83 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.212344 # Nu sim_ticks 212344043000 # Number of ticks simulated final_tick 212344043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1679583 # Simulator instruction rate (inst/s) -host_op_rate 2147266 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1306228104 # Simulator tick rate (ticks/s) -host_mem_usage 246496 # Number of bytes of host memory used -host_seconds 162.56 # Real time elapsed on the host +host_inst_rate 1312619 # Simulator instruction rate (inst/s) +host_op_rate 1678120 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1020836459 # Simulator tick rate (ticks/s) +host_mem_usage 266392 # Number of bytes of host memory used +host_seconds 208.01 # Real time elapsed on the host sim_insts 273037663 # Number of instructions simulated sim_ops 349065399 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -39,6 +39,27 @@ system.membus.throughput 10715621794 # Th system.membus.data_through_bus 2275398455 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -60,6 +81,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -93,7 +135,7 @@ system.cpu.num_func_calls 12448615 # nu system.cpu.num_conditional_control_insts 18105897 # number of instructions that are conditional controls system.cpu.num_int_insts 279584918 # number of integer instructions system.cpu.num_fp_insts 114216705 # number of float instructions -system.cpu.num_int_register_reads 1887652153 # number of times the integer registers were read +system.cpu.num_int_register_reads 2254222459 # number of times the integer registers were read system.cpu.num_int_register_writes 251197905 # number of times the integer registers were written system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini index aa5380744..3089e084a 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,19 +42,21 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -105,10 +108,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -116,6 +144,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -163,24 +192,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -188,6 +253,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -236,7 +302,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout index 32b55c30c..9d7fb2434 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 22:52:55 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:29:04 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x4c37d00 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 5bfa9270c..7d607329f 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.525834 # Nu sim_ticks 525834342000 # Number of ticks simulated final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 870200 # Simulator instruction rate (inst/s) -host_op_rate 1112519 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1677723175 # Simulator tick rate (ticks/s) -host_mem_usage 255236 # Number of bytes of host memory used -host_seconds 313.42 # Real time elapsed on the host +host_inst_rate 719381 # Simulator instruction rate (inst/s) +host_op_rate 919702 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1386947293 # Simulator tick rate (ticks/s) +host_mem_usage 276148 # Number of bytes of host memory used +host_seconds 379.13 # Real time elapsed on the host sim_insts 272739283 # Number of instructions simulated sim_ops 348687122 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -45,6 +45,27 @@ system.membus.reqLayer0.utilization 0.0 # La system.membus.respLayer1.occupancy 61488000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -66,6 +87,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -99,7 +141,7 @@ system.cpu.num_func_calls 12448615 # nu system.cpu.num_conditional_control_insts 18105896 # number of instructions that are conditional controls system.cpu.num_int_insts 279584917 # number of integer instructions system.cpu.num_fp_insts 114216705 # number of float instructions -system.cpu.num_int_register_reads 2212913168 # number of times the integer registers were read +system.cpu.num_int_register_reads 2579483474 # number of times the integer registers were read system.cpu.num_int_register_writes 251197902 # number of times the integer registers were written system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written |