diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
| commit | df8df4fd0a95763cb0658cbe77615e7deac391d3 (patch) | |
| tree | 0c8776db2ef482a4f6e5db099133105f9af799d7 /tests/long/se/30.eon/ref | |
| parent | b2342c5d9aea0b732f6d5a5b6c9c3961940ed8e7 (diff) | |
| download | gem5-df8df4fd0a95763cb0658cbe77615e7deac391d3.tar.xz | |
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
Diffstat (limited to 'tests/long/se/30.eon/ref')
6 files changed, 1808 insertions, 1664 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index ca5c08420..fd544a1a5 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.226819 # Nu sim_ticks 226818771000 # Number of ticks simulated final_tick 226818771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 285609 # Simulator instruction rate (inst/s) -host_op_rate 285609 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 162496290 # Simulator tick rate (ticks/s) -host_mem_usage 242892 # Number of bytes of host memory used -host_seconds 1395.84 # Real time elapsed on the host +host_inst_rate 333141 # Simulator instruction rate (inst/s) +host_op_rate 333141 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 189539219 # Simulator tick rate (ticks/s) +host_mem_usage 300760 # Number of bytes of host memory used +host_seconds 1196.69 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895 32 2.10% 84.83% # By system.physmem.bytesPerActivate::896-1023 40 2.63% 87.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 191 12.54% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1523 # Bytes accessed per row activation -system.physmem.totQLat 50615750 # Total ticks spent queuing -system.physmem.totMemAccLat 198234500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 50610250 # Total ticks spent queuing +system.physmem.totMemAccLat 198229000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6429.03 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6428.33 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25179.03 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25178.33 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.22 # Average system read bandwidth in MiByte/s @@ -218,36 +218,41 @@ system.physmem.readRowHitRate 80.54 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 28809690.02 # Average gap between requests system.physmem.pageHitRate 80.54 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 217525128250 # Time in different power states -system.physmem.memoryStateTime::REF 7573800000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1714919250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 6698160 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 4808160 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 3654750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2623500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 34164000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 26910000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 14814352800 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 14814352800 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 5823022815 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 5572463355 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 130980318750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 131200107750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 151662211275 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 151621265565 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.664178 # Core power per rank (mW) -system.physmem.averagePower::1 668.483652 # Core power per rank (mW) -system.cpu.branchPred.lookups 46273762 # Number of BP lookups +system.physmem_0.actEnergy 6698160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3654750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 34164000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 14814352800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5823127980 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 130980226500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 151662224190 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.664235 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 217898379000 # Time in different power states +system.physmem_0.memoryStateTime::REF 7573800000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1344256000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 4808160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2623500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 26910000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 14814352800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5572496700 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 131200078500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 151621269660 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.483670 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 218263346500 # Time in different power states +system.physmem_1.memoryStateTime::REF 7573800000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 976701000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 46273761 # Number of BP lookups system.cpu.branchPred.condPredicted 26730646 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1017469 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25595417 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 25595416 # Number of BTB lookups system.cpu.branchPred.BTBHits 21359944 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.452221 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 83.452224 # BTB Hit Percentage system.cpu.branchPred.usedRAS 8341649 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -293,15 +298,15 @@ system.cpu.discardedOps 4467797 # Nu system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.137893 # CPI: cycles per instruction system.cpu.ipc 0.878818 # IPC: instructions per cycle -system.cpu.tickCycles 450174331 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3463211 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 450174327 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3463215 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.955317 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3291.955330 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168028615 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 40343.004802 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.955317 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.955330 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.803700 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.803700 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id @@ -329,14 +334,14 @@ system.cpu.dcache.demand_misses::cpu.inst 7119 # n system.cpu.dcache.demand_misses::total 7119 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 7119 # number of overall misses system.cpu.dcache.overall_misses::total 7119 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 81052500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 81052500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 391543250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 391543250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 472595750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 472595750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 472595750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 472595750 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 81009750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 81009750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 391587500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 391587500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 472597250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 472597250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 472597250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 472597250 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 94515004 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94515004 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 73520730 # number of WriteReq accesses(hits+misses) @@ -353,14 +358,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.000042 system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68630.397968 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68630.397968 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65938.573594 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65938.573594 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66385.131339 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66385.131339 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66385.131339 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66385.131339 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68594.199831 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68594.199831 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65946.025598 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65946.025598 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66385.342042 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66385.342042 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66385.342042 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66385.342042 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -387,14 +392,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 4165 system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 64327500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 64327500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 214316000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 214316000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 278643500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 278643500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 278643500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 278643500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 64296000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 64296000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 214342750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 214342750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 278638750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 278638750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 278638750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 278638750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for WriteReq accesses @@ -403,22 +408,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66317.010309 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66317.010309 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67078.560250 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67078.560250 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66901.200480 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66901.200480 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66901.200480 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66901.200480 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66284.536082 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66284.536082 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67086.932707 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67086.932707 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66900.060024 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66900.060024 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66900.060024 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66900.060024 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3196 # number of replacements -system.cpu.icache.tags.tagsinuse 1918.781810 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1918.781818 # Cycle average of tags in use system.cpu.icache.tags.total_refs 98776054 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 5174 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 19090.849246 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1918.781810 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1918.781818 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.936905 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.936905 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id @@ -441,12 +446,12 @@ system.cpu.icache.demand_misses::cpu.inst 5174 # n system.cpu.icache.demand_misses::total 5174 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5174 # number of overall misses system.cpu.icache.overall_misses::total 5174 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 293010500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 293010500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 293010500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 293010500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 293010500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 293010500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 293011250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 293011250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 293011250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 293011250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 293011250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 293011250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 98781228 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 98781228 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 98781228 # number of demand (read+write) accesses @@ -459,12 +464,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56631.329726 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56631.329726 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56631.329726 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56631.329726 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56631.329726 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56631.329726 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56631.474681 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56631.474681 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56631.474681 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56631.474681 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56631.474681 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56631.474681 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -479,33 +484,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 5174 system.cpu.icache.demand_mshr_misses::total 5174 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 5174 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 5174 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281053500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281053500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281053500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281053500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281053500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281053500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281053750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 281053750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281053750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 281053750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281053750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 281053750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54320.351759 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54320.351759 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54320.351759 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54320.351759 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54320.351759 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54320.351759 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54320.400077 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54320.400077 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54320.400077 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54320.400077 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54320.400077 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54320.400077 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4426.924710 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4426.924727 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1494 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5273 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.283330 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 373.138333 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4053.786377 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 373.138335 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4053.786392 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011387 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123712 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.135099 # Average percentage of cache occupancy @@ -535,14 +540,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 7873 # system.cpu.l2cache.demand_misses::total 7873 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 7873 # number of overall misses system.cpu.l2cache.overall_misses::total 7873 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 324986750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 324986750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 210671750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 210671750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 535658500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 535658500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 535658500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 535658500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 324955500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 324955500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 210698500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 210698500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 535654000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 535654000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 535654000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 535654000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 6141 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 6141 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 654 # number of Writeback accesses(hits+misses) @@ -561,14 +566,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.843024 system.cpu.l2cache.demand_miss_rate::total 0.843024 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.843024 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.843024 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68620.513091 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68620.513091 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67157.076825 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67157.076825 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68037.406325 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68037.406325 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68037.406325 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68037.406325 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68613.914696 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68613.914696 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67165.604080 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67165.604080 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68036.834752 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68036.834752 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68036.834752 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68036.834752 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -585,14 +590,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 7873 system.cpu.l2cache.demand_mshr_misses::total 7873 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 7873 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7873 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 265636250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 265636250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 170998250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 170998250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 436634500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 436634500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 436634500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 436634500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 265602000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 265602000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 171025500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 171025500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 436627500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 436627500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 436627500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 436627500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.771210 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771210 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.980926 # mshr miss rate for ReadExReq accesses @@ -601,14 +606,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.843024 system.cpu.l2cache.demand_mshr_miss_rate::total 0.843024 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.843024 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.843024 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56088.735220 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56088.735220 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54510.121135 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54510.121135 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55459.735806 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55459.735806 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55459.735806 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55459.735806 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56081.503378 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56081.503378 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54518.807778 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54518.807778 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55458.846691 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55458.846691 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55458.846691 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55458.846691 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 6141 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 6141 # Transaction distribution @@ -635,9 +640,9 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 9993 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 5650500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8565500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 8565750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6972500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6972750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.trans_dist::ReadReq 4736 # Transaction distribution system.membus.trans_dist::ReadResp 4736 # Transaction distribution @@ -660,7 +665,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 7873 # Request fanout histogram system.membus.reqLayer0.occupancy 9387500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 73875500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 73877500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 52c9c0408..90aeffe97 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.069652 # Nu sim_ticks 69651704000 # Number of ticks simulated final_tick 69651704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 274902 # Simulator instruction rate (inst/s) -host_op_rate 274902 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50981523 # Simulator tick rate (ticks/s) -host_mem_usage 244336 # Number of bytes of host memory used -host_seconds 1366.21 # Real time elapsed on the host +host_inst_rate 253977 # Simulator instruction rate (inst/s) +host_op_rate 253977 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47101012 # Simulator tick rate (ticks/s) +host_mem_usage 302288 # Number of bytes of host memory used +host_seconds 1478.77 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1956 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 918 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4228 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 915 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 293 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 63 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see @@ -188,24 +188,24 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 1353 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 350.509978 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 208.823320 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 348.868335 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 424 31.34% 31.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 330 24.39% 55.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 151 11.16% 66.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 84 6.21% 73.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 54 3.99% 77.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 42 3.10% 80.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 39 2.88% 83.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 208.904608 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 348.764111 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 423 31.26% 31.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 330 24.39% 55.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 152 11.23% 66.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 83 6.13% 73.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 55 4.07% 77.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 43 3.18% 80.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 38 2.81% 83.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 25 1.85% 84.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 204 15.08% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1353 # Bytes accessed per row activation -system.physmem.totQLat 66704750 # Total ticks spent queuing -system.physmem.totMemAccLat 206542250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 67034750 # Total ticks spent queuing +system.physmem.totMemAccLat 206872250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37290000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8944.05 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8988.30 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27694.05 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27738.30 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.85 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.85 # Average system read bandwidth in MiByte/s @@ -222,82 +222,64 @@ system.physmem.readRowHitRate 81.74 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 9339181.35 # Average gap between requests system.physmem.pageHitRate 81.74 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 66207575500 # Time in different power states -system.physmem.memoryStateTime::REF 2325700000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1115004500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 5843880 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 4362120 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 3188625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2380125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 32385600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 25373400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 4549069200 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 4549069200 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 2090120175 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1977791130 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 39955521000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 40054055250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 46636128480 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 46613031225 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.594966 # Core power per rank (mW) -system.physmem.averagePower::1 669.263339 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 4328 # Transaction distribution -system.membus.trans_dist::ReadResp 4328 # Transaction distribution -system.membus.trans_dist::ReadExReq 3130 # Transaction distribution -system.membus.trans_dist::ReadExResp 3130 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14916 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14916 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 477312 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7458 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7458 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7458 # Request fanout histogram -system.membus.reqLayer0.occupancy 9424000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 69710500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 51167476 # Number of BP lookups +system.physmem_0.actEnergy 5843880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3188625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 32385600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4549069200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2090226195 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 39955428000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 46636141500 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.595153 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 66468117000 # Time in different power states +system.physmem_0.memoryStateTime::REF 2325700000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 855864000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 4362120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2380125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 25373400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 4549069200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1978191270 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 40053704250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 46613080365 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.264045 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 66630949750 # Time in different power states +system.physmem_1.memoryStateTime::REF 2325700000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 691630250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 51167471 # Number of BP lookups system.cpu.branchPred.condPredicted 29641015 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1213095 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25804997 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 25804996 # Number of BTB lookups system.cpu.branchPred.BTBHits 23600999 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 91.459026 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9351095 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 91.459030 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9351091 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 307 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 103696201 # DTB read hits +system.cpu.dtb.read_hits 103696202 # DTB read hits system.cpu.dtb.read_misses 91462 # DTB read misses system.cpu.dtb.read_acv 49407 # DTB read access violations -system.cpu.dtb.read_accesses 103787663 # DTB read accesses +system.cpu.dtb.read_accesses 103787664 # DTB read accesses system.cpu.dtb.write_hits 79414480 # DTB write hits system.cpu.dtb.write_misses 1579 # DTB write misses system.cpu.dtb.write_acv 2 # DTB write access violations system.cpu.dtb.write_accesses 79416059 # DTB write accesses -system.cpu.dtb.data_hits 183110681 # DTB hits +system.cpu.dtb.data_hits 183110682 # DTB hits system.cpu.dtb.data_misses 93041 # DTB misses system.cpu.dtb.data_acv 49409 # DTB access violations -system.cpu.dtb.data_accesses 183203722 # DTB accesses -system.cpu.itb.fetch_hits 51277823 # ITB hits +system.cpu.dtb.data_accesses 183203723 # DTB accesses +system.cpu.itb.fetch_hits 51277820 # ITB hits system.cpu.itb.fetch_misses 422 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 51278245 # ITB accesses +system.cpu.itb.fetch_accesses 51278242 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -314,57 +296,57 @@ system.cpu.workload.num_syscalls 215 # Nu system.cpu.numCycles 139303411 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 52063861 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 457094552 # Number of instructions fetch has processed -system.cpu.fetch.Branches 51167476 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 32952094 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 85692225 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 52063926 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 457094521 # Number of instructions fetch has processed +system.cpu.fetch.Branches 51167471 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 32952090 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 85692281 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 2532764 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb system.cpu.fetch.MiscStallCycles 174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 13783 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 51277823 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 545280 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 139036455 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.287588 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 51277820 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 545278 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 139036576 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.287585 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.344928 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 58307210 41.94% 41.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4519217 3.25% 45.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58307337 41.94% 41.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4519216 3.25% 45.19% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 7280822 5.24% 50.42% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 5545601 3.99% 54.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11970287 8.61% 63.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11970286 8.61% 63.02% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 8019991 5.77% 68.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5933035 4.27% 73.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5933032 4.27% 73.06% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 1884761 1.36% 74.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35575531 25.59% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35575530 25.59% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 139036455 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 139036576 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.367310 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.281288 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45112319 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16348091 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 71786999 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4526862 # Number of cycles decode is unblocking +system.cpu.fetch.rate 3.281287 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45112383 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16348146 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 71787003 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4526860 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1262184 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 9563244 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 4245 # Number of times decode detected a branch misprediction system.cpu.decode.DecodedInsts 451283163 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 14200 # Number of squashed instructions handled by decode +system.cpu.decode.SquashedInsts 14196 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 1262184 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 47010962 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5663544 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 518995 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 74309214 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10271556 # Number of cycles rename is unblocking +system.cpu.rename.IdleCycles 47011024 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5663526 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 519113 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 74309218 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 10271511 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 447721649 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 439815 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 2540100 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 2926498 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 3600572 # Number of times rename has blocked due to SQ full +system.cpu.rename.SQFullEvents 3600527 # Number of times rename has blocked due to SQ full system.cpu.rename.RenamedOperands 292278306 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 589607782 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 419965282 # Number of integer rename lookups @@ -373,35 +355,35 @@ system.cpu.rename.CommittedMaps 259532329 # Nu system.cpu.rename.UndoneMaps 32745977 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 37893 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 316 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 16173803 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 16173797 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 106306370 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 81667386 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 12470725 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 9729569 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 414594685 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 306 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 406915916 # Number of instructions issued +system.cpu.iq.iqInstsIssued 406915918 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 484036 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 38878487 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 18208108 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 18208107 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 91 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 139036455 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.926685 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.221928 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 139036576 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.926683 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.221929 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23891375 17.18% 17.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19616672 14.11% 31.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22677489 16.31% 47.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23891494 17.18% 17.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19616678 14.11% 31.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22677483 16.31% 47.60% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 18900240 13.59% 61.20% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 19609416 14.10% 75.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14153870 10.18% 85.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9626407 6.92% 92.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6209798 4.47% 96.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4351188 3.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14153871 10.18% 85.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9626410 6.92% 92.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6209797 4.47% 96.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4351187 3.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 139036455 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 139036576 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 258477 1.29% 1.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 1 0.00% 1.29% # attempts to use FU when none available @@ -437,7 +419,7 @@ system.cpu.iq.fu_full::MemWrite 4976149 24.90% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 153207489 37.65% 37.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 153207490 37.65% 37.66% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 2128182 0.52% 38.18% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.18% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 37392506 9.19% 47.37% # Type of FU issued @@ -466,21 +448,21 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.42% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.42% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.42% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 105367867 25.89% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 105367868 25.89% 80.32% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 80097727 19.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 406915916 # Type of FU issued +system.cpu.iq.FU_type_0::total 406915918 # Type of FU issued system.cpu.iq.rate 2.921076 # Inst issue rate system.cpu.iq.fu_busy_cnt 19986240 # FU busy when requested system.cpu.iq.fu_busy_rate 0.049116 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 625896924 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 625897049 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 265989715 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237228630 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 237228631 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 347441639 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 187559752 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 163339265 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 246150912 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 246150914 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 180717663 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 19936358 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -491,35 +473,35 @@ system.cpu.iew.lsq.thread0.squashedStores 8146657 # N system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 381699 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4486 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 4488 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 1262184 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 4471526 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 139226 # Number of cycles IEW is unblocking +system.cpu.iew.iewUnblockCycles 139208 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 439574480 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 145285 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 106306370 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 81667386 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 306 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 6690 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 131709 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 131691 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 76334 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 976027 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 412585 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 1388612 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 403157734 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 103837101 # Number of load instructions executed +system.cpu.iew.iewExecutedInsts 403157736 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 103837102 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 3758182 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 24979489 # number of nop insts executed -system.cpu.iew.exec_refs 183253197 # number of memory reference insts executed -system.cpu.iew.exec_branches 46959988 # Number of branches executed +system.cpu.iew.exec_refs 183253198 # number of memory reference insts executed +system.cpu.iew.exec_branches 46959989 # Number of branches executed system.cpu.iew.exec_stores 79416096 # Number of stores executed system.cpu.iew.exec_rate 2.894098 # Inst execution rate -system.cpu.iew.wb_sent 401401506 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 400567895 # cumulative count of insts written-back -system.cpu.iew.wb_producers 198000445 # num instructions producing a value -system.cpu.iew.wb_consumers 283955599 # num instructions consuming a value +system.cpu.iew.wb_sent 401401507 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 400567896 # cumulative count of insts written-back +system.cpu.iew.wb_producers 198000452 # num instructions producing a value +system.cpu.iew.wb_consumers 283955606 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.875507 # insts written-back per cycle system.cpu.iew.wb_fanout 0.697294 # average fanout of values written-back @@ -527,23 +509,23 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 40912072 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1208897 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 133310602 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.990494 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 133310723 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.990491 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 3.213946 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 48555591 36.42% 36.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18055922 13.54% 49.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 9630864 7.22% 57.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8737321 6.55% 63.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 48555712 36.42% 36.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18055923 13.54% 49.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 9630862 7.22% 57.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8737322 6.55% 63.75% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 6426217 4.82% 68.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4404757 3.30% 71.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4988495 3.74% 75.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2616133 1.96% 77.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29895302 22.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4404759 3.30% 71.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 4988493 3.74% 75.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2616131 1.96% 77.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29895304 22.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 133310602 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 133310723 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -589,60 +571,152 @@ system.cpu.commit.op_class_0::MemWrite 73520729 18.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 398664583 # Class of committed instruction -system.cpu.commit.bw_lim_events 29895302 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29895304 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 542988978 # The number of ROB reads +system.cpu.rob.rob_reads 542989097 # The number of ROB reads system.cpu.rob.rob_writes 884890973 # The number of ROB writes -system.cpu.timesIdled 3472 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 266956 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.timesIdled 3476 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 266835 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.cpi 0.370907 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.370907 # CPI: Total CPI of All Threads system.cpu.ipc 2.696092 # IPC: Instructions Per Cycle system.cpu.ipc_total 2.696092 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 403240144 # number of integer regfile reads -system.cpu.int_regfile_writes 171897287 # number of integer regfile writes +system.cpu.int_regfile_reads 403240146 # number of integer regfile reads +system.cpu.int_regfile_writes 171897288 # number of integer regfile writes system.cpu.fp_regfile_reads 157938395 # number of floating regfile reads system.cpu.fp_regfile_writes 105579710 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 5089 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5089 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 674 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3203 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3203 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8182 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9076 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 17258 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 573824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 8966 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 8966 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8966 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5157000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6787000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6700000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.dcache.tags.replacements 798 # number of replacements +system.cpu.dcache.tags.tagsinuse 3297.113166 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 156873476 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4201 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37341.936682 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3297.113166 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.804959 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.804959 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3403 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.830811 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 313794583 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 313794583 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 83372633 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 83372633 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73500836 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73500836 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 7 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 7 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 156873469 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 156873469 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 156873469 # number of overall hits +system.cpu.dcache.overall_hits::total 156873469 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1822 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1822 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19893 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19893 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21715 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21715 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21715 # number of overall misses +system.cpu.dcache.overall_misses::total 21715 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 114608500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 114608500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1125293584 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1125293584 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1239902084 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1239902084 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1239902084 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1239902084 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 83374455 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 83374455 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 7 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 7 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 156895184 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 156895184 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 156895184 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 156895184 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000271 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000271 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000138 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000138 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000138 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000138 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62902.579583 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62902.579583 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56567.314332 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56567.314332 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 57098.875616 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 57098.875616 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 57098.875616 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 57098.875616 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 46396 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 61 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 946 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.044397 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 61 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 674 # number of writebacks +system.cpu.dcache.writebacks::total 674 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 824 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 824 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16690 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16690 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17514 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17514 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17514 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17514 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 998 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 998 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3203 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3203 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4201 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4201 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4201 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4201 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67693000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 67693000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 235962750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 235962750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 303655750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 303655750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 303655750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 303655750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67828.657315 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67828.657315 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73669.294411 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73669.294411 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72281.778148 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72281.778148 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72281.778148 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72281.778148 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2164 # number of replacements -system.cpu.icache.tags.tagsinuse 1832.364308 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 51272145 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1832.364532 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 51272141 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4091 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12532.912491 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 12532.911513 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1832.364308 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1832.364532 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.894709 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.894709 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1927 # Occupied blocks per task id @@ -651,44 +725,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 167 system.cpu.icache.tags.age_task_id_blocks_1024::2 294 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1343 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.940918 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 102559737 # Number of tag accesses -system.cpu.icache.tags.data_accesses 102559737 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 51272145 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 51272145 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 51272145 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 51272145 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 51272145 # number of overall hits -system.cpu.icache.overall_hits::total 51272145 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5678 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5678 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5678 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5678 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5678 # number of overall misses -system.cpu.icache.overall_misses::total 5678 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 340036249 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 340036249 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 340036249 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 340036249 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 340036249 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 340036249 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 51277823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 51277823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 51277823 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 51277823 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 51277823 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 51277823 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 102559731 # Number of tag accesses +system.cpu.icache.tags.data_accesses 102559731 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 51272141 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 51272141 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 51272141 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 51272141 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 51272141 # number of overall hits +system.cpu.icache.overall_hits::total 51272141 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5679 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5679 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5679 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5679 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5679 # number of overall misses +system.cpu.icache.overall_misses::total 5679 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 341090499 # 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average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 59886.623635 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60061.718436 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 60061.718436 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 60061.718436 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 60061.718436 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 60061.718436 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 60061.718436 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 528 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked @@ -697,46 +771,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 58.666667 system.cpu.icache.avg_blocked_cycles::no_targets nan # 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Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4864 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.178043 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 371.133812 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2983.662944 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 666.835269 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 371.133834 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2983.663344 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 666.835334 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011326 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.091054 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.020350 # Average percentage of cache occupancy @@ -773,17 +847,17 @@ system.cpu.l2cache.demand_misses::total 7458 # nu system.cpu.l2cache.overall_misses::cpu.inst 3462 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3996 # number of overall misses system.cpu.l2cache.overall_misses::total 7458 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 239571000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 65252750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 304823750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 231908750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 231908750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 239571000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 297161500 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 537078500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 239866750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 297211750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 537078500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 4091 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 998 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 5089 # number of ReadReq accesses(hits+misses) @@ -808,17 +882,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.899421 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.846248 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.951202 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.899421 # 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average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69285.600809 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75383.371824 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70505.718577 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74098.961661 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74098.961661 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69285.600809 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74377.314815 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72013.743631 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69285.600809 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74377.314815 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72013.743631 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -838,17 +912,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7458 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3462 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3996 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7458 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 195687500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54580750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 250268250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 193330750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 193330750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195687500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 247911500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 443599000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195687500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 247911500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 443599000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 195982250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54610500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 250592750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 193350250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 193350250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195982250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 247960750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 443943000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195982250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 247960750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 443943000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867735 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.850462 # mshr miss rate for ReadReq accesses @@ -860,138 +934,69 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899421 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.951202 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899421 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56524.407857 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63026.270208 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57825.381238 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61767.012780 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61767.012780 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56524.407857 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62039.914915 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59479.619201 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56524.407857 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62039.914915 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59479.619201 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56609.546505 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63060.623557 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57900.358133 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61773.242812 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61773.242812 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56609.546505 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62052.239740 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59525.744167 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56609.546505 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62052.239740 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59525.744167 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 798 # number of replacements -system.cpu.dcache.tags.tagsinuse 3297.113011 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 156873476 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4201 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37341.936682 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3297.113011 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.804959 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.804959 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3403 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.830811 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 313794583 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 313794583 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 83372633 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 83372633 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73500836 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73500836 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 7 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 7 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 156873469 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 156873469 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 156873469 # number of overall hits -system.cpu.dcache.overall_hits::total 156873469 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1822 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1822 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19893 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19893 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21715 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21715 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21715 # number of overall misses -system.cpu.dcache.overall_misses::total 21715 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 114579750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 114579750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1125182835 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1125182835 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1239762585 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1239762585 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1239762585 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1239762585 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 83374455 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 83374455 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 156895184 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 156895184 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 156895184 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 156895184 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000271 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000271 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000138 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000138 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000138 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000138 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62886.800220 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62886.800220 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56561.747097 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56561.747097 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 57092.451531 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 57092.451531 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 57092.451531 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 57092.451531 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 46428 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 61 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 947 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.026399 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 61 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 674 # number of writebacks -system.cpu.dcache.writebacks::total 674 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 824 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 824 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16690 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16690 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17514 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17514 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17514 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17514 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 998 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 998 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3203 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3203 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4201 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4201 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4201 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4201 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67663750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 67663750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 235941750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 235941750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 303605500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 303605500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 303605500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 303605500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67799.348697 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67799.348697 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73662.738058 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73662.738058 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72269.816710 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72269.816710 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72269.816710 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72269.816710 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 5089 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5089 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 674 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3203 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3203 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8182 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9076 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 17258 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 573824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 8966 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 8966 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 8966 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5157000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 6787250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 6700250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 4328 # Transaction distribution +system.membus.trans_dist::ReadResp 4328 # Transaction distribution +system.membus.trans_dist::ReadExReq 3130 # Transaction distribution +system.membus.trans_dist::ReadExResp 3130 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14916 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14916 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 477312 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7458 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 7458 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 7458 # Request fanout histogram +system.membus.reqLayer0.occupancy 9422500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 69712000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index a544f3c3c..d0b9d8c3b 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.216828 # Nu sim_ticks 216828260500 # Number of ticks simulated final_tick 216828260500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 172164 # Simulator instruction rate (inst/s) -host_op_rate 206702 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 136721287 # Simulator tick rate (ticks/s) -host_mem_usage 262128 # Number of bytes of host memory used -host_seconds 1585.91 # Real time elapsed on the host +host_inst_rate 175239 # Simulator instruction rate (inst/s) +host_op_rate 210394 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 139163086 # Simulator tick rate (ticks/s) +host_mem_usage 320864 # Number of bytes of host memory used +host_seconds 1558.09 # Real time elapsed on the host sim_insts 273037856 # Number of instructions simulated sim_ops 327812213 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -184,24 +184,24 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 1505 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 321.360797 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 189.317321 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.826076 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 548 36.41% 36.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 349 23.19% 59.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 163 10.83% 70.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.304771 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 333.736324 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 549 36.48% 36.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 346 22.99% 59.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 165 10.96% 70.43% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 68 4.52% 74.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 69 4.58% 79.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 60 3.99% 83.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 33 2.19% 85.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 70 4.65% 79.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 58 3.85% 83.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 34 2.26% 85.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 33 2.19% 87.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 182 12.09% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1505 # Bytes accessed per row activation -system.physmem.totQLat 50683250 # Total ticks spent queuing -system.physmem.totMemAccLat 192902000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 50845500 # Total ticks spent queuing +system.physmem.totMemAccLat 193064250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37925000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6682.04 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6703.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25432.04 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25453.43 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.24 # Average system read bandwidth in MiByte/s @@ -218,29 +218,34 @@ system.physmem.readRowHitRate 80.07 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 28586424.65 # Average gap between requests system.physmem.pageHitRate 80.07 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 207228229000 # Time in different power states -system.physmem.memoryStateTime::REF 7240220000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 2356912000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 5012280 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 6342840 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 2734875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 3460875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 29905200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 29000400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 14161870320 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 14161870320 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 5651949285 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 5745162240 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 125136528000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 125054762250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 144987999960 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 145000598925 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.689925 # Core power per rank (mW) -system.physmem.averagePower::1 668.748031 # Core power per rank (mW) +system.physmem_0.actEnergy 5012280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2734875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 14161870320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5652564030 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 125135988750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 144988075455 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.690273 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 208174326250 # Time in different power states +system.physmem_0.memoryStateTime::REF 7240220000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1410814750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 6342840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3460875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 29000400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 14161870320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5745534165 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 125054436000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 145000644600 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.748242 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 208036674250 # Time in different power states +system.physmem_1.memoryStateTime::REF 7240220000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1549163250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 33221230 # Number of BP lookups system.cpu.branchPred.condPredicted 17174007 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1583983 # Number of conditional branches incorrect @@ -251,6 +256,14 @@ system.cpu.branchPred.BTBHitPct 87.059638 # BT system.cpu.branchPred.usedRAS 6611215 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -272,6 +285,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -293,6 +314,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -314,6 +343,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -345,15 +382,15 @@ system.cpu.discardedOps 4064410 # Nu system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.588265 # CPI: cycles per instruction system.cpu.ipc 0.629618 # IPC: instructions per cycle -system.cpu.tickCycles 430211091 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3445430 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 430211127 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3445394 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 1354 # number of replacements -system.cpu.dcache.tags.tagsinuse 3086.009332 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3086.009488 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168783807 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37416.051208 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 3086.009332 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 3086.009488 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.753420 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.753420 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id @@ -385,14 +422,14 @@ system.cpu.dcache.demand_misses::cpu.inst 7290 # n system.cpu.dcache.demand_misses::total 7290 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 7290 # number of overall misses system.cpu.dcache.overall_misses::total 7290 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 126122956 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 126122956 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 360338500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 360338500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 486461456 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 486461456 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 486461456 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 486461456 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 126489706 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 126489706 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 360451750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 360451750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 486941456 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 486941456 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 486941456 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 486941456 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 86716630 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 86716630 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses) @@ -413,14 +450,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61135.703345 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61135.703345 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68937.918500 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 68937.918500 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66729.966529 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66729.966529 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66729.966529 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66729.966529 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61313.478429 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61313.478429 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68959.584848 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 68959.584848 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66795.810151 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66795.810151 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66795.810151 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66795.810151 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -447,14 +484,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 4511 system.cpu.dcache.demand_mshr_misses::total 4511 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 4511 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 99847542 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 99847542 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197786250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 197786250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297633792 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 297633792 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297633792 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 297633792 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100259792 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 100259792 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197855250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 197855250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 298115042 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 298115042 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 298115042 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 298115042 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses @@ -463,22 +500,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60845.546618 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60845.546618 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68915.069686 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68915.069686 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 65979.559299 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65979.559299 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 65979.559299 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65979.559299 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61096.765387 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61096.765387 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68939.111498 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68939.111498 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66086.242962 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66086.242962 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66086.242962 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66086.242962 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 36927 # number of replacements -system.cpu.icache.tags.tagsinuse 1924.993605 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 73270396 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1924.993634 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 73270394 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 38864 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1885.302491 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1885.302439 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1924.993605 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.993634 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.939938 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.939938 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id @@ -488,44 +525,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 34 system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1487 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146657386 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146657386 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 73270396 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 73270396 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 73270396 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 73270396 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 73270396 # number of overall hits -system.cpu.icache.overall_hits::total 73270396 # number of overall hits +system.cpu.icache.tags.tag_accesses 146657382 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146657382 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 73270394 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 73270394 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 73270394 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 73270394 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 73270394 # number of overall hits +system.cpu.icache.overall_hits::total 73270394 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 38865 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 38865 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 38865 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 38865 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 38865 # number of overall misses system.cpu.icache.overall_misses::total 38865 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 703294747 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 703294747 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 703294747 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 703294747 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 703294747 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 703294747 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 73309261 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 73309261 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 73309261 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 73309261 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 73309261 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 73309261 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 703218247 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 703218247 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 703218247 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 703218247 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 703218247 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 703218247 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 73309259 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 73309259 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 73309259 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 73309259 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 73309259 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 73309259 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000530 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000530 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000530 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000530 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000530 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000530 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18095.838081 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18095.838081 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18095.838081 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18095.838081 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18095.838081 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18095.838081 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18093.869729 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18093.869729 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18093.869729 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18093.869729 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18093.869729 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18093.869729 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -540,33 +577,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 38865 system.cpu.icache.demand_mshr_misses::total 38865 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 38865 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 38865 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 624165253 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 624165253 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 624165253 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 624165253 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 624165253 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 624165253 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 624088753 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 624088753 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 624088753 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 624088753 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 624088753 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 624088753 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000530 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000530 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000530 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16059.828972 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16059.828972 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16059.828972 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16059.828972 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16059.828972 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16059.828972 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16057.860620 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16057.860620 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16057.860620 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16057.860620 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16057.860620 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16057.860620 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4198.559652 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4198.559801 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 35809 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5647 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 6.341243 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 353.760812 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.798840 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 353.760842 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.798959 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010796 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117334 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.128130 # Average percentage of cache occupancy @@ -597,14 +634,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 7630 # system.cpu.l2cache.demand_misses::total 7630 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 7630 # number of overall misses system.cpu.l2cache.overall_misses::total 7630 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 326194750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 326194750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194720750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 194720750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 520915500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 520915500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 520915500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 520915500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 326530500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 326530500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194789750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 194789750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 521320250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 521320250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 521320250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 521320250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 40506 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 40506 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 1010 # number of Writeback accesses(hits+misses) @@ -623,14 +660,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.175904 system.cpu.l2cache.demand_miss_rate::total 0.175904 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.175904 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.175904 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68298.733250 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68298.733250 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68227.312544 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68227.312544 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68272.018349 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68272.018349 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68272.018349 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68272.018349 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68369.032663 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68369.032663 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68251.489138 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68251.489138 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68325.065531 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68325.065531 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68325.065531 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68325.065531 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -653,14 +690,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 7585 system.cpu.l2cache.demand_mshr_misses::total 7585 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 7585 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7585 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 264387500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 264387500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158755250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158755250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 423142750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 423142750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 423142750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 423142750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 264479250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 264479250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158825750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158825750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 423305000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 423305000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 423305000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 423305000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.116798 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116798 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994425 # mshr miss rate for ReadExReq accesses @@ -669,14 +706,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174866 system.cpu.l2cache.demand_mshr_miss_rate::total 0.174866 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174866 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.174866 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55884.062566 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55884.062566 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55625.525578 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55625.525578 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55786.783125 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55786.783125 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55786.783125 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55786.783125 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55903.455929 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55903.455929 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55650.227751 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55650.227751 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55808.174028 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55808.174028 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55808.174028 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55808.174028 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 40506 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 40505 # Transaction distribution @@ -709,7 +746,7 @@ system.cpu.toL2Bus.reqLayer0.occupancy 23203000 # La system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 58996747 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7500208 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7500458 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.trans_dist::ReadReq 4731 # Transaction distribution system.membus.trans_dist::ReadResp 4731 # Transaction distribution @@ -730,9 +767,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7585 # Request fanout histogram -system.membus.reqLayer0.occupancy 8963500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8964000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 71030250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 71030500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 784b1e77a..2e0077bb1 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.112541 # Number of seconds simulated -sim_ticks 112540655000 # Number of ticks simulated -final_tick 112540655000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.112624 # Number of seconds simulated +sim_ticks 112623767500 # Number of ticks simulated +final_tick 112623767500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 132153 # Simulator instruction rate (inst/s) -host_op_rate 158665 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54470958 # Simulator tick rate (ticks/s) -host_mem_usage 270904 # Number of bytes of host memory used -host_seconds 2066.07 # Real time elapsed on the host +host_inst_rate 123996 # Simulator instruction rate (inst/s) +host_op_rate 148871 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51146556 # Simulator tick rate (ticks/s) +host_mem_usage 325020 # Number of bytes of host memory used +host_seconds 2201.98 # Real time elapsed on the host sim_insts 273037219 # Number of instructions simulated sim_ops 327811601 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 30592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 80768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 512320 # Number of bytes read from this memory -system.physmem.bytes_read::total 623680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 30592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 30592 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 478 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1262 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 8005 # Number of read requests responded to by this memory -system.physmem.num_reads::total 9745 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 271831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 717678 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 4552310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5541820 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 271831 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 271831 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 271831 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 717678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 4552310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5541820 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 9745 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 187072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 169856 # Number of bytes read from this memory +system.physmem.bytes_read::total 469120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 187072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 187072 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2923 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2654 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7330 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1661035 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 996166 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1508172 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4165373 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1661035 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1661035 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1661035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 996166 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1508172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4165373 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7330 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 9745 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7330 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 623680 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 469120 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 623680 # Total read bytes from the system interface side +system.physmem.bytesReadSys 469120 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 803 # Per bank write bursts -system.physmem.perBankRdBursts::1 999 # Per bank write bursts -system.physmem.perBankRdBursts::2 769 # Per bank write bursts -system.physmem.perBankRdBursts::3 645 # Per bank write bursts -system.physmem.perBankRdBursts::4 618 # Per bank write bursts -system.physmem.perBankRdBursts::5 484 # Per bank write bursts -system.physmem.perBankRdBursts::6 251 # Per bank write bursts -system.physmem.perBankRdBursts::7 363 # Per bank write bursts -system.physmem.perBankRdBursts::8 300 # Per bank write bursts -system.physmem.perBankRdBursts::9 432 # Per bank write bursts -system.physmem.perBankRdBursts::10 486 # Per bank write bursts -system.physmem.perBankRdBursts::11 534 # Per bank write bursts -system.physmem.perBankRdBursts::12 696 # Per bank write bursts -system.physmem.perBankRdBursts::13 850 # Per bank write bursts -system.physmem.perBankRdBursts::14 782 # Per bank write bursts -system.physmem.perBankRdBursts::15 733 # Per bank write bursts +system.physmem.perBankRdBursts::0 589 # Per bank write bursts +system.physmem.perBankRdBursts::1 789 # Per bank write bursts +system.physmem.perBankRdBursts::2 601 # Per bank write bursts +system.physmem.perBankRdBursts::3 519 # Per bank write bursts +system.physmem.perBankRdBursts::4 444 # Per bank write bursts +system.physmem.perBankRdBursts::5 346 # Per bank write bursts +system.physmem.perBankRdBursts::6 153 # Per bank write bursts +system.physmem.perBankRdBursts::7 257 # Per bank write bursts +system.physmem.perBankRdBursts::8 219 # Per bank write bursts +system.physmem.perBankRdBursts::9 291 # Per bank write bursts +system.physmem.perBankRdBursts::10 316 # Per bank write bursts +system.physmem.perBankRdBursts::11 411 # Per bank write bursts +system.physmem.perBankRdBursts::12 547 # Per bank write bursts +system.physmem.perBankRdBursts::13 678 # Per bank write bursts +system.physmem.perBankRdBursts::14 615 # Per bank write bursts +system.physmem.perBankRdBursts::15 555 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 112540488500 # Total gap between requests +system.physmem.totGap 112623613500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 9745 # Read request sizes (log2) +system.physmem.readPktSize::6 7330 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,22 +94,22 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2266 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1763 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 847 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 758 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 667 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 627 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 603 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 528 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 95 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 298 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 176 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -190,100 +190,88 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1235 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 501.635628 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 310.924046 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 394.932906 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 290 23.48% 23.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 197 15.95% 39.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 103 8.34% 47.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 73 5.91% 53.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 78 6.32% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 75 6.07% 66.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 32 2.59% 68.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 38 3.08% 71.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 349 28.26% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1235 # Bytes accessed per row activation -system.physmem.totQLat 248191131 # Total ticks spent queuing -system.physmem.totMemAccLat 430909881 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 48725000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25468.56 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1371 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 340.446389 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 197.878789 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 348.729899 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 488 35.59% 35.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 298 21.74% 57.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 137 9.99% 67.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 90 6.56% 73.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 49 3.57% 77.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 55 4.01% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 23 1.68% 83.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 26 1.90% 85.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 205 14.95% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1371 # Bytes accessed per row activation +system.physmem.totQLat 100359280 # Total ticks spent queuing +system.physmem.totMemAccLat 237796780 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36650000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13691.58 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44218.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 5.54 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32441.58 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.17 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 5.54 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.17 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.04 # Data bus utilization in percentage -system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.38 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 8500 # Number of row buffer hits during reads +system.physmem.readRowHits 5950 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.22 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.17 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 11548536.53 # Average gap between requests -system.physmem.pageHitRate 87.22 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 107209849499 # Time in different power states -system.physmem.memoryStateTime::REF 3757780000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1567991501 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 4460400 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 4845960 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 2433750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2644125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 38220000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 37221600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 7350217680 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 7350217680 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 3071428470 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 3094710975 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 64826723250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 64806300000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 75293483550 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 75295940340 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.067664 # Core power per rank (mW) -system.physmem.averagePower::1 669.089495 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 9170 # Transaction distribution -system.membus.trans_dist::ReadResp 9170 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 575 # Transaction distribution -system.membus.trans_dist::ReadExResp 575 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 19492 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 19492 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 623680 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 623680 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 9746 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 9746 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 9746 # Request fanout histogram -system.membus.reqLayer0.occupancy 11064261 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 88934700 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 37763717 # Number of BP lookups -system.cpu.branchPred.condPredicted 20179624 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1746237 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18664531 # Number of BTB lookups -system.cpu.branchPred.BTBHits 17302092 # Number of BTB hits +system.physmem.avgGap 15364749.45 # Average gap between requests +system.physmem.pageHitRate 81.17 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4906440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2677125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 28688400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 7355811840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3232257390 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 64737034500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 75361375695 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.161673 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 107692958200 # Time in different power states +system.physmem_0.memoryStateTime::REF 3760640000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1167342300 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 5435640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2965875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 28165800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 7355811840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3291484950 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 64685080500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 75368944605 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.228880 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 107605030400 # Time in different power states +system.physmem_1.memoryStateTime::REF 3760640000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1254923350 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 37762202 # Number of BP lookups +system.cpu.branchPred.condPredicted 20178978 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1746186 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18669843 # Number of BTB lookups +system.cpu.branchPred.BTBHits 17301885 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.700384 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7228871 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.672900 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7228775 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3814 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -305,6 +293,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -326,6 +322,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -347,6 +351,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -369,96 +381,95 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 225081311 # number of cpu cycles simulated +system.cpu.numCycles 225247536 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12228964 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 334152318 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37763717 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24530963 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 210956137 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3511517 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 130 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 514 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 89111612 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 21313 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 224941514 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.801835 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.228393 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12260997 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 334142837 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37762202 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24530660 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 210950106 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3511423 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1112 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 2317 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 89109626 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 21670 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 224970243 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.801560 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.228501 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 51202945 22.76% 22.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42808370 19.03% 41.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 30291484 13.47% 55.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 100638715 44.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 51235855 22.77% 22.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42807602 19.03% 41.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 30290628 13.46% 55.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 100636158 44.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 224941514 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.167778 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.484585 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 27726149 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64007988 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108311612 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 23274772 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1620993 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6880386 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 135232 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 363491063 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 6273375 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1620993 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 45185790 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13191872 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 337791 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 113472399 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51132669 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 355733781 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 2913620 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 6683703 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 151097 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7653475 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 21162184 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 7934136 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 403386511 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2533827094 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 350198229 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 194873795 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 224970243 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.167648 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.483447 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 27756041 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64007493 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108311444 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 23274289 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1620976 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6880269 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 135184 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 363488172 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6272061 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1620976 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 45214868 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13194135 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 339970 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 113472539 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 51127755 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 355731319 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 2913591 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 6682784 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 150888 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7653578 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 21157029 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 7934488 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 403383639 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2533813915 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 350195205 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 194873173 # Number of floating rename lookups system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31156460 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 17017 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 17054 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 55398119 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 92429190 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 88465233 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1673754 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1845335 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 353207304 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28026 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 346267862 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 2344729 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24807728 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 73571108 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 5906 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 224941514 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.539368 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.101787 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 31153588 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 17016 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 17052 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 55396743 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 92428788 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 88464605 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1673696 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1845347 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 353205084 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 28025 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 346266425 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 2344670 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24805703 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 73566871 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 5905 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 224970243 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.539165 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.101848 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 40716883 18.10% 18.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 78348178 34.83% 52.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 60751241 27.01% 79.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34738398 15.44% 95.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9740749 4.33% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 637378 0.28% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8687 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 40745402 18.11% 18.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 78348887 34.83% 52.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 60751762 27.00% 79.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34737500 15.44% 95.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9740629 4.33% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 637380 0.28% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8683 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 224941514 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 224970243 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9315738 7.51% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7336 0.01% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9315798 7.51% 7.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7337 0.01% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.52% # attempts to use FU when none available @@ -477,22 +488,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.52% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 233465 0.19% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 233455 0.19% 7.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 152519 0.12% 7.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 103426 0.08% 7.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 152510 0.12% 7.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 103371 0.08% 7.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 37180 0.03% 7.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 820096 0.66% 8.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 318386 0.26% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 687826 0.55% 9.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 820015 0.66% 8.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 318375 0.26% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 687813 0.55% 9.41% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 53407084 43.05% 52.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 58973857 47.54% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 53407928 43.05% 52.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 58972553 47.54% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 110648843 31.95% 31.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148167 0.62% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 110648263 31.95% 31.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148166 0.62% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.58% # Type of FU issued @@ -511,93 +522,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.58% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6796997 1.96% 34.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6796965 1.96% 34.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8667397 2.50% 37.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3331873 0.96% 38.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1592437 0.46% 38.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20937214 6.05% 44.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7180794 2.07% 46.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147102 2.06% 48.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8667386 2.50% 37.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3331882 0.96% 38.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592439 0.46% 38.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20937021 6.05% 44.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7180792 2.07% 46.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147105 2.06% 48.65% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 91783348 26.51% 75.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 85858404 24.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 91783076 26.51% 75.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 85858044 24.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 346267862 # Type of FU issued -system.cpu.iq.rate 1.538412 # Inst issue rate -system.cpu.iq.fu_busy_cnt 124056913 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.358269 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 756613481 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 251259921 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 223227498 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 287265399 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 126793827 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 117417697 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 302953956 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 167370819 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5034316 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 346266425 # Type of FU issued +system.cpu.iq.rate 1.537271 # Inst issue rate +system.cpu.iq.fu_busy_cnt 124056335 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.358268 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 756639732 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 251256110 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 223226406 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 287264366 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 126793395 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 117417412 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 302952760 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 167370000 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5033832 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6696915 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13655 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 10694 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6089616 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6696513 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13646 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 10697 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6088988 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 151174 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 488913 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 151171 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 488903 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1620993 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2123091 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 319754 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 353236194 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 1620976 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2121777 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 321028 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 353233977 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 92429190 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 88465233 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 16993 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 8080 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 327488 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 10694 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1220289 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 438322 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1658611 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 342304940 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 90585369 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3962922 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 92428788 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 88464605 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 16992 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 8078 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 328775 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 10697 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1220281 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 438299 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1658580 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 342303629 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 90585110 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3962796 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 864 # number of nop insts executed -system.cpu.iew.exec_refs 175168098 # number of memory reference insts executed -system.cpu.iew.exec_branches 31752179 # Number of branches executed -system.cpu.iew.exec_stores 84582729 # Number of stores executed -system.cpu.iew.exec_rate 1.520806 # Inst execution rate -system.cpu.iew.wb_sent 340904975 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 340645195 # cumulative count of insts written-back -system.cpu.iew.wb_producers 153543382 # num instructions producing a value -system.cpu.iew.wb_consumers 265817565 # num instructions consuming a value +system.cpu.iew.exec_nop 868 # number of nop insts executed +system.cpu.iew.exec_refs 175167602 # number of memory reference insts executed +system.cpu.iew.exec_branches 31752029 # Number of branches executed +system.cpu.iew.exec_stores 84582492 # Number of stores executed +system.cpu.iew.exec_rate 1.519678 # Inst execution rate +system.cpu.iew.wb_sent 340903564 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 340643818 # cumulative count of insts written-back +system.cpu.iew.wb_producers 153542130 # num instructions producing a value +system.cpu.iew.wb_consumers 265815285 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.513432 # insts written-back per cycle +system.cpu.iew.wb_rate 1.512309 # insts written-back per cycle system.cpu.iew.wb_fanout 0.577627 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23000910 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 22999072 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1611472 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 221213350 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.481883 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.053410 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1611451 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 221242338 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.481688 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.053337 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 87832177 39.70% 39.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 69867778 31.58% 71.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 20927331 9.46% 80.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13474141 6.09% 86.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8800060 3.98% 90.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4584952 2.07% 92.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2913270 1.32% 94.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2446398 1.11% 95.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10367243 4.69% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 87860442 39.71% 39.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 69868164 31.58% 71.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 20927833 9.46% 80.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13474111 6.09% 86.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8800250 3.98% 90.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4584845 2.07% 92.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2913190 1.32% 94.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2446339 1.11% 95.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10367164 4.69% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 221213350 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 221242338 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037831 # Number of instructions committed system.cpu.commit.committedOps 327812213 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -643,489 +654,155 @@ system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 327812213 # Class of committed instruction -system.cpu.commit.bw_lim_events 10367243 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 10367164 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 561656707 # The number of ROB reads -system.cpu.rob.rob_writes 705358339 # The number of ROB writes -system.cpu.timesIdled 49342 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 139797 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 561683936 # The number of ROB reads +system.cpu.rob.rob_writes 705354391 # The number of ROB writes +system.cpu.timesIdled 50923 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 277293 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273037219 # Number of Instructions Simulated system.cpu.committedOps 327811601 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.824361 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.824361 # CPI: Total CPI of All Threads -system.cpu.ipc 1.213060 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.213060 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 331187240 # number of integer regfile reads -system.cpu.int_regfile_writes 136909181 # number of integer regfile writes -system.cpu.fp_regfile_reads 187100304 # number of floating regfile reads -system.cpu.fp_regfile_writes 132166714 # number of floating regfile writes -system.cpu.cc_regfile_reads 1296661589 # number of cc regfile reads -system.cpu.cc_regfile_writes 80246596 # number of cc regfile writes -system.cpu.misc_regfile_reads 1182269483 # number of misc regfile reads +system.cpu.cpi 0.824970 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.824970 # CPI: Total CPI of All Threads +system.cpu.ipc 1.212165 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.212165 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 331186150 # number of integer regfile reads +system.cpu.int_regfile_writes 136908474 # number of integer regfile writes +system.cpu.fp_regfile_reads 187099872 # number of floating regfile reads +system.cpu.fp_regfile_writes 132166295 # number of floating regfile writes +system.cpu.cc_regfile_reads 1296656595 # number of cc regfile reads +system.cpu.cc_regfile_writes 80246016 # number of cc regfile writes +system.cpu.misc_regfile_reads 1182266137 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 2029653 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2029653 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 966282 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 49309 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 220486 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 220486 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1430858 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4034802 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5465660 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45758528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160034560 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205793088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 50213 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3265775 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.015099 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.121946 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3216466 98.49% 98.49% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 49309 1.51% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3265775 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2574531466 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1074172389 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2301537734 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 715368 # number of replacements -system.cpu.icache.tags.tagsinuse 511.871967 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 88391816 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 715880 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 123.472951 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 275609500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.871967 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999750 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999750 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 66 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 178939093 # Number of tag accesses -system.cpu.icache.tags.data_accesses 178939093 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 88391816 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 88391816 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 88391816 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 88391816 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 88391816 # number of overall hits -system.cpu.icache.overall_hits::total 88391816 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 719790 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 719790 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 719790 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 719790 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 719790 # number of overall misses -system.cpu.icache.overall_misses::total 719790 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 5791847611 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 5791847611 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 5791847611 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 5791847611 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 5791847611 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 5791847611 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 89111606 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 89111606 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 89111606 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 89111606 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 89111606 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 89111606 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008077 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008077 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008077 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008077 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008077 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008077 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8046.579712 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8046.579712 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8046.579712 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8046.579712 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8046.579712 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8046.579712 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 12631 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 17 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1514 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 8.342801 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 17 # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3909 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3909 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3909 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3909 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3909 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3909 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 715881 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 715881 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 715881 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 715881 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 715881 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 715881 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 4688303087 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 4688303087 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 4688303087 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 4688303087 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 4688303087 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 4688303087 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008034 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.008034 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.008034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6548.997790 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6548.997790 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6548.997790 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 6548.997790 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6548.997790 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 6548.997790 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 6641923 # number of hwpf identified -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 7386 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6574564 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 13578 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2097 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 44298 # number of hwpf issued -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 135685 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 8320.579960 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2794148 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 9718 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 287.522947 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2574.248018 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 441.129211 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 367.415546 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 4937.787185 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.157120 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.026924 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.022425 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.301379 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.507848 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 5676 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 4042 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 59 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 84 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 572 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4961 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 626 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 123 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3234 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.346436 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.246704 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 51678510 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 51678510 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 714431 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1313042 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2027473 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 966282 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 966282 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 219797 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 219797 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 714431 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1532839 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2247270 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 714431 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1532839 # number of overall hits -system.cpu.l2cache.overall_hits::total 2247270 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 546 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 730 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1276 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 689 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 689 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 546 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1419 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1965 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 546 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1419 # number of overall misses -system.cpu.l2cache.overall_misses::total 1965 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 38998499 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 50021748 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 89020247 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 15499 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 15499 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41954499 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 41954499 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 38998499 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 91976247 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 130974746 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 38998499 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 91976247 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 130974746 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 714977 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1313772 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2028749 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 966282 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 966282 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 220486 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 220486 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 714977 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1534258 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2249235 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 714977 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1534258 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2249235 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.000764 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000556 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000629 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003125 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.003125 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000764 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.000925 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.000874 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000764 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.000925 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.000874 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71425.822344 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68522.942466 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69765.083856 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15499 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15499 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60891.870827 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60891.870827 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71425.822344 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64817.651163 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66653.814758 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71425.822344 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64817.651163 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66653.814758 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 6173 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 209 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 29.535885 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 43 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 111 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 114 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 114 # number of ReadExReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 157 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 225 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 157 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 225 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 478 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 687 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1165 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 44298 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 44298 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 575 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 575 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 478 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1262 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1740 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 478 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1262 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 44298 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 46038 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32592250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42691498 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 75283748 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 669707182 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 669707182 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6001 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6001 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 34465750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 34465750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32592250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 77157248 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 109749498 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32592250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 77157248 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 669707182 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 779456680 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000669 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000523 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000574 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.002608 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.002608 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000669 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000823 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000774 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000669 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000823 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.020468 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68184.623431 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62141.918486 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64621.242918 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 15118.226150 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 15118.226150 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59940.434783 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59940.434783 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68184.623431 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61138.865293 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63074.424138 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68184.623431 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61138.865293 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 15118.226150 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 16930.724184 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1533746 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.875745 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 163803379 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1534258 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 106.763907 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 61007500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.875745 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999757 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1533739 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.852624 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 163803903 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1534251 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 106.764736 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 77087500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.852624 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999712 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999712 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336684382 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336684382 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 82726080 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 82726080 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80985064 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80985064 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 336684823 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336684823 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 82726313 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 82726313 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80985354 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80985354 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 70429 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 70429 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10910 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10910 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 163711144 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 163711144 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 163781573 # number of overall hits -system.cpu.dcache.overall_hits::total 163781573 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2704026 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2704026 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1067635 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1067635 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 163711667 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 163711667 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 163782096 # number of overall hits +system.cpu.dcache.overall_hits::total 163782096 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2704016 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2704016 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1067345 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1067345 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 19 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 19 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3771661 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3771661 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3771680 # number of overall misses -system.cpu.dcache.overall_misses::total 3771680 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 21403617484 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 21403617484 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8344449821 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8344449821 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 164500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 164500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29748067305 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29748067305 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29748067305 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29748067305 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 85430106 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 85430106 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3771361 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3771361 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3771380 # number of overall misses +system.cpu.dcache.overall_misses::total 3771380 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 21429430210 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 21429430210 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8382362067 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8382362067 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 174750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 174750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29811792277 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29811792277 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29811792277 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29811792277 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 85430329 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 85430329 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 70448 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 70448 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10915 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10915 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 167482805 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 167482805 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 167553253 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 167553253 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 167483028 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 167483028 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 167553476 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 167553476 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.031652 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.031652 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013012 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013012 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013008 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013008 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000270 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.000270 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.022520 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.022520 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.022510 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.022510 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7915.462900 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 7915.462900 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7815.826402 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7815.826402 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32900 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 32900 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 7887.259037 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 7887.259037 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 7887.219304 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 7887.219304 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 761243 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 111844 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 6.806293 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.022518 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.022518 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.022509 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.022509 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7925.038243 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 7925.038243 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7853.470122 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7853.470122 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 34950 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 34950 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 7904.783519 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 7904.783519 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 7904.743695 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 7904.743695 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 768686 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 111802 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 6.875423 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 966282 # number of writebacks -system.cpu.dcache.writebacks::total 966282 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1390265 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1390265 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 847147 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 847147 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 966281 # number of writebacks +system.cpu.dcache.writebacks::total 966281 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1390263 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1390263 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 846856 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 846856 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2237412 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2237412 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2237412 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2237412 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313761 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1313761 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220488 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 220488 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 2237119 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2237119 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2237119 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2237119 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313753 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1313753 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220489 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 220489 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1534249 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1534249 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1534260 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1534260 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9295842016 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9295842016 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1592020910 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1592020910 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 638250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 638250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10887862926 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10887862926 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10888501176 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10888501176 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1534242 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1534242 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1534253 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1534253 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9313835285 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9313835285 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1599508327 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1599508327 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 613250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 613250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10913343612 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10913343612 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10913956862 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10913956862 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015378 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015378 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002687 # mshr miss rate for WriteReq accesses @@ -1136,16 +813,372 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009161 system.cpu.dcache.demand_mshr_miss_rate::total 0.009161 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009157 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.009157 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7075.748189 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7075.748189 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7220.442428 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7220.442428 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58022.727273 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58022.727273 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7096.542299 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 7096.542299 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7096.907419 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 7096.907419 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7089.487358 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7089.487358 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7254.367914 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7254.367914 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 55750 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 55750 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7113.182674 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 7113.182674 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7113.531381 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 7113.531381 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 715275 # number of replacements +system.cpu.icache.tags.tagsinuse 511.840362 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 88389408 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 715787 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 123.485629 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 315060000 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 133 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 775 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5746 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.031433 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.414368 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 51674481 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 51674481 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 711950 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1312705 # 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number of ReadExReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 131 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 142 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 131 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 142 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2923 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1026 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3949 # number of ReadReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 30530 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 30530 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 727 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 727 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2923 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1753 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 4676 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2923 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1753 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 30530 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 35206 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 153898250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 59960500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 213858750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 204942291 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 204942291 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6001 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6001 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 41351500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 41351500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 153898250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101312000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 255210250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 153898250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101312000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 204942291 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 460152541 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004089 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000781 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001947 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003297 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003297 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004089 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001143 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.002079 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004089 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001143 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.015653 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52650.786863 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58441.033138 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54155.165865 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6712.816607 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 6712.816607 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56879.642366 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56879.642366 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52650.786863 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57793.496863 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54578.753208 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52650.786863 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57793.496863 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6712.816607 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13070.287479 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 2029552 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2029552 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 966281 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 32098 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 220487 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 220487 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1430672 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4034787 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5465459 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45752576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160034048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205786624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 33002 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3248420 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.009881 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.098911 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 3216322 99.01% 99.01% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 32098 0.99% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3248420 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2574443497 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1074521893 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2301598998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 6603 # Transaction distribution +system.membus.trans_dist::ReadResp 6603 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 727 # Transaction distribution +system.membus.trans_dist::ReadExResp 727 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14662 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14662 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 469120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 469120 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7331 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 7331 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 7331 # Request fanout histogram +system.membus.reqLayer0.occupancy 9338317 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 68128868 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index 607680a6d..8e74d72ee 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.201717 # Nu sim_ticks 201717313500 # Number of ticks simulated final_tick 201717313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1306299 # Simulator instruction rate (inst/s) -host_op_rate 1568357 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 965080142 # Simulator tick rate (ticks/s) -host_mem_usage 305108 # Number of bytes of host memory used -host_seconds 209.02 # Real time elapsed on the host +host_inst_rate 1117455 # Simulator instruction rate (inst/s) +host_op_rate 1341629 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 825564009 # Simulator tick rate (ticks/s) +host_mem_usage 308812 # Number of bytes of host memory used +host_seconds 244.34 # Real time elapsed on the host sim_insts 273037594 # Number of instructions simulated sim_ops 327811949 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,37 +35,15 @@ system.physmem.bw_write::total 1983209850 # Wr system.physmem.bw_total::cpu.inst 6913839312 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4366293422 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11280132734 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 434895827 # Transaction distribution -system.membus.trans_dist::ReadResp 434906722 # Transaction distribution -system.membus.trans_dist::WriteReq 82052672 # Transaction distribution -system.membus.trans_dist::WriteResp 82052672 # Transaction distribution -system.membus.trans_dist::SoftPFReq 54062 # Transaction distribution -system.membus.trans_dist::SoftPFResp 54062 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 10895 # Transaction distribution -system.membus.trans_dist::StoreCondReq 10895 # Transaction distribution -system.membus.trans_dist::StoreCondResp 10895 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 697320546 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336728156 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1034048702 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1394641092 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 2275398071 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 517024351 # Request fanout histogram -system.membus.snoop_fanout::mean 4.674359 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 168364078 32.56% 32.56% # Request fanout histogram -system.membus.snoop_fanout::5 348660273 67.44% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 517024351 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -87,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -108,6 +94,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -129,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -211,5 +213,35 @@ system.cpu.op_class::MemWrite 82375594 25.13% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812144 # Class of executed instruction +system.membus.trans_dist::ReadReq 434895827 # Transaction distribution +system.membus.trans_dist::ReadResp 434906722 # Transaction distribution +system.membus.trans_dist::WriteReq 82052672 # Transaction distribution +system.membus.trans_dist::WriteResp 82052672 # Transaction distribution +system.membus.trans_dist::SoftPFReq 54062 # Transaction distribution +system.membus.trans_dist::SoftPFResp 54062 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 10895 # Transaction distribution +system.membus.trans_dist::StoreCondReq 10895 # Transaction distribution +system.membus.trans_dist::StoreCondResp 10895 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 697320546 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336728156 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1034048702 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1394641092 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 2275398071 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 517024351 # Request fanout histogram +system.membus.snoop_fanout::mean 4.674359 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 168364078 32.56% 32.56% # Request fanout histogram +system.membus.snoop_fanout::5 348660273 67.44% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 517024351 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 09b69e575..c39fe9424 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.517235 # Nu sim_ticks 517235411000 # Number of ticks simulated final_tick 517235411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 795879 # Simulator instruction rate (inst/s) -host_op_rate 955482 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1509341441 # Simulator tick rate (ticks/s) -host_mem_usage 314596 # Number of bytes of host memory used -host_seconds 342.69 # Real time elapsed on the host +host_inst_rate 761441 # Simulator instruction rate (inst/s) +host_op_rate 914138 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1444030997 # Simulator tick rate (ticks/s) +host_mem_usage 318052 # Number of bytes of host memory used +host_seconds 358.19 # Real time elapsed on the host sim_insts 272739285 # Number of instructions simulated sim_ops 327433743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,30 +29,15 @@ system.physmem.bw_inst_read::total 322824 # In system.physmem.bw_total::cpu.inst 322824 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 522532 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 3976 # Transaction distribution -system.membus.trans_dist::ReadResp 3976 # Transaction distribution -system.membus.trans_dist::ReadExReq 2856 # Transaction distribution -system.membus.trans_dist::ReadExResp 2856 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 6833 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6833 # Request fanout histogram -system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -74,6 +59,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -95,6 +88,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -116,6 +117,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -198,6 +207,145 @@ system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812213 # Class of executed instruction +system.cpu.dcache.tags.replacements 1332 # number of replacements +system.cpu.dcache.tags.tagsinuse 3078.445016 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445016 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits +system.cpu.dcache.overall_hits::total 168337827 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses +system.cpu.dcache.overall_misses::total 4479 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 78354000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 78354000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 157425500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 157425500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 235779500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 235779500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 235779500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 235779500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52676.385165 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52641.102925 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 998 # number of writebacks +system.cpu.dcache.writebacks::total 998 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75108000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75108000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151681500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 151681500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 159000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 159000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226789500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 226789500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226948500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 226948500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13796 # number of replacements system.cpu.icache.tags.tagsinuse 1766.007645 # Cycle average of tags in use system.cpu.icache.tags.total_refs 348644749 # Total number of references to valid blocks. @@ -430,145 +578,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.916443 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1332 # number of replacements -system.cpu.dcache.tags.tagsinuse 3078.445016 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445016 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits -system.cpu.dcache.overall_hits::total 168337827 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses -system.cpu.dcache.overall_misses::total 4479 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 78354000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 78354000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 157425500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 157425500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 235779500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 235779500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 235779500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 235779500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52676.385165 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52641.102925 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 998 # number of writebacks -system.cpu.dcache.writebacks::total 998 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75108000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75108000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151681500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 151681500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 159000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 159000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226789500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 226789500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226948500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 226948500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution @@ -602,5 +611,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 23404500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 3976 # Transaction distribution +system.membus.trans_dist::ReadResp 3976 # Transaction distribution +system.membus.trans_dist::ReadExReq 2856 # Transaction distribution +system.membus.trans_dist::ReadExResp 2856 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 6833 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 6833 # Request fanout histogram +system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |