stats: update stats for previous changes.

3 files changed, 224 insertions, 220 deletions

diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
index aecbd5e16..cd1ce8718 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
 init_param=0
 kernel=
 load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
 memories=system.physmem
 num_work_ids=16
 readfile=
@@ -30,7 +31,7 @@ system_port=system.membus.slave[0]
 
 [system.cpu]
 type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
@@ -56,7 +57,6 @@ cpu_id=0
 decodeToFetchDelay=1
 decodeToRenameDelay=1
 decodeWidth=8
-defer_registration=false
 dispatchWidth=8
 do_checkpoint_insts=true
 do_quiesce=true
@@ -78,6 +78,7 @@ iewToFetchDelay=1
 iewToRenameDelay=1
 instShiftAmt=2
 interrupts=system.cpu.interrupts
+isa=system.cpu.isa
 issueToExecuteDelay=1
 issueWidth=8
 itb=system.cpu.itb
@@ -115,6 +116,7 @@ smtROBPolicy=Partitioned
 smtROBThreshold=100
 squashWidth=8
 store_set_clear_period=250000
+switched_out=false
 system=system
 tracer=system.cpu.tracer
 trapLatency=13
@@ -131,21 +133,16 @@ assoc=2
 block_size=64
 clock=500
 forward_snoops=true
-hash_delay=1
 hit_latency=2
 is_top_level=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
 prefetcher=Null
-prioritizeRequests=false
-repl=Null
 response_latency=2
 size=262144
-subblock_size=0
 system=system
 tgts_per_mshr=20
-trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
@@ -434,21 +431,16 @@ assoc=2
 block_size=64
 clock=500
 forward_snoops=true
-hash_delay=1
 hit_latency=2
 is_top_level=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
 prefetcher=Null
-prioritizeRequests=false
-repl=Null
 response_latency=2
 size=131072
-subblock_size=0
 system=system
 tgts_per_mshr=20
-trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
@@ -457,6 +449,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
 [system.cpu.interrupts]
 type=ArmInterrupts
 
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
 [system.cpu.itb]
 type=ArmTLB
 children=walker
@@ -477,21 +486,16 @@ assoc=8
 block_size=64
 clock=500
 forward_snoops=true
-hash_delay=1
 hit_latency=20
 is_top_level=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
 prefetcher=Null
-prioritizeRequests=false
-repl=Null
 response_latency=20
 size=2097152
-subblock_size=0
 system=system
 tgts_per_mshr=12
-trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
@@ -518,7 +522,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
+executable=/gem5/dist/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
index 4b90608f0..46ca25e4c 100755
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 30 2012 11:20:14
-gem5 started Oct 30 2012 19:45:28
-gem5 executing on u200540-lin
+gem5 compiled Jan  4 2013 21:17:24
+gem5 started Jan  5 2013 00:06:54
+gem5 executing on u200540
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
index 210b47f80..3611ed5dd 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.068267                       # Nu
 sim_ticks                                 68267465500                       # Number of ticks simulated
 final_tick                                68267465500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 160764                       # Simulator instruction rate (inst/s)
-host_op_rate                                   205527                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               40194170                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 285344                       # Number of bytes of host memory used
-host_seconds                                  1698.44                       # Real time elapsed on the host
+host_inst_rate                                  47859                       # Simulator instruction rate (inst/s)
+host_op_rate                                    61184                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               11965597                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 240720                       # Number of bytes of host memory used
+host_seconds                                  5705.31                       # Real time elapsed on the host
 sim_insts                                   273048375                       # Number of instructions simulated
 sim_ops                                     349076099                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            193920                       # Number of bytes read from this memory
@@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14                    0                       # Tr
 system.physmem.perBankWrReqs::15                    0                       # Track writes on a per bank basis
 system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
-system.physmem.totGap                     68267282000                       # Total gap between requests
+system.physmem.totGap                     68267283000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
@@ -184,7 +184,7 @@ system.physmem.readRowHits                       6392                       # Nu
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   87.60                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9355527.20                       # Average gap between requests
+system.physmem.avgGap                      9355527.34                       # Average gap between requests
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -239,23 +239,23 @@ system.cpu.BPredUnit.BTBHits                 16735646                       # Nu
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                  6736138                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                7270                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           38860071                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles           38860072                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.Insts                      317518566                       # Number of instructions fetch has processed
 system.cpu.fetch.Branches                    41739250                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches           23471784                       # Number of branches that fetch has predicted taken
 system.cpu.fetch.Cycles                      70794265                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu.fetch.SquashCycles                 6760095                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               21559516                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   34                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.BlockedCycles               21559517                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   33                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles          1854                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles           30                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  37487912                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                519564                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          136324280                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                  37487913                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                519565                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          136324281                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::mean              2.989165                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::stdev             3.456365                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 66156807     48.53%     48.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 66156808     48.53%     48.53% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::1                  6761816      4.96%     53.49% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::2                  5641032      4.14%     57.63% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::3                  6022575      4.42%     62.04% # Number of instructions fetched each cycle (Total)
@@ -267,11 +267,11 @@ system.cpu.fetch.rateDist::8                 35352444     25.93%    100.00% # Nu
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            136324280                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total            136324281                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.branchRate                  0.305704                       # Number of branch fetches per cycle
 system.cpu.fetch.rate                        2.325548                       # Number of inst fetches per cycle
 system.cpu.decode.IdleCycles                 45389084                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              16729555                       # Number of cycles decode is blocked
+system.cpu.decode.BlockedCycles              16729556                       # Number of cycles decode is blocked
 system.cpu.decode.RunCycles                  66615921                       # Number of cycles decode is running
 system.cpu.decode.UnblockCycles               2549925                       # Number of cycles decode is unblocking
 system.cpu.decode.SquashCycles                5039795                       # Number of cycles decode is squashing
@@ -283,19 +283,19 @@ system.cpu.rename.SquashCycles                5039795                       # Nu
 system.cpu.rename.IdleCycles                 50891753                       # Number of cycles rename is idle
 system.cpu.rename.BlockCycles                 1911896                       # Number of cycles rename is blocking
 system.cpu.rename.serializeStallCycles         347462                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  63595531                       # Number of cycles rename is running
+system.cpu.rename.RunCycles                  63595532                       # Number of cycles rename is running
 system.cpu.rename.UnblockCycles              14537843                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              393365757                       # Number of instructions processed by rename
+system.cpu.rename.RenamedInsts              393365758                       # Number of instructions processed by rename
 system.cpu.rename.ROBFullEvents                    50                       # Number of times rename has blocked due to ROB full
 system.cpu.rename.IQFullEvents                1668272                       # Number of times rename has blocked due to IQ full
 system.cpu.rename.LSQFullEvents              10291112                       # Number of times rename has blocked due to LSQ full
 system.cpu.rename.FullRegisterEvents             1086                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           431881386                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            2329985493                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1257436076                       # Number of integer rename lookups
+system.cpu.rename.RenamedOperands           431881387                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2329985497                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1257436080                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups        1072549417                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             384584833                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 47296553                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                 47296554                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts              14334                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts          14333                       # count of temporary serializing insts renamed
 system.cpu.rename.skidInsts                  36353497                       # count of insts added to the skid buffer
@@ -310,11 +310,11 @@ system.cpu.iq.iqSquashedInstsIssued           1224653                       # Nu
 system.cpu.iq.iqSquashedInstsExamined        34098402                       # Number of squashed instructions iterated over during squash; mainly for profiling
 system.cpu.iq.iqSquashedOperandsExamined     84823076                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved            961                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     136324280                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples     136324281                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::mean         2.743078                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::stdev        2.023492                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            24852306     18.23%     18.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            24852307     18.23%     18.23% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::1            19962410     14.64%     32.87% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::2            20554570     15.08%     47.95% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::3            18105177     13.28%     61.23% # Number of insts issued each cycle
@@ -326,7 +326,7 @@ system.cpu.iq.issued_per_cycle::8              911515      0.67%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       136324280                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       136324281                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntAlu                    8956      0.05%      0.05% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                   4688      0.03%      0.08% # attempts to use FU when none available
@@ -399,7 +399,7 @@ system.cpu.iq.FU_type_0::total              373948163                       # Ty
 system.cpu.iq.rate                           2.738846                       # Inst issue rate
 system.cpu.iq.fu_busy_cnt                    17797690                       # FU busy when requested
 system.cpu.iq.fu_busy_rate                   0.047594                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          653530496                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads          653530497                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_writes         287597541                       # Number of integer instruction queue writes
 system.cpu.iq.int_inst_queue_wakeup_accesses    249877083                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads           249712453                       # Number of floating instruction queue reads
@@ -422,7 +422,7 @@ system.cpu.iew.iewSquashCycles                5039795                       # Nu
 system.cpu.iew.iewBlockCycles                  281091                       # Number of cycles IEW is blocking
 system.cpu.iew.iewUnblockCycles                 41482                       # Number of cycles IEW is unblocking
 system.cpu.iew.iewDispatchedInsts           383923458                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            951525                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispSquashedInsts            951526                       # Number of squashed instructions skipped by dispatch
 system.cpu.iew.iewDispLoadInsts             103432229                       # Number of dispatched load instructions
 system.cpu.iew.iewDispStoreInsts             91356063                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts              14236                       # Number of dispatched non-speculative instructions
@@ -484,7 +484,7 @@ system.cpu.commit.bw_limited                        0                       # nu
 system.cpu.rob.rob_reads                    500559121                       # The number of ROB reads
 system.cpu.rob.rob_writes                   772890927                       # The number of ROB writes
 system.cpu.timesIdled                            6411                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          210652                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                          210651                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   273048375                       # Number of Instructions Simulated
 system.cpu.committedOps                     349076099                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             273048375                       # Number of Instructions Simulated
@@ -513,36 +513,36 @@ system.cpu.icache.demand_hits::cpu.inst      37470862                       # nu
 system.cpu.icache.demand_hits::total         37470862                       # number of demand (read+write) hits
 system.cpu.icache.overall_hits::cpu.inst     37470862                       # number of overall hits
 system.cpu.icache.overall_hits::total        37470862                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        17049                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         17049                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        17049                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          17049                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        17049                       # number of overall misses
-system.cpu.icache.overall_misses::total         17049                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    356549497                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    356549497                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    356549497                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    356549497                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    356549497                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    356549497                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     37487911                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     37487911                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     37487911                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     37487911                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     37487911                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     37487911                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_misses::cpu.inst        17050                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         17050                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        17050                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          17050                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        17050                       # number of overall misses
+system.cpu.icache.overall_misses::total         17050                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    356620497                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    356620497                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    356620497                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    356620497                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    356620497                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    356620497                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     37487912                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     37487912                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     37487912                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     37487912                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     37487912                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     37487912                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000455                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000455                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000455                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000455                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000455                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000455                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20913.220541                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 20913.220541                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 20913.220541                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 20913.220541                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 20913.220541                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 20913.220541                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20916.158182                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 20916.158182                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 20916.158182                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 20916.158182                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 20916.158182                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 20916.158182                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs          585                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                19                       # number of cycles access was blocked
@@ -551,12 +551,12 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs    30.789474
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1254                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1254                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1254                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1254                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1254                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1254                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1255                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1255                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1255                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1255                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1255                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1255                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15795                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total        15795                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst        15795                       # number of demand (read+write) MSHR misses
@@ -582,140 +582,14 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 18468.059323
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18468.059323                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 18468.059323                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                   1414                       # number of replacements
-system.cpu.dcache.tagsinuse               3122.405383                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                170873491                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                   4624                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs               36953.609645                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    3122.405383                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.762306                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.762306                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     88815229                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        88815229                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     82031562                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       82031562                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        13475                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        13475                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data        13225                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total        13225                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     170846791                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        170846791                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    170846791                       # number of overall hits
-system.cpu.dcache.overall_hits::total       170846791                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         4046                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          4046                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        21103                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        21103                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data        25149                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total          25149                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data        25149                       # number of overall misses
-system.cpu.dcache.overall_misses::total         25149                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    164690000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    164690000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    831954164                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    831954164                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       115000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       115000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    996644164                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    996644164                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    996644164                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    996644164                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     88819275                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     88819275                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     82052665                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     82052665                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        13477                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        13477                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data        13225                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total        13225                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    170871940                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    170871940                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    170871940                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    170871940                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000046                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000046                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000257                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000257                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000148                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000148                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000147                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000147                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000147                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000147                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40704.399407                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 40704.399407                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39423.502061                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 39423.502061                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        57500                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        57500                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 39629.574297                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 39629.574297                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 39629.574297                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 39629.574297                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        13562                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets          751                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               431                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              12                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    31.466357                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    62.583333                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks         1040                       # number of writebacks
-system.cpu.dcache.writebacks::total              1040                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data         2234                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total         2234                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        18291                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        18291                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        20525                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        20525                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        20525                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        20525                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1812                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total         1812                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2812                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         2812                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         4624                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         4624                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         4624                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         4624                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     79757000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     79757000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    131966500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    131966500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    211723500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    211723500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    211723500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    211723500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000020                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000020                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000034                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000034                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44016.004415                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44016.004415                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46929.765292                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46929.765292                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45787.954152                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 45787.954152                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45787.954152                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 45787.954152                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse              3959.582107                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse              3959.582108                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                   13162                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                  5412                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  2.432003                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.occ_blocks::writebacks   367.644751                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   2774.541574                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   2774.541575                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_blocks::cpu.data    817.395782                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::writebacks     0.011220                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.inst     0.084672                       # Average percentage of cache occupancy
@@ -746,16 +620,16 @@ system.cpu.l2cache.overall_misses::cpu.inst         3042                       #
 system.cpu.l2cache.overall_misses::cpu.data         4307                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         7349                       # number of overall misses
 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    148332000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     74801500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    223133500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     74802000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    223134000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    128955500                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total    128955500                       # number of ReadExReq miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.inst    148332000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    203757000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    352089000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    203757500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    352089500                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.inst    148332000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    203757000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    352089000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    203757500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    352089500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst        15795                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data         1811                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total        17606                       # number of ReadReq accesses(hits+misses)
@@ -781,16 +655,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst     0.192593
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.931445                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.359910                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48761.341223                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 49471.891534                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 48997.255160                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 49472.222222                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 48997.364954                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46137.924866                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46137.924866                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48761.341223                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47308.335268                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 47909.783644                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47308.451358                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 47909.851681                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48761.341223                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47308.335268                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 47909.783644                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47308.451358                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 47909.851681                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -853,5 +727,131 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36140.626733
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34915.655730                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35424.311635                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                   1414                       # number of replacements
+system.cpu.dcache.tagsinuse               3122.405384                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                170873491                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   4624                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               36953.609645                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    3122.405384                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.762306                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.762306                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     88815229                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        88815229                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     82031562                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       82031562                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        13475                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        13475                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data        13225                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total        13225                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     170846791                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        170846791                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    170846791                       # number of overall hits
+system.cpu.dcache.overall_hits::total       170846791                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         4046                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          4046                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        21103                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        21103                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data        25149                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total          25149                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data        25149                       # number of overall misses
+system.cpu.dcache.overall_misses::total         25149                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    164690500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    164690500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    831954164                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    831954164                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       115000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       115000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    996644664                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    996644664                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    996644664                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    996644664                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     88819275                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     88819275                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     82052665                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     82052665                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        13477                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        13477                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data        13225                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total        13225                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    170871940                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    170871940                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    170871940                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    170871940                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000046                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000046                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000257                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000257                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000148                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000148                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000147                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000147                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000147                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000147                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40704.522986                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 40704.522986                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39423.502061                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 39423.502061                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        57500                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        57500                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 39629.594179                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 39629.594179                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 39629.594179                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 39629.594179                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        13562                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          751                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               431                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              12                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    31.466357                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    62.583333                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks         1040                       # number of writebacks
+system.cpu.dcache.writebacks::total              1040                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data         2234                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total         2234                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        18291                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        18291                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        20525                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        20525                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        20525                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        20525                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1812                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total         1812                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2812                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         2812                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         4624                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         4624                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         4624                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         4624                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     79757500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     79757500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    131966500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    131966500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    211724000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    211724000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    211724000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    211724000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000020                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000020                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000034                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000034                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44016.280353                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44016.280353                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46929.765292                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46929.765292                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45788.062284                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 45788.062284                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45788.062284                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 45788.062284                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------