diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
| commit | 5a15909bac241dc795c691d49c4e2c68cab745f4 (patch) | |
| tree | d0ae694e320c725ed8116943c7179516567279f3 /tests/long/se/30.eon | |
| parent | ac515d7a9b131ffc9e128bd209fcddb2f383808b (diff) | |
| download | gem5-5a15909bac241dc795c691d49c4e2c68cab745f4.tar.xz | |
stats: Update stats for monitor, cache and bus changes
This patch removes the sparse histogram total from the CommMonitor
stats. It also bumps the stats after the unit fixes in the atomic
cache access. Lastly, it updates the stats to match the new port
ordering. All numbers are the same, and the only thing that changes is
which master corresponds to what port index.
Diffstat (limited to 'tests/long/se/30.eon')
5 files changed, 1587 insertions, 1587 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index dfb21513b..3f8921752 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.139913 # Number of seconds simulated -sim_ticks 139912878500 # Number of ticks simulated -final_tick 139912878500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.139916 # Number of seconds simulated +sim_ticks 139916242500 # Number of ticks simulated +final_tick 139916242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81894 # Simulator instruction rate (inst/s) -host_op_rate 81894 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28740964 # Simulator tick rate (ticks/s) -host_mem_usage 231128 # Number of bytes of host memory used -host_seconds 4868.07 # Real time elapsed on the host +host_inst_rate 84616 # Simulator instruction rate (inst/s) +host_op_rate 84616 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 29697100 # Simulator tick rate (ticks/s) +host_mem_usage 231112 # Number of bytes of host memory used +host_seconds 4711.44 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 214976 # Nu system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1536499 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1815530 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3352029 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1536499 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1536499 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1536499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1815530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3352029 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1536462 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1815486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3351948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1536462 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1536462 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1536462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1815486 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3351948 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7328 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 7328 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 139912806500 # Total gap between requests +system.physmem.totGap 139916169000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,10 +85,10 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4704 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1856 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 522 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1857 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 186 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -219,14 +219,14 @@ system.physmem.bytesPerActivate::7232-7233 1 0.14% 98.86% # system.physmem.bytesPerActivate::7296-7297 1 0.14% 99.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 7 1.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 702 # Bytes accessed per row activation -system.physmem.totQLat 37727500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 172831250 # Sum of mem lat for all requests +system.physmem.totQLat 39772250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 175041000 # Sum of mem lat for all requests system.physmem.totBusLat 36640000 # Total cycles spent in databus access -system.physmem.totBankLat 98463750 # Total cycles spent in bank access -system.physmem.avgQLat 5148.40 # Average queueing delay per request -system.physmem.avgBankLat 13436.65 # Average bank access latency per request +system.physmem.totBankLat 98628750 # Total cycles spent in bank access +system.physmem.avgQLat 5427.44 # Average queueing delay per request +system.physmem.avgBankLat 13459.16 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23585.05 # Average memory access latency +system.physmem.avgMemAccLat 23886.60 # Average memory access latency system.physmem.avgRdBW 3.35 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 3.35 # Average consumed read bandwidth in MB/s @@ -239,8 +239,8 @@ system.physmem.readRowHits 6626 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.42 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19092904.82 # Average gap between requests -system.membus.throughput 3352029 # Throughput (bytes/s) +system.physmem.avgGap 19093363.67 # Average gap between requests +system.membus.throughput 3351948 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 4183 # Transaction distribution system.membus.trans_dist::ReadResp 4183 # Transaction distribution system.membus.trans_dist::ReadExReq 3145 # Transaction distribution @@ -251,39 +251,39 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 468992 system.membus.tot_pkt_size 468992 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 468992 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8784000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8796500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 68408750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 68414000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 53489761 # Number of BP lookups -system.cpu.branchPred.condPredicted 30685482 # Number of conditional branches predicted +system.cpu.branchPred.lookups 53489675 # Number of BP lookups +system.cpu.branchPred.condPredicted 30685396 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 15149659 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 32882438 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15212539 # Number of BTB hits +system.cpu.branchPred.BTBLookups 32882352 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15212540 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 46.263416 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 46.263540 # BTB Hit Percentage system.cpu.branchPred.usedRAS 8007516 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 20 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 94754611 # DTB read hits +system.cpu.dtb.read_hits 94754653 # DTB read hits system.cpu.dtb.read_misses 21 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 94754632 # DTB read accesses -system.cpu.dtb.write_hits 73521122 # DTB write hits +system.cpu.dtb.read_accesses 94754674 # DTB read accesses +system.cpu.dtb.write_hits 73521120 # DTB write hits system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73521157 # DTB write accesses -system.cpu.dtb.data_hits 168275733 # DTB hits +system.cpu.dtb.write_accesses 73521155 # DTB write accesses +system.cpu.dtb.data_hits 168275773 # DTB hits system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168275789 # DTB accesses -system.cpu.itb.fetch_hits 48611325 # ITB hits +system.cpu.dtb.data_accesses 168275829 # DTB accesses +system.cpu.itb.fetch_hits 48611327 # ITB hits system.cpu.itb.fetch_misses 44520 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 48655845 # ITB accesses +system.cpu.itb.fetch_accesses 48655847 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -297,18 +297,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 279825758 # number of cpu cycles simulated +system.cpu.numCycles 279832486 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 29230506 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 24259255 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 280386575 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 29230507 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 24259168 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 280386579 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 439722434 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 119631956 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 439722438 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 119631954 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 219828437 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100484572 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.floatRegFileAccesses 219828435 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 100484570 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 168485322 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken). @@ -319,12 +319,12 @@ system.cpu.execution_unit.executions 205475782 # Nu system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 279401420 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 279400467 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7883 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13519017 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 266306741 # Number of cycles cpu stages are processed. -system.cpu.activity 95.168773 # Percentage of cycles cpu is active +system.cpu.timesIdled 7142 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13525828 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 266306658 # Number of cycles cpu stages are processed. +system.cpu.activity 95.166455 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -336,112 +336,112 @@ system.cpu.committedInsts 398664595 # Nu system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) -system.cpu.cpi 0.701908 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.701925 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.701908 # CPI: Total CPI of All Threads -system.cpu.ipc 1.424689 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.701925 # CPI: Total CPI of All Threads +system.cpu.ipc 1.424654 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.424689 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 78078009 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 201747749 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 72.097633 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 107174029 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 1.424654 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 78084810 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 201747676 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 72.095874 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 107180757 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 172651729 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.699727 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 102610556 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 177215202 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 63.330554 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 181081179 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 98744579 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 35.287880 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 90357849 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 189467909 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.709245 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 1975 # number of replacements -system.cpu.icache.tagsinuse 1830.982662 # Cycle average of tags in use -system.cpu.icache.total_refs 48606794 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3903 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12453.700743 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1830.982662 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.894035 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.894035 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 48606794 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 48606794 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 48606794 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 48606794 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 48606794 # number of overall hits -system.cpu.icache.overall_hits::total 48606794 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4531 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4531 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4531 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4531 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4531 # number of overall misses -system.cpu.icache.overall_misses::total 4531 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 268165000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 268165000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 268165000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 268165000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 268165000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 268165000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 48611325 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 48611325 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 48611325 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 48611325 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 48611325 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 48611325 # number of overall (read+write) accesses +system.cpu.stage1.utilization 61.698244 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 102617259 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 177215227 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 63.329040 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 181087860 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 98744626 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 35.287049 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 90364523 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 189467963 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 67.707637 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.tags.replacements 1975 # number of replacements +system.cpu.icache.tags.tagsinuse 1830.971183 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 48606795 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 3903 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12453.700999 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1830.971183 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894029 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894029 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 48606795 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 48606795 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 48606795 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 48606795 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 48606795 # number of overall hits +system.cpu.icache.overall_hits::total 48606795 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4532 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4532 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4532 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4532 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4532 # number of overall misses +system.cpu.icache.overall_misses::total 4532 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 272220250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 272220250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 272220250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 272220250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 272220250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 272220250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 48611327 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 48611327 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 48611327 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 48611327 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 48611327 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 48611327 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59184.506731 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 59184.506731 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 59184.506731 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 59184.506731 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 59184.506731 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 59184.506731 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 326 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60066.251103 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 60066.251103 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 60066.251103 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 60066.251103 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 60066.251103 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 60066.251103 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 330 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 236384250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 236384250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 236384250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 236384250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60172.303356 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60172.303356 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60172.303356 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60172.303356 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60172.303356 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60172.303356 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60564.757879 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60564.757879 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60564.757879 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60564.757879 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60564.757879 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60564.757879 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 3981449 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 3981353 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 4850 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 4850 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution @@ -457,23 +457,23 @@ system.cpu.toL2Bus.data_through_bus 557056 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 5001000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 5854500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6540750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6228499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6779999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3906.975758 # Cycle average of tags in use -system.cpu.l2cache.total_refs 753 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4717 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.159635 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 370.554458 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2908.829780 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 627.591520 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.088770 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019153 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.119231 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 3906.944649 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 753 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4717 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.159635 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 370.550028 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.807922 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 627.586699 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088770 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.019152 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.119230 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 544 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 667 # number of ReadReq hits @@ -498,17 +498,17 @@ system.cpu.l2cache.demand_misses::total 7328 # nu system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7328 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 225463500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 58932500 # 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number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4850 # number of ReadReq accesses(hits+misses) @@ -533,17 +533,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.909745 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.860620 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.909745 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67122.208991 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71520.024272 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67988.524982 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67822.416534 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67822.416534 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67122.208991 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69061.161502 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68381.413755 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67578.222685 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69061.161502 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68381.413755 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -563,17 +563,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7328 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 183879500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 48740750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 232620250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 174684500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 174684500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 183879500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 223425250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 407304750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 183879500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 223425250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 407304750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 184726250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 49135000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 233861250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 175601750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 175601750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 184726250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 224736750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 409463000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 184726250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 224736750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 409463000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses @@ -585,51 +585,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54742.334028 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59151.395631 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59629.854369 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55907.542434 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55835.214626 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55835.214626 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54994.417982 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56623.015873 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55876.501092 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54994.417982 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56623.015873 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55876.501092 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3284.992544 # Cycle average of tags in use -system.cpu.dcache.total_refs 168254254 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 40523.664258 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3284.992544 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.802000 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.802000 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 764 # number of replacements +system.cpu.dcache.tags.tagsinuse 3284.967259 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168254256 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40523.664740 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3284.967259 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.801994 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.801994 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94753181 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753181 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501073 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501073 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168254254 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168254254 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168254254 # number of overall hits -system.cpu.dcache.overall_hits::total 168254254 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501075 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501075 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168254256 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168254256 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168254256 # number of overall hits +system.cpu.dcache.overall_hits::total 168254256 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1308 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1308 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19656 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19656 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 20964 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20964 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 20964 # number of overall misses -system.cpu.dcache.overall_misses::total 20964 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 84017000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 84017000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1065172500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1065172500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1149189500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1149189500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1149189500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1149189500 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 19654 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19654 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 20962 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20962 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 20962 # number of overall misses +system.cpu.dcache.overall_misses::total 20962 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 85220999 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 85220999 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1076127000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1076127000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1161347999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1161347999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1161347999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1161347999 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -646,19 +646,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000125 system.cpu.dcache.demand_miss_rate::total 0.000125 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000125 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000125 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64233.180428 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 64233.180428 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54190.705128 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54190.705128 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54817.282007 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54817.282007 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54817.282007 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54817.282007 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 28818 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65153.668960 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 65153.668960 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54753.587056 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54753.587056 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55402.537878 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55402.537878 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55402.537878 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55402.537878 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29647 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 562 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 596 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 51.277580 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.743289 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -666,12 +666,12 @@ system.cpu.dcache.writebacks::writebacks 649 # nu system.cpu.dcache.writebacks::total 649 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 358 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 358 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16454 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16454 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 16812 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 16812 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 16812 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 16812 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16452 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16452 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16810 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16810 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16810 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16810 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses @@ -680,14 +680,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 61415001 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 61415001 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 217011500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 217011500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 278426501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 278426501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 278426501 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 278426501 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 61946751 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 61946751 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 218347750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 218347750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 280294501 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 280294501 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 280294501 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 280294501 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -696,14 +696,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64647.369474 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64647.369474 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67773.735166 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67773.735166 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67058.405829 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67058.405829 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67058.405829 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67058.405829 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65207.106316 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65207.106316 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68191.052467 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68191.052467 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67508.309489 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67508.309489 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67508.309489 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67508.309489 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 73956e98a..1f99291ed 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,56 +1,56 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.077363 # Number of seconds simulated -sim_ticks 77363103500 # Number of ticks simulated -final_tick 77363103500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.077522 # Number of seconds simulated +sim_ticks 77521581000 # Number of ticks simulated +final_tick 77521581000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 219490 # Simulator instruction rate (inst/s) -host_op_rate 219490 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45211856 # Simulator tick rate (ticks/s) +host_inst_rate 159390 # Simulator instruction rate (inst/s) +host_op_rate 159390 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32899346 # Simulator tick rate (ticks/s) host_mem_usage 233160 # Number of bytes of host memory used -host_seconds 1711.12 # Real time elapsed on the host +host_seconds 2356.33 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 220864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255360 # Number of bytes read from this memory -system.physmem.bytes_read::total 476224 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 220864 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 220864 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3451 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3990 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7441 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2854901 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3300798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6155699 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2854901 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2854901 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2854901 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3300798 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6155699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7441 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 220992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255296 # Number of bytes read from this memory +system.physmem.bytes_read::total 476288 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 220992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220992 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3453 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3989 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7442 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2850716 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3293225 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6143941 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2850716 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2850716 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2850716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3293225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6143941 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7442 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7441 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 476224 # Total number of bytes read from memory +system.physmem.cpureqs 7442 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 476288 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 476224 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 476288 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 524 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 654 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 449 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 599 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 527 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 653 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 447 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 600 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 447 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 455 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 516 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 517 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 524 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 435 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 436 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 405 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 339 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 337 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 305 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 414 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 543 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 453 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 542 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 454 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 379 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 77363015000 # Total gap between requests +system.physmem.totGap 77521491500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7441 # Categorize read packet sizes +system.physmem.readPktSize::6 7442 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,10 +85,10 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4419 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2033 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 692 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2027 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 699 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 243 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -149,138 +149,138 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 761 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 617.293035 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 239.548208 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1200.351847 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 242 31.80% 31.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 107 14.06% 45.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 65 8.54% 54.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 58 7.62% 62.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 31 4.07% 66.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 22 2.89% 68.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 22 2.89% 71.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 17 2.23% 74.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 13 1.71% 75.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 18 2.37% 78.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 4 0.53% 78.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 12 1.58% 80.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 9 1.18% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 10 1.31% 82.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 5 0.66% 83.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 5 0.66% 84.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 18 2.37% 86.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 4 0.53% 86.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 4 0.53% 87.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 2 0.26% 87.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 3 0.39% 88.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 7 0.92% 89.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 4 0.53% 89.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 4 0.53% 90.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.39% 90.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 5 0.66% 91.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 7 0.92% 92.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 1 0.13% 92.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 4 0.53% 92.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 3 0.39% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 1 0.13% 93.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 4 0.53% 93.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 3 0.39% 94.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 2 0.26% 94.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 3 0.39% 94.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.13% 95.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 1 0.13% 95.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 1 0.13% 95.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 2 0.26% 95.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 3 0.39% 95.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.13% 96.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 2 0.26% 96.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 2 0.26% 96.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.13% 96.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.13% 96.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.13% 96.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.26% 97.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 1 0.13% 97.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.13% 97.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 1 0.13% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 1 0.13% 97.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.13% 97.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.13% 98.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 1 0.13% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.13% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 1 0.13% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 1 0.13% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.13% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.13% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 1 0.13% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 1 0.13% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 7 0.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 761 # Bytes accessed per row activation -system.physmem.totQLat 39473750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 177700000 # Sum of mem lat for all requests -system.physmem.totBusLat 37205000 # Total cycles spent in databus access -system.physmem.totBankLat 101021250 # Total cycles spent in bank access -system.physmem.avgQLat 5304.90 # Average queueing delay per request -system.physmem.avgBankLat 13576.30 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 756 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 621.460317 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 241.668493 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1200.727367 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 238 31.48% 31.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 108 14.29% 45.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 62 8.20% 53.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 57 7.54% 61.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 33 4.37% 65.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 22 2.91% 68.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 21 2.78% 71.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 18 2.38% 73.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 13 1.72% 75.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 16 2.12% 77.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 6 0.79% 78.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 12 1.59% 80.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 9 1.19% 81.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 9 1.19% 82.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 5 0.66% 83.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 6 0.79% 83.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 17 2.25% 86.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 4 0.53% 86.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 4 0.53% 87.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 2 0.26% 87.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 3 0.40% 87.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 7 0.93% 88.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 4 0.53% 89.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 4 0.53% 89.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.40% 90.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 6 0.79% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 7 0.93% 92.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 1 0.13% 92.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 4 0.53% 92.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 3 0.40% 93.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 1 0.13% 93.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 4 0.53% 93.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 3 0.40% 94.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 2 0.26% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 2 0.26% 94.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.13% 94.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 1 0.13% 94.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 1 0.13% 95.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.13% 95.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 2 0.26% 95.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 3 0.40% 95.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 2 0.26% 96.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.13% 96.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 2 0.26% 96.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.13% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.13% 96.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.13% 96.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 2 0.26% 97.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 1 0.13% 97.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 1 0.13% 97.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 2 0.26% 97.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 1 0.13% 97.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.13% 98.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.13% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.13% 98.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 1 0.13% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 1 0.13% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.13% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.13% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 1 0.13% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 1 0.13% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 7 0.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 756 # Bytes accessed per row activation +system.physmem.totQLat 42048500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 179991000 # Sum of mem lat for all requests +system.physmem.totBusLat 37210000 # Total cycles spent in databus access +system.physmem.totBankLat 100732500 # Total cycles spent in bank access +system.physmem.avgQLat 5650.16 # Average queueing delay per request +system.physmem.avgBankLat 13535.68 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23881.20 # Average memory access latency -system.physmem.avgRdBW 6.16 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24185.84 # Average memory access latency +system.physmem.avgRdBW 6.14 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 6.16 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 6.14 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6680 # Number of row buffer hits during reads +system.physmem.readRowHits 6686 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.77 # Row buffer hit rate for reads +system.physmem.readRowHitRate 89.84 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 10396857.28 # Average gap between requests -system.membus.throughput 6155699 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4309 # Transaction distribution -system.membus.trans_dist::ReadResp 4309 # Transaction distribution +system.physmem.avgGap 10416755.11 # Average gap between requests +system.membus.throughput 6143941 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4310 # Transaction distribution +system.membus.trans_dist::ReadResp 4310 # Transaction distribution system.membus.trans_dist::ReadExReq 3132 # Transaction distribution system.membus.trans_dist::ReadExResp 3132 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 14882 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 14882 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 476224 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 476224 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 476224 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side 14884 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 14884 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 476288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 476288 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 476288 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 9093000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9304000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 69496500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 69668500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.branchPred.lookups 50225543 # Number of BP lookups -system.cpu.branchPred.condPredicted 29217666 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1195897 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25687498 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23216118 # Number of BTB hits +system.cpu.branchPred.lookups 50329141 # Number of BP lookups +system.cpu.branchPred.condPredicted 29286929 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1209855 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 26570475 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23288927 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 90.379055 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9009525 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1024 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 87.649645 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9008918 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1078 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 101778798 # DTB read hits -system.cpu.dtb.read_misses 78056 # DTB read misses -system.cpu.dtb.read_acv 48605 # DTB read access violations -system.cpu.dtb.read_accesses 101856854 # DTB read accesses -system.cpu.dtb.write_hits 78401927 # DTB write hits -system.cpu.dtb.write_misses 1498 # DTB write misses -system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 78403425 # DTB write accesses -system.cpu.dtb.data_hits 180180725 # DTB hits -system.cpu.dtb.data_misses 79554 # DTB misses -system.cpu.dtb.data_acv 48607 # DTB access violations -system.cpu.dtb.data_accesses 180260279 # DTB accesses -system.cpu.itb.fetch_hits 50199009 # ITB hits -system.cpu.itb.fetch_misses 367 # ITB misses +system.cpu.dtb.read_hits 101805775 # DTB read hits +system.cpu.dtb.read_misses 78244 # DTB read misses +system.cpu.dtb.read_acv 48603 # DTB read access violations +system.cpu.dtb.read_accesses 101884019 # DTB read accesses +system.cpu.dtb.write_hits 78424815 # DTB write hits +system.cpu.dtb.write_misses 1501 # DTB write misses +system.cpu.dtb.write_acv 3 # DTB write access violations +system.cpu.dtb.write_accesses 78426316 # DTB write accesses +system.cpu.dtb.data_hits 180230590 # DTB hits +system.cpu.dtb.data_misses 79745 # DTB misses +system.cpu.dtb.data_acv 48606 # DTB access violations +system.cpu.dtb.data_accesses 180310335 # DTB accesses +system.cpu.itb.fetch_hits 50278510 # ITB hits +system.cpu.itb.fetch_misses 355 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 50199376 # ITB accesses +system.cpu.itb.fetch_accesses 50278865 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -294,238 +294,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 154726209 # number of cpu cycles simulated +system.cpu.numCycles 155043164 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 51083952 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 448497930 # Number of instructions fetch has processed -system.cpu.fetch.Branches 50225543 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 32225643 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 78739470 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6093368 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19754761 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 10148 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 20 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 50199009 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 408107 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 154447023 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.903895 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.325218 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 51171798 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 449189873 # Number of instructions fetch has processed +system.cpu.fetch.Branches 50329141 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 32297845 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 78873322 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6177793 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19775166 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 181 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 10164 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 50278510 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 413807 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 154759425 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.902504 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.324797 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 75707553 49.02% 49.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4276532 2.77% 51.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6874422 4.45% 56.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5367897 3.48% 59.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11734775 7.60% 67.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 7804305 5.05% 72.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5608156 3.63% 76.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1827762 1.18% 77.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35245621 22.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 75886103 49.03% 49.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4289159 2.77% 51.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6884479 4.45% 56.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5373987 3.47% 59.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11775541 7.61% 67.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 7819980 5.05% 72.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5600753 3.62% 76.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1832171 1.18% 77.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35297252 22.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154447023 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.324609 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.898655 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 56435005 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 15098519 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74108370 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3950827 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4854302 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9469599 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4266 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 444616188 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12118 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4854302 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 59563357 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4893725 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 414604 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 75021983 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9699052 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 440177556 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 167 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 18387 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8017745 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 287187239 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 578692114 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 306192880 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 272499234 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 154759425 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.324614 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.897192 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 56546720 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 15105326 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74238970 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3943829 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4924580 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9495837 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4282 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 445245835 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12211 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4924580 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 59688043 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4892244 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 416020 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 75141817 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9696721 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 440741300 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 165 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 25268 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8017940 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 287478957 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 579418122 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 306415899 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 273002223 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27654910 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 36841 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 298 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 27864767 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104645789 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80545124 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8910343 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6399312 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 408008914 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 286 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 401637302 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 964402 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32300806 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15167317 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 71 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154447023 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.600486 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.995525 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 27946628 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 36876 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 265 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 27780890 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104697675 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80623147 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8951892 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6419862 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 408420930 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 258 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 401925039 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 976126 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32712161 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15467708 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 43 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154759425 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.597096 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.996071 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 28234595 18.28% 18.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 25848670 16.74% 35.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25579083 16.56% 51.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 24239826 15.69% 67.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21261159 13.77% 81.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15485386 10.03% 91.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8478015 5.49% 96.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3990980 2.58% 99.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1329309 0.86% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 28451061 18.38% 18.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 25861408 16.71% 35.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25614965 16.55% 51.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24252162 15.67% 67.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21259746 13.74% 81.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15502795 10.02% 91.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8516760 5.50% 96.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3980528 2.57% 99.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1320000 0.85% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154447023 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154759425 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 34190 0.29% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 34116 0.29% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 57000 0.48% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 5570 0.05% 0.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 5383 0.05% 0.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1934681 16.39% 17.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1747492 14.80% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5061407 42.87% 74.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2960127 25.07% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 59668 0.50% 0.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 5432 0.05% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 5299 0.04% 0.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1955339 16.54% 17.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1744150 14.75% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5075259 42.92% 75.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2944520 24.90% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 155697269 38.77% 38.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126268 0.53% 39.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 155814394 38.77% 38.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126224 0.53% 39.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32795718 8.17% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7492895 1.87% 49.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2793275 0.70% 50.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16555197 4.12% 54.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1576539 0.39% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103353833 25.73% 80.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 79212727 19.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32839124 8.17% 47.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7506811 1.87% 49.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2794214 0.70% 50.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16556558 4.12% 54.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1581320 0.39% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103393269 25.72% 80.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 79279544 19.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 401637302 # Type of FU issued -system.cpu.iq.rate 2.595794 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11805850 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.029394 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 633814426 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 260039391 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 234669938 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 336677453 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 180319624 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 161314335 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 241373993 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 172035578 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 15061229 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 401925039 # Type of FU issued +system.cpu.iq.rate 2.592343 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11823783 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.029418 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 634356878 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 260386455 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 234772610 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 337052534 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 180795959 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 161415506 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 241485172 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172230069 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 15009534 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 9891302 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 112335 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 49025 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7024395 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 9943188 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 112068 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 49084 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7102418 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 260907 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3733 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 260799 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3689 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4854302 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2516728 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 369298 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 432783708 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 121887 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104645789 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80545124 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 286 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 93 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 98 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 49025 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 940065 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 405593 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1345658 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 398139116 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101905490 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3498186 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4924580 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2516499 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 372884 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 433248692 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 121349 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104697675 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80623147 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 258 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 99 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 81 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 49084 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 956530 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 406825 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1363355 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 398354690 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101932663 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3570349 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24774508 # number of nop insts executed -system.cpu.iew.exec_refs 180308945 # number of memory reference insts executed -system.cpu.iew.exec_branches 46542252 # Number of branches executed -system.cpu.iew.exec_stores 78403455 # Number of stores executed -system.cpu.iew.exec_rate 2.573185 # Inst execution rate -system.cpu.iew.wb_sent 396614980 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 395984273 # cumulative count of insts written-back -system.cpu.iew.wb_producers 193530512 # num instructions producing a value -system.cpu.iew.wb_consumers 271082574 # num instructions consuming a value +system.cpu.iew.exec_nop 24827504 # number of nop insts executed +system.cpu.iew.exec_refs 180359006 # number of memory reference insts executed +system.cpu.iew.exec_branches 46573877 # Number of branches executed +system.cpu.iew.exec_stores 78426343 # Number of stores executed +system.cpu.iew.exec_rate 2.569315 # Inst execution rate +system.cpu.iew.wb_sent 396825960 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 396188116 # cumulative count of insts written-back +system.cpu.iew.wb_producers 193569295 # num instructions producing a value +system.cpu.iew.wb_consumers 271188688 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.559258 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.713917 # average fanout of values written-back +system.cpu.iew.wb_rate 2.555341 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.713781 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 34145749 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 34614887 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1191710 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149592721 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.665000 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.996623 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1205659 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149834845 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.660693 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.995613 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 55286060 36.96% 36.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 22516991 15.05% 52.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13020116 8.70% 60.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11469174 7.67% 68.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8183204 5.47% 73.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5453733 3.65% 77.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5164454 3.45% 80.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3280279 2.19% 83.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 25218710 16.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 55453685 37.01% 37.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22592497 15.08% 52.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13053957 8.71% 60.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11447163 7.64% 68.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8190236 5.47% 73.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5440968 3.63% 77.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5148789 3.44% 80.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3296235 2.20% 83.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 25211315 16.83% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149592721 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 149834845 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -536,212 +536,212 @@ system.cpu.commit.branches 44587533 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 25218710 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 25211315 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 557181366 # The number of ROB reads -system.cpu.rob.rob_writes 870483842 # The number of ROB writes -system.cpu.timesIdled 3633 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 279186 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 557900023 # The number of ROB reads +system.cpu.rob.rob_writes 871491746 # The number of ROB writes +system.cpu.timesIdled 3551 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 283739 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated -system.cpu.cpi 0.411972 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.411972 # CPI: Total CPI of All Threads -system.cpu.ipc 2.427351 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.427351 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 397971851 # number of integer regfile reads -system.cpu.int_regfile_writes 170072905 # number of integer regfile writes -system.cpu.fp_regfile_reads 156478965 # number of floating regfile reads -system.cpu.fp_regfile_writes 104018276 # number of floating regfile writes +system.cpu.cpi 0.412816 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.412816 # CPI: Total CPI of All Threads +system.cpu.ipc 2.422389 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.422389 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 398140602 # number of integer regfile reads +system.cpu.int_regfile_writes 170166273 # number of integer regfile writes +system.cpu.fp_regfile_reads 156587084 # number of floating regfile reads +system.cpu.fp_regfile_writes 104079306 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 7367647 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 5060 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5060 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 655 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3191 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3191 # Transaction distribution +system.cpu.toL2Bus.throughput 7370748 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 5062 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5062 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 666 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3200 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3200 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 8148 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 9009 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 17157 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 9042 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 17190 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 260736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 309248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 569984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 569984 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 310656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 571392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 571392 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 5108000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 5130000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6111000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6844000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6265500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6767250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.replacements 2147 # number of replacements -system.cpu.icache.tagsinuse 1831.625379 # Cycle average of tags in use -system.cpu.icache.total_refs 50193388 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4074 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12320.419244 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1831.625379 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.894348 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.894348 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 50193388 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 50193388 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 50193388 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 50193388 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 50193388 # number of overall hits -system.cpu.icache.overall_hits::total 50193388 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5621 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5621 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5621 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5621 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5621 # number of overall misses -system.cpu.icache.overall_misses::total 5621 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 317313500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 317313500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 317313500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 317313500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 317313500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 317313500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 50199009 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 50199009 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 50199009 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 50199009 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 50199009 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 50199009 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 2147 # number of replacements +system.cpu.icache.tags.tagsinuse 1831.618681 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 50272888 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4074 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12339.933235 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1831.618681 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894345 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894345 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 50272888 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 50272888 # 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average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59049.828179 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 59049.828179 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59567.255768 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59567.255768 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59567.255768 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 59567.255768 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59567.255768 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 59567.255768 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # 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number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4188 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8262 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 4074 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4177 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 8251 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.847079 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870183 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.851581 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981510 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.981510 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.847079 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.955231 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.901830 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.847079 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.955231 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.901830 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66720.805564 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75148.601399 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68398.932467 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68035.280971 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68035.280971 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66720.805564 # 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miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.978750 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.847570 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.952483 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.900750 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.847570 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.952483 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.900750 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67299.087750 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69029.176334 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68396.471903 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68396.471903 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67299.087750 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70030.020055 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68762.899758 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67299.087750 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70030.020055 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68762.899758 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -750,162 +750,162 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3451 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 858 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4309 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3453 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 857 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4310 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3132 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 3132 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3451 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3990 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7441 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3451 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3990 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7441 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 187216000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 53949250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 241165250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 174832750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 174832750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 187216000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 228782000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 415998000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 187216000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 228782000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 415998000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.847079 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870183 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.851581 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981510 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981510 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.847079 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955231 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.901830 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.847079 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955231 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.901830 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54249.782672 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62877.913753 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55967.799954 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55821.439974 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55821.439974 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54249.782672 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57338.847118 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55906.195404 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54249.782672 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57338.847118 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55906.195404 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3453 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3989 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7442 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3453 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3989 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7442 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 188417250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54498500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 242915750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 175604250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 175604250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 188417250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 230102750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 418520000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 188417250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 230102750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 418520000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.847570 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867409 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.851442 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.978750 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.978750 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.847570 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.952483 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.900750 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.847570 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.952483 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.900750 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54566.246742 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63592.182030 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56360.962877 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56067.768199 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56067.768199 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54566.246742 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57684.319378 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56237.570546 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54566.246742 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57684.319378 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56237.570546 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 776 # number of replacements -system.cpu.dcache.tagsinuse 3295.678448 # Cycle average of tags in use -system.cpu.dcache.total_refs 159952392 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4177 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 38293.605937 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3295.678448 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.804609 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.804609 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 86451599 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86451599 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73500787 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73500787 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 159952386 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 159952386 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 159952386 # number of overall hits -system.cpu.dcache.overall_hits::total 159952386 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1809 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1809 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19942 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19942 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21751 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21751 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21751 # number of overall misses -system.cpu.dcache.overall_misses::total 21751 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 111333000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 111333000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1028184585 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1028184585 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1139517585 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1139517585 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1139517585 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1139517585 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86453408 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86453408 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.replacements 788 # number of replacements +system.cpu.dcache.tags.tagsinuse 3294.798817 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 160031202 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4188 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 38211.843840 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3294.798817 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.804394 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.804394 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 86530434 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86530434 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73500763 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73500763 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 160031197 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 160031197 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 160031197 # number of overall hits +system.cpu.dcache.overall_hits::total 160031197 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1798 # 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number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1153750837 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1153750837 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1153750837 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86532232 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86532232 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 159974137 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 159974137 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 159974137 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 159974137 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 160052961 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 160052961 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 160052961 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 160052961 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000271 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000271 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000272 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000272 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000136 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000136 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000136 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000136 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61543.946932 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61543.946932 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51558.749624 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 51558.749624 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52389.204404 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52389.204404 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52389.204404 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52389.204404 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 37387 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63645.300334 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63645.300334 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52054.321697 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52054.321697 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53011.892897 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53011.892897 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53011.892897 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53011.892897 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 38531 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 654 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.166667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 58.915902 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 655 # number of writebacks -system.cpu.dcache.writebacks::total 655 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 823 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 823 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16751 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16751 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17574 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17574 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17574 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17574 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 986 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 986 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3191 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3191 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4177 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4177 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4177 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4177 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 66792500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 66792500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 216966500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 216966500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 283759000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 283759000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 283759000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 283759000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 666 # number of writebacks +system.cpu.dcache.writebacks::total 666 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 810 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 810 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16766 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16766 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17576 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17576 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17576 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17576 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 988 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 988 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3200 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3200 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4188 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4188 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4188 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4188 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67480500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 67480500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 218199250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 218199250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 285679750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 285679750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 285679750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 285679750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67740.872211 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67740.872211 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67993.262300 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67993.262300 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67933.684463 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67933.684463 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67933.684463 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67933.684463 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68300.101215 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68300.101215 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68187.265625 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68187.265625 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68213.884909 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68213.884909 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68213.884909 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68213.884909 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index ff5b38f2f..2e7f2c614 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 1134670186 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 1769 # number of replacements -system.cpu.icache.tagsinuse 1795.138964 # Cycle average of tags in use -system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1795.138964 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.876533 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1769 # number of replacements +system.cpu.icache.tags.tagsinuse 1795.138964 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1795.138964 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.876533 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits @@ -175,19 +175,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 47648.516199 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3772.485305 # Cycle average of tags in use -system.cpu.l2cache.total_refs 677 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4566 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.148270 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 371.540221 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2770.469924 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 630.475161 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011339 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019241 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.115127 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 3772.485305 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 677 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4566 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.148270 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 371.540221 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.469924 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 630.475161 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011339 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.019241 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.115127 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 468 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 591 # number of ReadReq hits @@ -311,15 +311,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3288.930576 # Cycle average of tags in use -system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3288.930576 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.802962 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 764 # number of replacements +system.cpu.dcache.tags.tagsinuse 3288.930576 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3288.930576 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.802962 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 3fe39b26c..31843ed63 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068340 # Number of seconds simulated -sim_ticks 68340072000 # Number of ticks simulated -final_tick 68340072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.068375 # Number of seconds simulated +sim_ticks 68375005500 # Number of ticks simulated +final_tick 68375005500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97727 # Simulator instruction rate (inst/s) -host_op_rate 124939 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24460648 # Simulator tick rate (ticks/s) -host_mem_usage 254748 # Number of bytes of host memory used -host_seconds 2793.88 # Real time elapsed on the host +host_inst_rate 171790 # Simulator instruction rate (inst/s) +host_op_rate 219625 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43020256 # Simulator tick rate (ticks/s) +host_mem_usage 254724 # Number of bytes of host memory used +host_seconds 1589.37 # Real time elapsed on the host sim_insts 273036725 # Number of instructions simulated sim_ops 349064449 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 193856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272320 # Number of bytes read from this memory -system.physmem.bytes_read::total 466176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 193856 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 193856 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3029 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4255 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7284 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2836637 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3984778 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6821415 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2836637 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2836637 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2836637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3984778 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6821415 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7284 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 194176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272256 # Number of bytes read from this memory +system.physmem.bytes_read::total 466432 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 194176 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 194176 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3034 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4254 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7288 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2839868 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3981806 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6821674 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2839868 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2839868 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2839868 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3981806 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6821674 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7288 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7289 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 466176 # Total number of bytes read from memory +system.physmem.cpureqs 7293 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 466432 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 466176 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 466432 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 5 # Reqs where no action is needed system.physmem.perBankRdReqs::0 605 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 803 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 607 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 525 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 802 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 608 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 526 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 442 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 354 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 161 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 353 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 163 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 219 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 210 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 208 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 288 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 325 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 414 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 530 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 686 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 611 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 504 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 323 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 416 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 529 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 688 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 612 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 506 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 68339875000 # Total gap between requests +system.physmem.totGap 68374814000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7284 # Categorize read packet sizes +system.physmem.readPktSize::6 7288 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,12 +85,12 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4420 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 561 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4427 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2050 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 168 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 65 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -149,62 +149,62 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 717 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 639.642957 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 236.501213 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1328.325684 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 231 32.22% 32.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 96 13.39% 45.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 63 8.79% 54.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 56 7.81% 62.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 30 4.18% 66.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 30 4.18% 70.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 16 2.23% 72.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 21 2.93% 75.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 13 1.81% 77.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 17 2.37% 79.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 8 1.12% 81.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 12 1.67% 82.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 3 0.42% 83.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 9 1.26% 84.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 5 0.70% 85.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 7 0.98% 86.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 5 0.70% 86.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 5 0.70% 87.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 4 0.56% 88.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 4 0.56% 88.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 2 0.28% 88.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 4 0.56% 89.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3 0.42% 89.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 4 0.56% 90.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 4 0.56% 90.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 2 0.28% 91.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 2 0.28% 91.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 2 0.28% 91.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 2 0.28% 92.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 2 0.28% 92.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 2 0.28% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 3 0.42% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 3 0.42% 93.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.14% 93.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 2 0.28% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 2 0.28% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.14% 94.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 2 0.28% 94.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.14% 94.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 2 0.28% 94.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 718 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 639.554318 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 239.565124 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1324.415379 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 223 31.06% 31.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 101 14.07% 45.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 63 8.77% 53.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 56 7.80% 61.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 31 4.32% 66.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 32 4.46% 70.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 16 2.23% 72.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 24 3.34% 76.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 9 1.25% 77.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 16 2.23% 79.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 9 1.25% 80.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 12 1.67% 82.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 5 0.70% 83.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 9 1.25% 84.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 7 0.97% 85.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 6 0.84% 86.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 4 0.56% 86.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 3 0.42% 87.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 5 0.70% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 4 0.56% 88.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 3 0.42% 88.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 3 0.42% 89.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 4 0.56% 89.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 5 0.70% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 4 0.56% 91.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 3 0.42% 91.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 2 0.28% 91.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 3 0.42% 92.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 1 0.14% 92.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 2 0.28% 92.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 2 0.28% 92.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 3 0.42% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 3 0.42% 93.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 2 0.28% 94.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.14% 94.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.14% 94.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.14% 94.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 1 0.14% 94.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.14% 94.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 2 0.28% 94.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::2816-2817 2 0.28% 95.26% # Bytes accessed per row activation system.physmem.bytesPerActivate::2880-2881 1 0.14% 95.40% # Bytes accessed per row activation system.physmem.bytesPerActivate::3072-3073 3 0.42% 95.82% # Bytes accessed per row activation system.physmem.bytesPerActivate::3136-3137 1 0.14% 95.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.14% 96.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 1 0.14% 96.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.14% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 1 0.14% 96.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.14% 96.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.14% 96.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 1 0.14% 96.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.14% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.14% 96.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 1 0.14% 96.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.14% 96.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 1 0.14% 96.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.14% 96.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.14% 96.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 1 0.14% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 1 0.14% 97.08% # Bytes accessed per row activation system.physmem.bytesPerActivate::4800-4801 1 0.14% 97.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::4864-4865 2 0.28% 97.49% # Bytes accessed per row activation system.physmem.bytesPerActivate::5632-5633 1 0.14% 97.63% # Bytes accessed per row activation @@ -214,15 +214,15 @@ system.physmem.bytesPerActivate::6656-6657 1 0.14% 98.05% # system.physmem.bytesPerActivate::6912-6913 2 0.28% 98.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 2 0.28% 98.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 10 1.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 717 # Bytes accessed per row activation -system.physmem.totQLat 39275000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 171092500 # Sum of mem lat for all requests -system.physmem.totBusLat 36420000 # Total cycles spent in databus access -system.physmem.totBankLat 95397500 # Total cycles spent in bank access -system.physmem.avgQLat 5391.95 # Average queueing delay per request -system.physmem.avgBankLat 13096.86 # Average bank access latency per request +system.physmem.bytesPerActivate::total 718 # Bytes accessed per row activation +system.physmem.totQLat 36604250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 168483000 # Sum of mem lat for all requests +system.physmem.totBusLat 36440000 # Total cycles spent in databus access +system.physmem.totBankLat 95438750 # Total cycles spent in bank access +system.physmem.avgQLat 5022.54 # Average queueing delay per request +system.physmem.avgBankLat 13095.33 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23488.81 # Average memory access latency +system.physmem.avgMemAccLat 23117.86 # Average memory access latency system.physmem.avgRdBW 6.82 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 6.82 # Average consumed read bandwidth in MB/s @@ -231,37 +231,37 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6567 # Number of row buffer hits during reads +system.physmem.readRowHits 6570 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.16 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.15 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9382190.42 # Average gap between requests -system.membus.throughput 6821415 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4461 # Transaction distribution -system.membus.trans_dist::ReadResp 4461 # Transaction distribution +system.physmem.avgGap 9381835.07 # Average gap between requests +system.membus.throughput 6821674 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4467 # Transaction distribution +system.membus.trans_dist::ReadResp 4467 # Transaction distribution system.membus.trans_dist::UpgradeReq 5 # Transaction distribution system.membus.trans_dist::UpgradeResp 5 # Transaction distribution -system.membus.trans_dist::ReadExReq 2823 # Transaction distribution -system.membus.trans_dist::ReadExResp 2823 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 14578 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 14578 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 466176 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 466176 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 466176 # Total data (bytes) +system.membus.trans_dist::ReadExReq 2821 # Transaction distribution +system.membus.trans_dist::ReadExResp 2821 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 14586 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 14586 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 466432 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 466432 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 466432 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8863500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8910500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 67994996 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 68010245 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.branchPred.lookups 35386289 # Number of BP lookups -system.cpu.branchPred.condPredicted 21204879 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1638532 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19153921 # Number of BTB lookups -system.cpu.branchPred.BTBHits 16759106 # Number of BTB hits +system.cpu.branchPred.lookups 35388733 # Number of BP lookups +system.cpu.branchPred.condPredicted 21200896 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1644934 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19122518 # Number of BTB lookups +system.cpu.branchPred.BTBHits 16795427 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.496999 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6781793 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 8488 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 87.830625 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6785564 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 8441 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -305,100 +305,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 136680145 # number of cpu cycles simulated +system.cpu.numCycles 136750012 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 38911514 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 317585001 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35386289 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23540899 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70801219 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6795871 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 21500027 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 100 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1484 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 53 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37522622 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 503492 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 136360129 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.984944 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.454705 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 38949353 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 317676023 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35388733 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23580991 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70834954 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6803690 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 21493719 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1383 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 54 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 37560816 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 509146 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 136426737 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.984407 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.454366 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66188924 48.54% 48.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6771554 4.97% 53.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5692762 4.17% 57.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6083969 4.46% 62.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4907326 3.60% 65.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4077145 2.99% 68.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3184432 2.34% 71.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4135342 3.03% 74.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35318675 25.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66221739 48.54% 48.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6780898 4.97% 53.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5694782 4.17% 57.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6088849 4.46% 62.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4909575 3.60% 65.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4088004 3.00% 68.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3182942 2.33% 71.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4139594 3.03% 74.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35320354 25.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 136360129 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258899 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.323564 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45414780 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16659439 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 66663560 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2545187 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5077163 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7331349 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 68935 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401047467 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 212517 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5077163 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50947779 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1931381 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 327570 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 63615860 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14460376 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 393522571 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 45 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1660698 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10177766 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1066 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 432139045 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2330040462 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1257112117 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1072928345 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 136426737 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258784 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.323042 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45449120 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16657240 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 66693516 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2548377 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5078484 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7335953 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69077 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401163284 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 211870 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5078484 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50979253 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1928009 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 329001 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 63651330 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14460660 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 393604020 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 59 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1657735 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10191603 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1124 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 432142984 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2330358431 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1257645546 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1072712885 # Number of floating rename lookups system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 47572852 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11802 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11801 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 36468583 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 103474945 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 91276854 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4259608 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5261316 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 384098955 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22768 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 373971213 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1208914 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 34303040 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 86231470 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 648 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 136360129 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.742526 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.023578 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 47576791 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11831 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11830 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 36438205 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 103461367 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 91301104 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4273842 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5281559 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 384115412 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22788 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 373986631 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1200950 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 34324808 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 86133615 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 668 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 136426737 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.741300 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.023490 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24894566 18.26% 18.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19912259 14.60% 32.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20562905 15.08% 47.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18156426 13.32% 61.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24028186 17.62% 78.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15708589 11.52% 90.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8792760 6.45% 96.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3383887 2.48% 99.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 920551 0.68% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24929928 18.27% 18.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19932793 14.61% 32.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20578448 15.08% 47.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18152288 13.31% 61.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 24038629 17.62% 78.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15699021 11.51% 90.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8799073 6.45% 96.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3376437 2.47% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 920120 0.67% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 136360129 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 136426737 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8941 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4699 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8934 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4692 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -417,22 +417,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 46063 0.26% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 46301 0.26% 0.34% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7630 0.04% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 434 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7704 0.04% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 463 0.00% 0.38% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 190949 1.08% 1.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 4204 0.02% 1.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 241086 1.36% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 190616 1.07% 1.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 3949 0.02% 1.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241166 1.36% 2.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9286535 52.36% 55.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7946359 44.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9286471 52.35% 55.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7950501 44.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 126344065 33.78% 33.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2175771 0.58% 34.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 126356667 33.79% 33.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2175742 0.58% 34.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.37% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.37% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.37% # Type of FU issued @@ -451,93 +451,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.37% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6778681 1.81% 36.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6779199 1.81% 36.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8473226 2.27% 38.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3428816 0.92% 39.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1595959 0.43% 39.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20861053 5.58% 45.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7172627 1.92% 47.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7127553 1.91% 49.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8471128 2.27% 38.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3427474 0.92% 39.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1595849 0.43% 39.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20859409 5.58% 45.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7172834 1.92% 47.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7127502 1.91% 49.19% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101561380 27.16% 76.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88276793 23.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101548323 27.15% 76.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88297215 23.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 373971213 # Type of FU issued -system.cpu.iq.rate 2.736105 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17736902 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047429 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 653872242 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 288125780 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 249960786 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 249376129 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 130313231 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118044740 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 263109864 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 128598251 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11095244 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 373986631 # Type of FU issued +system.cpu.iq.rate 2.734820 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17740799 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047437 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 653979183 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 288208067 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 249975124 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249362565 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 130269118 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118046236 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 263130568 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128596862 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11091317 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 8826197 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 108953 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14410 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8901271 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8812619 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 109039 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14268 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8925521 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 178209 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1806 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 177200 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1779 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5077163 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 281172 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 37033 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 384123288 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 853132 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 103474945 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 91276854 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11734 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 343 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 352 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14410 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1275078 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 370888 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1645966 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 370028321 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100269572 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3942892 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 5078484 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 284505 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 35417 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 384139745 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 871852 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 103461367 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 91301104 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11754 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 311 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 371 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14268 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1284870 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 366093 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1650963 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 370046005 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100262370 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3940626 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1565 # number of nop insts executed -system.cpu.iew.exec_refs 187470029 # number of memory reference insts executed -system.cpu.iew.exec_branches 32001457 # Number of branches executed -system.cpu.iew.exec_stores 87200457 # Number of stores executed -system.cpu.iew.exec_rate 2.707257 # Inst execution rate -system.cpu.iew.wb_sent 368660932 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 368005526 # cumulative count of insts written-back -system.cpu.iew.wb_producers 182984682 # num instructions producing a value -system.cpu.iew.wb_consumers 363667286 # num instructions consuming a value +system.cpu.iew.exec_nop 1545 # number of nop insts executed +system.cpu.iew.exec_refs 187486507 # number of memory reference insts executed +system.cpu.iew.exec_branches 32007235 # Number of branches executed +system.cpu.iew.exec_stores 87224137 # Number of stores executed +system.cpu.iew.exec_rate 2.706003 # Inst execution rate +system.cpu.iew.wb_sent 368676629 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 368021360 # cumulative count of insts written-back +system.cpu.iew.wb_producers 182960102 # num instructions producing a value +system.cpu.iew.wb_consumers 363631500 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.692458 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.503165 # average fanout of values written-back +system.cpu.iew.wb_rate 2.691198 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.503147 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 35058333 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 35074746 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1569963 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 131282966 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.658875 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.659705 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1576251 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 131348253 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.657554 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.659541 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 34515611 26.29% 26.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 28430867 21.66% 47.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13310132 10.14% 58.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11454615 8.73% 66.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13758236 10.48% 77.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7411224 5.65% 82.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3878786 2.95% 85.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3899655 2.97% 88.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14623840 11.14% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34568937 26.32% 26.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 28443468 21.66% 47.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13309150 10.13% 58.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11454276 8.72% 66.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13766870 10.48% 77.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7405227 5.64% 82.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3876233 2.95% 85.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3903284 2.97% 88.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14620808 11.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 131282966 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 131348253 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037337 # Number of instructions committed system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -548,220 +548,220 @@ system.cpu.commit.branches 30563497 # Nu system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14623840 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14620808 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 500779997 # The number of ROB reads -system.cpu.rob.rob_writes 773327958 # The number of ROB writes -system.cpu.timesIdled 6728 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320016 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 500864729 # The number of ROB reads +system.cpu.rob.rob_writes 773362160 # The number of ROB writes +system.cpu.timesIdled 6666 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 323275 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273036725 # Number of Instructions Simulated system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated -system.cpu.cpi 0.500593 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.500593 # CPI: Total CPI of All Threads -system.cpu.ipc 1.997633 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.997633 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1768864956 # number of integer regfile reads -system.cpu.int_regfile_writes 232856502 # number of integer regfile writes -system.cpu.fp_regfile_reads 188105910 # number of floating regfile reads -system.cpu.fp_regfile_writes 132495512 # number of floating regfile writes -system.cpu.misc_regfile_reads 566780330 # number of misc regfile reads +system.cpu.cpi 0.500848 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.500848 # CPI: Total CPI of All Threads +system.cpu.ipc 1.996612 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.996612 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1768925077 # number of integer regfile reads +system.cpu.int_regfile_writes 232843327 # number of integer regfile writes +system.cpu.fp_regfile_reads 188113453 # number of floating regfile reads +system.cpu.fp_regfile_writes 132483580 # number of floating regfile writes +system.cpu.misc_regfile_reads 566770577 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.toL2Bus.throughput 20129917 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 17615 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 17615 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1040 # Transaction distribution +system.cpu.toL2Bus.throughput 20110273 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 17610 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 17610 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1037 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2840 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2840 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 31680 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 10272 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 41952 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1013504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 361664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 1375168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 1375168 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 512 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 11790000 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadExReq 2838 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2838 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 31674 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 10263 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 41937 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1013376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 361280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 1374656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 1374656 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 384 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 11782000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 23771988 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24379238 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6938461 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7509966 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.replacements 13951 # number of replacements -system.cpu.icache.tagsinuse 1844.969918 # Cycle average of tags in use -system.cpu.icache.total_refs 37505309 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15840 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2367.759407 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1844.969918 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.900864 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.900864 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 37505309 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37505309 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37505309 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37505309 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37505309 # number of overall hits -system.cpu.icache.overall_hits::total 37505309 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17311 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17311 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17311 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17311 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17311 # number of overall misses -system.cpu.icache.overall_misses::total 17311 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 438177497 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 438177497 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 438177497 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 438177497 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 438177497 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 438177497 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37522620 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37522620 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37522620 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37522620 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37522620 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37522620 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 13946 # number of replacements +system.cpu.icache.tags.tagsinuse 1848.498389 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 37543488 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15836 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2370.768376 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1848.498389 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.902587 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.902587 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37543488 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37543488 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37543488 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37543488 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37543488 # number of overall hits +system.cpu.icache.overall_hits::total 37543488 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17326 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17326 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17326 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17326 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17326 # number of overall misses +system.cpu.icache.overall_misses::total 17326 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 439962484 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 439962484 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 439962484 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 439962484 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 439962484 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 439962484 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37560814 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37560814 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37560814 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37560814 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37560814 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37560814 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000461 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000461 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000461 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000461 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000461 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000461 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25312.084628 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25312.084628 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25312.084628 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25312.084628 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25312.084628 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25312.084628 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 919 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25393.194275 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25393.194275 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25393.194275 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25393.194275 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25393.194275 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25393.194275 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 913 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 39.956522 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 41.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1467 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1467 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1467 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1467 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1467 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1467 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15844 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15844 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15844 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15844 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15844 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15844 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 350210509 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 350210509 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 350210509 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 350210509 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 350210509 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 350210509 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1486 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1486 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1486 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1486 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1486 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1486 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15840 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15840 # 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mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994014 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994014 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191273 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922793 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.356238 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191273 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922793 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.356238 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55504.044239 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56894.203911 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55950.291414 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10300.800000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10300.800000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54533.209352 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54533.209352 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55504.044239 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55327.790834 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55401.084569 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55504.044239 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55327.790834 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55401.084569 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994010 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994010 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191613 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923177 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.356521 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191613 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923177 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.356521 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54944.133158 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56670.272156 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55497.873293 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10201 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10201 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54420.684155 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54420.684155 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54944.133158 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55178.479079 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55080.920692 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54944.133158 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55178.479079 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55080.920692 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1417 # number of replacements -system.cpu.dcache.tagsinuse 3105.227160 # Cycle average of tags in use -system.cpu.dcache.total_refs 170865642 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4611 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37056.092388 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3105.227160 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.758112 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.758112 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88812489 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88812489 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82031226 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82031226 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11012 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11012 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 1414 # number of replacements +system.cpu.dcache.tags.tagsinuse 3101.863625 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 170862922 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4608 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37079.627170 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3101.863625 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.757291 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.757291 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 88809743 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88809743 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82031242 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82031242 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11022 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11022 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 170843715 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 170843715 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 170843715 # number of overall hits -system.cpu.dcache.overall_hits::total 170843715 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3995 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3995 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 21439 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 21439 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 170840985 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 170840985 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 170840985 # number of overall hits +system.cpu.dcache.overall_hits::total 170840985 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3962 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3962 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 21423 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 21423 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25434 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25434 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25434 # number of overall misses -system.cpu.dcache.overall_misses::total 25434 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 218203000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 218203000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1190820596 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1190820596 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 155000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 155000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1409023596 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1409023596 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1409023596 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1409023596 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88816484 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88816484 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 25385 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25385 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25385 # number of overall misses +system.cpu.dcache.overall_misses::total 25385 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 221925207 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 221925207 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1196433403 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1196433403 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 157000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 157000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1418358610 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1418358610 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1418358610 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1418358610 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88813705 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88813705 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11014 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11014 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11024 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11024 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 170869149 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 170869149 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 170869149 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 170869149 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 170866370 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 170866370 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 170866370 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 170866370 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000261 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000261 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000182 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000182 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000181 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000181 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000149 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000149 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000149 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000149 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54619.023780 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54619.023780 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55544.596110 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55544.596110 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 77500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 77500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55399.213494 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55399.213494 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55399.213494 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55399.213494 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 24937 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1182 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 461 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.093275 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 90.923077 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56013.429329 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56013.429329 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55848.079307 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55848.079307 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 78500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55873.886547 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55873.886547 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55873.886547 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55873.886547 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 25209 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1225 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 407 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 61.938575 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 102.083333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1040 # number of writebacks -system.cpu.dcache.writebacks::total 1040 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2223 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2223 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18595 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18595 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1037 # number of writebacks +system.cpu.dcache.writebacks::total 1037 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2191 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2191 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18581 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18581 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20818 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20818 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20818 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20818 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1772 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1772 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2844 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2844 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4616 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4616 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4616 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4616 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 106478039 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 106478039 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 191753000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 191753000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298231039 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 298231039 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298231039 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 298231039 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 20772 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20772 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20772 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20772 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1771 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1771 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2842 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2842 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4613 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4613 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4613 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4613 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 106433039 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 106433039 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 191658495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 191658495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298091534 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 298091534 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298091534 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 298091534 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -949,14 +949,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60089.186795 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60089.186795 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67423.699015 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67423.699015 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64608.110702 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 64608.110702 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64608.110702 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 64608.110702 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60097.706945 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60097.706945 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67437.894089 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67437.894089 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64619.885974 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 64619.885974 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64619.885974 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 64619.885974 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 03f82082e..e8172a215 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -107,15 +107,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 1051668684 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 13796 # number of replacements -system.cpu.icache.tagsinuse 1765.993223 # Cycle average of tags in use -system.cpu.icache.total_refs 348644747 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 22344.725181 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1765.993223 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.862301 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.862301 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 13796 # number of replacements +system.cpu.icache.tags.tagsinuse 1765.993223 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 348644747 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22344.725181 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1765.993223 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.862301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.862301 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits @@ -185,19 +185,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3487.723791 # Cycle average of tags in use -system.cpu.l2cache.total_refs 13310 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4882 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.726342 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 341.616093 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2408.399470 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 737.708228 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.106437 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 3487.723791 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 341.616093 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.399470 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 737.708228 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.106437 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits @@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1332 # number of replacements -system.cpu.dcache.tagsinuse 3078.412981 # Cycle average of tags in use -system.cpu.dcache.total_refs 176641599 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4478 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 39446.538410 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.751566 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1332 # number of replacements +system.cpu.dcache.tags.tagsinuse 3078.412981 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 176641599 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 39446.538410 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.751566 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits |