diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
| commit | 55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch) | |
| tree | 6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/long/se/30.eon | |
| parent | ee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff) | |
| download | gem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz | |
stats: Update to match classic memory changes
Diffstat (limited to 'tests/long/se/30.eon')
7 files changed, 2334 insertions, 2302 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index b65c3962a..6b30c3cf1 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.233526 # Number of seconds simulated -sim_ticks 233525789500 # Number of ticks simulated -final_tick 233525789500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.233534 # Number of seconds simulated +sim_ticks 233533887500 # Number of ticks simulated +final_tick 233533887500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 279317 # Simulator instruction rate (inst/s) -host_op_rate 279317 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 163615265 # Simulator tick rate (ticks/s) -host_mem_usage 255720 # Number of bytes of host memory used -host_seconds 1427.29 # Real time elapsed on the host +host_inst_rate 225573 # Simulator instruction rate (inst/s) +host_op_rate 225573 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 132138421 # Simulator tick rate (ticks/s) +host_mem_usage 260868 # Number of bytes of host memory used +host_seconds 1767.34 # Real time elapsed on the host sim_insts 398664651 # Number of instructions simulated sim_ops 398664651 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 249280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory system.physmem.bytes_read::total 503872 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 249280 # Nu system.physmem.num_reads::cpu.inst 3895 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1067462 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1090209 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2157672 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1067462 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1067462 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1067462 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1090209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2157672 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1067425 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1090172 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2157597 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1067425 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1067425 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1067425 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1090172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2157597 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7873 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7873 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 233525688500 # Total gap between requests +system.physmem.totGap 233533785500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6857 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 948 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6853 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 951 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 69 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1541 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 326.852693 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 195.480715 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 331.694198 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 535 34.72% 34.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 344 22.32% 57.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 186 12.07% 69.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 104 6.75% 75.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 66 4.28% 80.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 53 3.44% 83.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 28 1.82% 85.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 39 2.53% 87.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 186 12.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1541 # Bytes accessed per row activation -system.physmem.totQLat 52273750 # Total ticks spent queuing -system.physmem.totMemAccLat 199892500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1544 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 326.051813 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 195.846863 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.937998 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 532 34.46% 34.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 344 22.28% 56.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 193 12.50% 69.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 103 6.67% 75.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 73 4.73% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 45 2.91% 83.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 32 2.07% 85.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 36 2.33% 87.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 186 12.05% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1544 # Bytes accessed per row activation +system.physmem.totQLat 53440000 # Total ticks spent queuing +system.physmem.totMemAccLat 201058750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6639.62 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6787.76 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25389.62 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25537.76 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s @@ -217,75 +217,75 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6330 # Number of row buffer hits during reads +system.physmem.readRowHits 6327 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.40 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.36 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 29661588.78 # Average gap between requests -system.physmem.pageHitRate 80.40 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6804000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3712500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 34327800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 29662617.24 # Average gap between requests +system.physmem.pageHitRate 80.36 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6758640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3687750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 34296600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15252731520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5982776145 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 134867232750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 156147584715 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.653337 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 224361889750 # Time in different power states -system.physmem_0.memoryStateTime::REF 7797920000 # Time in different power states +system.physmem_0.refreshEnergy 15253240080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6038642700 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 134822908500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 156159534270 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.682165 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 224288059000 # Time in different power states +system.physmem_0.memoryStateTime::REF 7798180000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1365674000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1447046250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4845960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2644125 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 4914000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2681250 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 27058200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15252731520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5743132470 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 135077446500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 156107858775 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.483223 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 224713608000 # Time in different power states -system.physmem_1.memoryStateTime::REF 7797920000 # Time in different power states +system.physmem_1.refreshEnergy 15253240080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5739994620 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 135084870750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 156112758900 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.481917 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 224725904750 # Time in different power states +system.physmem_1.memoryStateTime::REF 7798180000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1013955750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1009185250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 45912937 # Number of BP lookups -system.cpu.branchPred.condPredicted 26702744 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 45912940 # Number of BP lookups +system.cpu.branchPred.condPredicted 26702743 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 565787 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25186730 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 25186733 # Number of BTB lookups system.cpu.branchPred.BTBHits 18811780 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 74.689251 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 74.689242 # BTB Hit Percentage system.cpu.branchPred.usedRAS 8285572 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2249877 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 2249880 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 2235903 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 13974 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 13977 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 111495 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 95338457 # DTB read hits +system.cpu.dtb.read_hits 95338456 # DTB read hits system.cpu.dtb.read_misses 116 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 95338573 # DTB read accesses +system.cpu.dtb.read_accesses 95338572 # DTB read accesses system.cpu.dtb.write_hits 73578378 # DTB write hits system.cpu.dtb.write_misses 849 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 73579227 # DTB write accesses -system.cpu.dtb.data_hits 168916835 # DTB hits +system.cpu.dtb.data_hits 168916834 # DTB hits system.cpu.dtb.data_misses 965 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168917800 # DTB accesses -system.cpu.itb.fetch_hits 96959231 # ITB hits +system.cpu.dtb.data_accesses 168917799 # DTB accesses +system.cpu.itb.fetch_hits 96959232 # ITB hits system.cpu.itb.fetch_misses 1239 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 96960470 # ITB accesses +system.cpu.itb.fetch_accesses 96960471 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,16 +299,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 233525789500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 467051579 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 233533887500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 467067775 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664651 # Number of instructions committed system.cpu.committedOps 398664651 # Number of ops (including micro ops) committed system.cpu.discardedOps 2289293 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.171540 # CPI: cycles per instruction -system.cpu.ipc 0.853577 # IPC: instructions per cycle +system.cpu.cpi 1.171581 # CPI: cycles per instruction +system.cpu.ipc 0.853548 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction system.cpu.op_class_0::IntAlu 141652555 35.53% 41.33% # Class of committed instruction system.cpu.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction @@ -344,18 +344,18 @@ system.cpu.op_class_0::MemWrite 73520764 18.44% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 398664651 # Class of committed instruction -system.cpu.tickCycles 455740556 # Number of cycles that the object actually ticked -system.cpu.idleCycles 11311023 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 455740572 # Number of cycles that the object actually ticked +system.cpu.idleCycles 11327203 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.966637 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 167817023 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3291.924590 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 167817024 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40292.202401 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40292.202641 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3291.966637 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803703 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803703 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3291.924590 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803693 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803693 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id @@ -365,31 +365,31 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 3113 system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 335652191 # Number of tag accesses system.cpu.dcache.tags.data_accesses 335652191 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 94302223 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94302223 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73514800 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73514800 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 167817023 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 167817023 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 167817023 # number of overall hits -system.cpu.dcache.overall_hits::total 167817023 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 73514801 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73514801 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 167817024 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 167817024 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 167817024 # number of overall hits +system.cpu.dcache.overall_hits::total 167817024 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1061 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1061 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5929 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5929 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 6990 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6990 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 6990 # number of overall misses -system.cpu.dcache.overall_misses::total 6990 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 77930500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 77930500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 429190000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 429190000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 507120500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 507120500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 507120500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 507120500 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 5928 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5928 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 6989 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6989 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6989 # number of overall misses +system.cpu.dcache.overall_misses::total 6989 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 80682500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 80682500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 434084500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 434084500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 514767000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 514767000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 514767000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 514767000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94303284 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94303284 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -406,14 +406,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73450.047125 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73450.047125 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72388.261090 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72388.261090 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72549.427754 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72549.427754 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72549.427754 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72549.427754 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76043.826579 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 76043.826579 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73226.130229 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73226.130229 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73653.884676 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73653.884676 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73653.884676 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73653.884676 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -424,12 +424,12 @@ system.cpu.dcache.writebacks::writebacks 654 # nu system.cpu.dcache.writebacks::total 654 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 92 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2733 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2733 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2825 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2825 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2825 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2825 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2732 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2732 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2824 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2824 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2824 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2824 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses @@ -438,14 +438,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4165 system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70280500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 70280500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 239912500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 239912500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 310193000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 310193000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 310193000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 310193000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 72936500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 72936500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 242391000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 242391000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 315327500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 315327500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 315327500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 315327500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -454,69 +454,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72528.895769 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72528.895769 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75066.489362 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75066.489362 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74476.110444 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74476.110444 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74476.110444 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74476.110444 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75269.865841 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75269.865841 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75841.989987 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75841.989987 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75708.883553 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75708.883553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75708.883553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75708.883553 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 3193 # number of replacements -system.cpu.icache.tags.tagsinuse 1919.750364 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 96954060 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1919.733373 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 96954061 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 5171 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18749.576484 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 18749.576678 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1919.750364 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.937378 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.937378 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1919.733373 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.937370 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.937370 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1287 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 193923633 # Number of tag accesses -system.cpu.icache.tags.data_accesses 193923633 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 96954060 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 96954060 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 96954060 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 96954060 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 96954060 # number of overall hits -system.cpu.icache.overall_hits::total 96954060 # number of overall hits +system.cpu.icache.tags.tag_accesses 193923635 # Number of tag accesses +system.cpu.icache.tags.data_accesses 193923635 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 96954061 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 96954061 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 96954061 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 96954061 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 96954061 # number of overall hits +system.cpu.icache.overall_hits::total 96954061 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 5171 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 5171 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 5171 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 5171 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5171 # number of overall misses system.cpu.icache.overall_misses::total 5171 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 318040500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 318040500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 318040500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 318040500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 318040500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 318040500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 96959231 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 96959231 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 96959231 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 96959231 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 96959231 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 96959231 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 321948500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 321948500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 321948500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 321948500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 321948500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 321948500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 96959232 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 96959232 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 96959232 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 96959232 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 96959232 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 96959232 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000053 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000053 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000053 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61504.641269 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61504.641269 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61504.641269 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61504.641269 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61504.641269 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61504.641269 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62260.394508 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62260.394508 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62260.394508 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62260.394508 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62260.394508 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62260.394508 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -531,47 +531,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 5171 system.cpu.icache.demand_mshr_misses::total 5171 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 5171 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 5171 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312869500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 312869500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312869500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 312869500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312869500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 312869500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 316777500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 316777500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 316777500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 316777500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 316777500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 316777500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60504.641269 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60504.641269 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60504.641269 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60504.641269 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60504.641269 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60504.641269 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61260.394508 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61260.394508 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61260.394508 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61260.394508 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61260.394508 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61260.394508 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4425.384656 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4801 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5273 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.910487 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 7128.160045 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5427 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 7873 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.689318 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 372.164909 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.179805 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 642.039942 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011358 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104101 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.019594 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.135052 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5273 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 613 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4442 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160919 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 114871 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 114871 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.137560 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3717.022485 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104100 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.113435 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.217534 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 7873 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 503 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7185 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.240265 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 114273 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 114273 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 654 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 654 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 3193 # number of WritebackClean hits @@ -600,18 +599,18 @@ system.cpu.l2cache.demand_misses::total 7873 # nu system.cpu.l2cache.overall_misses::cpu.inst 3895 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3978 # number of overall misses system.cpu.l2cache.overall_misses::total 7873 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 234589500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 234589500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 291713500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 291713500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 67354500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 67354500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 291713500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 301944000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 593657500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 291713500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 301944000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 593657500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 237071000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 237071000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 295621500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 295621500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 70008000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 70008000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 295621500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 307079000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 602700500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 295621500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 307079000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 602700500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 654 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 654 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 3193 # number of WritebackClean accesses(hits+misses) @@ -640,18 +639,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.843295 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.753239 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955102 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.843295 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74781.479120 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74781.479120 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74894.351733 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74894.351733 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80088.585018 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80088.585018 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74894.351733 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75903.469080 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75404.229646 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74894.351733 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75903.469080 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75404.229646 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75572.521517 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75572.521517 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75897.689345 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75897.689345 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83243.757432 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83243.757432 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75897.689345 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77194.318753 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76552.838816 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75897.689345 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77194.318753 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76552.838816 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -670,18 +669,18 @@ system.cpu.l2cache.demand_mshr_misses::total 7873 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3895 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3978 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7873 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 203219500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 203219500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 252763500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 252763500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 58944500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 58944500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 252763500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 262164000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 514927500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 252763500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 262164000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 514927500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 205701000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 205701000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 256671500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 256671500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 61598000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 61598000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 256671500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 267299000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 523970500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 256671500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 267299000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 523970500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.753239 # mshr miss rate for ReadCleanReq accesses @@ -694,25 +693,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.843295 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.753239 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.843295 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64781.479120 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64781.479120 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64894.351733 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64894.351733 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70088.585018 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70088.585018 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64894.351733 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65903.469080 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65404.229646 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64894.351733 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65903.469080 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65404.229646 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65572.521517 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65572.521517 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65897.689345 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65897.689345 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73243.757432 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73243.757432 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65897.689345 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67194.318753 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66552.838816 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65897.689345 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67194.318753 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66552.838816 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 13300 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 3964 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 6138 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 654 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 3193 # Transaction distribution @@ -744,9 +743,15 @@ system.cpu.toL2Bus.reqLayer0.occupancy 10497000 # La system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 7756500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6247999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6247500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 7873 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4736 # Transaction distribution system.membus.trans_dist::ReadExReq 3137 # Transaction distribution system.membus.trans_dist::ReadExResp 3137 # Transaction distribution @@ -767,9 +772,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7873 # Request fanout histogram -system.membus.reqLayer0.occupancy 9219000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9223000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 41801750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 41799750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 81cd1b880..71e9e3432 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.064189 # Number of seconds simulated -sim_ticks 64188759000 # Number of ticks simulated -final_tick 64188759000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.064159 # Number of seconds simulated +sim_ticks 64159445000 # Number of ticks simulated +final_tick 64159445000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 260398 # Simulator instruction rate (inst/s) -host_op_rate 260398 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44504184 # Simulator tick rate (ticks/s) -host_mem_usage 257256 # Number of bytes of host memory used -host_seconds 1442.31 # Real time elapsed on the host +host_inst_rate 223776 # Simulator instruction rate (inst/s) +host_op_rate 223776 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38227708 # Simulator tick rate (ticks/s) +host_mem_usage 261380 # Number of bytes of host memory used +host_seconds 1678.35 # Real time elapsed on the host sim_insts 375574794 # Number of instructions simulated sim_ops 375574794 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 220736 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 255360 # Number of bytes read from this memory -system.physmem.bytes_read::total 476160 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 220800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 220800 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3450 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 476096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 220736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220736 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3449 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3990 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7440 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3439855 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3978267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7418121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3439855 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3439855 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3439855 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3978267 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7418121 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7440 # Number of read requests accepted +system.physmem.num_reads::total 7439 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 3440429 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3980084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7420513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3440429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3440429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3440429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3980084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7420513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7439 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7440 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7439 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 476160 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 476096 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 476160 # Total read bytes from the system interface side +system.physmem.bytesReadSys 476096 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -56,7 +56,7 @@ system.physmem.perBankRdBursts::10 339 # Pe system.physmem.perBankRdBursts::11 305 # Per bank write bursts system.physmem.perBankRdBursts::12 414 # Per bank write bursts system.physmem.perBankRdBursts::13 540 # Per bank write bursts -system.physmem.perBankRdBursts::14 454 # Per bank write bursts +system.physmem.perBankRdBursts::14 453 # Per bank write bursts system.physmem.perBankRdBursts::15 380 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 64188663500 # Total gap between requests +system.physmem.totGap 64159334500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7440 # Read request sizes (log2) +system.physmem.readPktSize::6 7439 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,11 +91,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1868 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 921 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1861 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 920 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1358 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 347.287187 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 206.380841 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 346.777138 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 443 32.62% 32.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 304 22.39% 55.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 160 11.78% 66.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 96 7.07% 73.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 54 3.98% 77.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 38 2.80% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 38 2.80% 83.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 25 1.84% 85.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 200 14.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1358 # Bytes accessed per row activation -system.physmem.totQLat 65294500 # Total ticks spent queuing -system.physmem.totMemAccLat 204794500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37200000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8776.14 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1349 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 352.640474 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 209.024877 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 349.175025 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 440 32.62% 32.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 302 22.39% 55.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 154 11.42% 66.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 83 6.15% 72.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 53 3.93% 76.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 50 3.71% 80.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 36 2.67% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 35 2.59% 85.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 196 14.53% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1349 # Bytes accessed per row activation +system.physmem.totQLat 63577500 # Total ticks spent queuing +system.physmem.totMemAccLat 203058750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37195000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8546.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27526.14 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27296.51 # Average memory access latency per DRAM burst system.physmem.avgRdBW 7.42 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 7.42 # Average system read bandwidth in MiByte/s @@ -217,75 +217,75 @@ system.physmem.busUtilRead 0.06 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6069 # Number of row buffer hits during reads +system.physmem.readRowHits 6088 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.84 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8627508.53 # Average gap between requests -system.physmem.pageHitRate 81.57 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5843880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3188625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 32221800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 8624725.70 # Average gap between requests +system.physmem.pageHitRate 81.84 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5821200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3176250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 32416800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4192060080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1996054785 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 36758466000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 42987835170 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.776911 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 61149211250 # Time in different power states -system.physmem_0.memoryStateTime::REF 2143180000 # Time in different power states +system.physmem_0.refreshEnergy 4190534400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1995176700 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 36745221000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 42972346350 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.779347 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 61126318750 # Time in different power states +system.physmem_0.memoryStateTime::REF 2142400000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 890802750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 890255000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4399920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2400750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 25217400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 4377240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2388375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 25560600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4192060080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1854861795 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 36882319500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 42961259445 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.362844 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 61355238000 # Time in different power states -system.physmem_1.memoryStateTime::REF 2143180000 # Time in different power states +system.physmem_1.refreshEnergy 4190534400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1859740425 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 36864024750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 42946625790 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.378459 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 61324552000 # Time in different power states +system.physmem_1.memoryStateTime::REF 2142400000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 684265000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 692021750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 47858697 # Number of BP lookups -system.cpu.branchPred.condPredicted 27887013 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 573168 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 23334340 # Number of BTB lookups -system.cpu.branchPred.BTBHits 19575055 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 47856205 # Number of BP lookups +system.cpu.branchPred.condPredicted 27886274 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 572784 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 23348714 # Number of BTB lookups +system.cpu.branchPred.BTBHits 19574502 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.889474 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 8688210 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1446 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2339152 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2308305 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 30847 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 111425 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 83.835461 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 8687459 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1418 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 2338624 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2308001 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 30623 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 111239 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 98833092 # DTB read hits -system.cpu.dtb.read_misses 28443 # DTB read misses -system.cpu.dtb.read_acv 867 # DTB read access violations -system.cpu.dtb.read_accesses 98861535 # DTB read accesses -system.cpu.dtb.write_hits 75500788 # DTB write hits +system.cpu.dtb.read_hits 98829712 # DTB read hits +system.cpu.dtb.read_misses 28367 # DTB read misses +system.cpu.dtb.read_acv 845 # DTB read access violations +system.cpu.dtb.read_accesses 98858079 # DTB read accesses +system.cpu.dtb.write_hits 75499203 # DTB write hits system.cpu.dtb.write_misses 1454 # DTB write misses system.cpu.dtb.write_acv 3 # DTB write access violations -system.cpu.dtb.write_accesses 75502242 # DTB write accesses -system.cpu.dtb.data_hits 174333880 # DTB hits -system.cpu.dtb.data_misses 29897 # DTB misses -system.cpu.dtb.data_acv 870 # DTB access violations -system.cpu.dtb.data_accesses 174363777 # DTB accesses -system.cpu.itb.fetch_hits 46960311 # ITB hits -system.cpu.itb.fetch_misses 430 # ITB misses -system.cpu.itb.fetch_acv 5 # ITB acv -system.cpu.itb.fetch_accesses 46960741 # ITB accesses +system.cpu.dtb.write_accesses 75500657 # DTB write accesses +system.cpu.dtb.data_hits 174328915 # DTB hits +system.cpu.dtb.data_misses 29821 # DTB misses +system.cpu.dtb.data_acv 848 # DTB access violations +system.cpu.dtb.data_accesses 174358736 # DTB accesses +system.cpu.itb.fetch_hits 46955913 # ITB hits +system.cpu.itb.fetch_misses 420 # ITB misses +system.cpu.itb.fetch_acv 7 # ITB acv +system.cpu.itb.fetch_accesses 46956333 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,141 +299,141 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 128377521 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 128318893 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 47431154 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 424848239 # Number of instructions fetch has processed -system.cpu.fetch.Branches 47858697 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 30571570 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80009353 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1247564 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 47425719 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 424811206 # Number of instructions fetch has processed +system.cpu.fetch.Branches 47856205 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 30569962 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 79950349 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1246202 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 13 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 284 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 13513 # Number of stall cycles due to pending traps +system.cpu.fetch.MiscStallCycles 270 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 13187 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 60 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 46960311 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 225671 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 128078159 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.317101 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.349648 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 46955913 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 225768 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 128012699 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.318508 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.349839 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 53091522 41.45% 41.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4331488 3.38% 44.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6713646 5.24% 50.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5106781 3.99% 54.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 10967794 8.56% 62.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 7526071 5.88% 68.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5305239 4.14% 72.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1848793 1.44% 74.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 33186825 25.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 53041219 41.43% 41.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4325218 3.38% 44.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6711253 5.24% 50.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5104898 3.99% 54.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 10968142 8.57% 62.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 7524114 5.88% 68.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5300788 4.14% 72.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1845614 1.44% 74.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 33191453 25.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 128078159 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.372797 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.309366 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 42083889 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 13603478 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 67893810 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3877357 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 619625 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 8883159 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4198 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 421926458 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 13804 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 619625 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 43653235 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3048927 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 516546 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70101215 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10138611 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 419911173 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 439346 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2543427 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2848893 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 3543199 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 273983157 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 552185759 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 393726185 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 158459573 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 128012699 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.372947 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.310590 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 42125446 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 13481218 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 67948873 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3838220 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 618942 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 8882912 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4201 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 421902807 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 13825 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 618942 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 43678343 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3058028 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 517106 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70134710 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 10005570 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 419884966 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 437260 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2526892 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2765017 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 3520699 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 273968908 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 552151473 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 393698766 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 158452706 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532319 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14450838 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 14436589 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 37562 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 298 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 15867681 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 99739292 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 76524203 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 11895065 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9302116 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 392194254 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 15635470 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 99735139 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 76519296 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 11859955 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9294086 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 392181792 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 290 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 389210938 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 196221 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 16619749 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7681566 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 389203558 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 195886 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 16607287 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7664931 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 75 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 128078159 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.038855 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.181056 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 128012699 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.040351 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.180919 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17247166 13.47% 13.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19402738 15.15% 28.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22008781 17.18% 45.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17964276 14.03% 59.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 19060613 14.88% 74.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 13269746 10.36% 85.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8793023 6.87% 91.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6106038 4.77% 96.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4225778 3.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17224377 13.46% 13.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19358192 15.12% 28.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22001472 17.19% 45.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17955910 14.03% 59.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 19066405 14.89% 74.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 13282652 10.38% 85.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8794829 6.87% 91.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6104058 4.77% 96.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4224804 3.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 128078159 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 128012699 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 255592 1.41% 1.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 138975 0.77% 2.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 79489 0.44% 2.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 3727 0.02% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 3445589 19.00% 21.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1648341 9.09% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8051616 44.40% 75.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4508979 24.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 256922 1.42% 1.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 1.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 138470 0.76% 2.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 78848 0.44% 2.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 3339 0.02% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 3443164 19.01% 21.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1648895 9.10% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8039924 44.38% 75.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4505956 24.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 146987981 37.77% 37.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2128295 0.55% 38.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 146986421 37.77% 37.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2128250 0.55% 38.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 36418632 9.36% 47.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7354909 1.89% 49.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2800462 0.72% 50.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16556521 4.25% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1584140 0.41% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 36418938 9.36% 47.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7355017 1.89% 49.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2800646 0.72% 50.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16556809 4.25% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1584153 0.41% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.95% # Type of FU issued @@ -455,82 +455,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.95% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 99505104 25.57% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 75841313 19.49% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 99502900 25.57% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 75836843 19.49% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 389210938 # Type of FU issued -system.cpu.iq.rate 3.031769 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18132308 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.046587 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 592570653 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 242193331 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 227932630 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 332257911 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 166691582 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 158290719 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 234731368 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 172578297 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19373689 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 389203558 # Type of FU issued +system.cpu.iq.rate 3.033096 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18115520 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.046545 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 592493180 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 242176639 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 227925873 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 332238041 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 166682962 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 158291544 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 234723560 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172561937 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19352464 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4984806 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 93159 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 70985 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3003475 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4980653 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 92349 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 70589 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2998568 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 382536 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3859 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 383293 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3853 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 619625 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1856570 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 132026 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 415917767 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 108843 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 99739292 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 76524203 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 618942 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1854909 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 149633 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 415904338 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 108226 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 99735139 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 76519296 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 290 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 8227 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 123512 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 70985 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 411741 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 230567 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 642308 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 387626106 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 98862428 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1584832 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 7462 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 141873 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 70589 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 411438 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 230495 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 641933 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 387616397 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 98858950 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1587161 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 23723223 # number of nop insts executed -system.cpu.iew.exec_refs 174364706 # number of memory reference insts executed -system.cpu.iew.exec_branches 45864043 # Number of branches executed -system.cpu.iew.exec_stores 75502278 # Number of stores executed -system.cpu.iew.exec_rate 3.019424 # Inst execution rate -system.cpu.iew.wb_sent 386487511 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 386223349 # cumulative count of insts written-back -system.cpu.iew.wb_producers 192322376 # num instructions producing a value -system.cpu.iew.wb_consumers 273878502 # num instructions consuming a value -system.cpu.iew.wb_rate 3.008497 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.702218 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 17254297 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 23722256 # number of nop insts executed +system.cpu.iew.exec_refs 174359643 # number of memory reference insts executed +system.cpu.iew.exec_branches 45862472 # Number of branches executed +system.cpu.iew.exec_stores 75500693 # Number of stores executed +system.cpu.iew.exec_rate 3.020727 # Inst execution rate +system.cpu.iew.wb_sent 386480663 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 386217417 # cumulative count of insts written-back +system.cpu.iew.wb_producers 192328787 # num instructions producing a value +system.cpu.iew.wb_consumers 273868663 # num instructions consuming a value +system.cpu.iew.wb_rate 3.009825 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.702266 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 17240745 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 569011 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 125612042 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.173777 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.248518 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 568625 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 125549188 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.175366 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.248155 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 42074654 33.50% 33.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 17552788 13.97% 47.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 8725383 6.95% 54.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9055727 7.21% 61.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6223211 4.95% 66.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4119483 3.28% 69.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4738198 3.77% 73.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2406397 1.92% 75.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 30716201 24.45% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 42020703 33.47% 33.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 17522364 13.96% 47.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 8729636 6.95% 54.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9062074 7.22% 61.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6240745 4.97% 66.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4112376 3.28% 69.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 4753795 3.79% 73.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2410879 1.92% 75.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 30696616 24.45% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 125612042 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 125549188 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664569 # Number of instructions committed system.cpu.commit.committedOps 398664569 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -576,33 +576,33 @@ system.cpu.commit.op_class_0::MemWrite 73520728 18.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 398664569 # Class of committed instruction -system.cpu.commit.bw_lim_events 30716201 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 510811730 # The number of ROB reads -system.cpu.rob.rob_writes 834310252 # The number of ROB writes -system.cpu.timesIdled 3164 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 299362 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 30696616 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 510754909 # The number of ROB reads +system.cpu.rob.rob_writes 834280363 # The number of ROB writes +system.cpu.timesIdled 3150 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 306194 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574794 # Number of Instructions Simulated system.cpu.committedOps 375574794 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.341816 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.341816 # CPI: Total CPI of All Threads -system.cpu.ipc 2.925550 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.925550 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 385452871 # number of integer regfile reads -system.cpu.int_regfile_writes 165252221 # number of integer regfile writes -system.cpu.fp_regfile_reads 154536644 # number of floating regfile reads -system.cpu.fp_regfile_writes 102074619 # number of floating regfile writes +system.cpu.cpi 0.341660 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.341660 # CPI: Total CPI of All Threads +system.cpu.ipc 2.926886 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.926886 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 385442521 # number of integer regfile reads +system.cpu.int_regfile_writes 165246956 # number of integer regfile writes +system.cpu.fp_regfile_reads 154535424 # number of floating regfile reads +system.cpu.fp_regfile_writes 102076666 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 776 # number of replacements -system.cpu.dcache.tags.tagsinuse 3292.009184 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 152572889 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4176 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 36535.653496 # Average number of references to valid blocks. +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 779 # number of replacements +system.cpu.dcache.tags.tagsinuse 3291.925722 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 152589979 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4179 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 36513.514956 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3292.009184 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803713 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803713 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3291.925722 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803693 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803693 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3400 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id @@ -610,45 +610,45 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 211 system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.830078 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 305192990 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 305192990 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 79071847 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 79071847 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501036 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501036 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 305227185 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 305227185 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 79088959 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 79088959 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501014 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501014 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 152572883 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 152572883 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 152572883 # number of overall hits -system.cpu.dcache.overall_hits::total 152572883 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1826 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1826 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19692 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19692 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21518 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21518 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21518 # number of overall misses -system.cpu.dcache.overall_misses::total 21518 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 128481000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 128481000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1201737956 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1201737956 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1330218956 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1330218956 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1330218956 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1330218956 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 79073673 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 79073673 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 152589973 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 152589973 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 152589973 # number of overall hits +system.cpu.dcache.overall_hits::total 152589973 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1810 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1810 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19714 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19714 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21524 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21524 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21524 # number of overall misses +system.cpu.dcache.overall_misses::total 21524 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 128203000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 128203000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1194602455 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1194602455 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1322805455 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1322805455 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1322805455 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1322805455 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 79090769 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 79090769 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520728 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520728 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 152594401 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 152594401 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 152594401 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 152594401 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 152611497 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 152611497 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 152611497 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 152611497 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000268 # miss rate for WriteReq accesses @@ -657,258 +657,257 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000141 system.cpu.dcache.demand_miss_rate::total 0.000141 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000141 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000141 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70361.993428 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70361.993428 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61026.709120 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61026.709120 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61818.893763 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61818.893763 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61818.893763 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61818.893763 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 50592 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 80 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 740 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70830.386740 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70830.386740 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60596.654915 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60596.654915 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61457.231695 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61457.231695 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61457.231695 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61457.231695 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 49869 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 82 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 741 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 68.367568 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 80 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 655 # number of writebacks -system.cpu.dcache.writebacks::total 655 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 838 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 838 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16504 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16504 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17342 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17342 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17342 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17342 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 988 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 988 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3188 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3188 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4176 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4176 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4176 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4176 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 74762500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 74762500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 249321500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 249321500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 324084000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 324084000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 324084000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 324084000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 67.299595 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 82 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 658 # number of writebacks +system.cpu.dcache.writebacks::total 658 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 821 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 821 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16524 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16524 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17345 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17345 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17345 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17345 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 989 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 989 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3190 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3190 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4179 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4179 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4179 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4179 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76039500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 76039500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 251163000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 251163000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 327202500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 327202500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 327202500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 327202500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000013 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000013 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75670.546559 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75670.546559 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78206.242158 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78206.242158 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77606.321839 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77606.321839 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77606.321839 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77606.321839 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 2132 # number of replacements -system.cpu.icache.tags.tagsinuse 1831.246133 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 46954666 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4060 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11565.188670 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76885.237614 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76885.237614 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78734.482759 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78734.482759 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78296.841350 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78296.841350 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78296.841350 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78296.841350 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 2131 # number of replacements +system.cpu.icache.tags.tagsinuse 1829.791655 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 46950265 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4058 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11569.804091 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1831.246133 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.894163 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.894163 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1928 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1346 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 93924682 # Number of tag accesses -system.cpu.icache.tags.data_accesses 93924682 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 46954666 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 46954666 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 46954666 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 46954666 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 46954666 # number of overall hits -system.cpu.icache.overall_hits::total 46954666 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5645 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5645 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5645 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5645 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5645 # number of overall misses -system.cpu.icache.overall_misses::total 5645 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 370489499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 370489499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 370489499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 370489499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 370489499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 370489499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 46960311 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 46960311 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 46960311 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 46960311 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 46960311 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 46960311 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1829.791655 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.893453 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.893453 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1927 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 297 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1343 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.940918 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 93915884 # Number of tag accesses +system.cpu.icache.tags.data_accesses 93915884 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 46950265 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 46950265 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 46950265 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 46950265 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 46950265 # number of overall hits +system.cpu.icache.overall_hits::total 46950265 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5648 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5648 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5648 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5648 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5648 # number of overall misses +system.cpu.icache.overall_misses::total 5648 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 373323999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 373323999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 373323999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 373323999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 373323999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 373323999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 46955913 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 46955913 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 46955913 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 46955913 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 46955913 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 46955913 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000120 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000120 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000120 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000120 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000120 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000120 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65631.443578 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 65631.443578 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 65631.443578 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 65631.443578 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 65631.443578 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 65631.443578 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 496 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66098.441749 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 66098.441749 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 66098.441749 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 66098.441749 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 66098.441749 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 66098.441749 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 575 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 62 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 63.888889 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 2132 # number of writebacks -system.cpu.icache.writebacks::total 2132 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1585 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1585 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1585 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1585 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1585 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1585 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4060 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4060 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4060 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4060 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4060 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4060 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 275403500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 275403500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 275403500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 275403500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 275403500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 275403500 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 2131 # number of writebacks +system.cpu.icache.writebacks::total 2131 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1590 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1590 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1590 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1590 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1590 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1590 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4058 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4058 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4058 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4058 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4058 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4058 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 277954000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 277954000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 277954000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 277954000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 277954000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 277954000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67833.374384 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67833.374384 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67833.374384 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67833.374384 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67833.374384 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67833.374384 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68495.317891 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68495.317891 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68495.317891 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68495.317891 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68495.317891 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68495.317891 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4001.708243 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3078 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4847 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.635032 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 6688.615033 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3708 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 7439 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.498454 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 370.790492 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2968.908882 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 662.008869 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011316 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.090604 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.020203 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.122122 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 4847 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 137 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 533 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4032 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.147919 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 97187 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 97187 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 655 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 655 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 2132 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 2132 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 610 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 610 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 126 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 126 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 610 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 186 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 796 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 610 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 186 # number of overall hits -system.cpu.l2cache.overall_hits::total 796 # number of overall hits +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2966.248754 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3722.366279 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.090523 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.113598 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.204120 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 7439 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 426 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6758 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.227020 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 96615 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 96615 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 658 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 658 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 2131 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 2131 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 62 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 62 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 609 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 609 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 127 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 127 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 609 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 189 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 798 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 609 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 189 # number of overall hits +system.cpu.l2cache.overall_hits::total 798 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 3128 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 3128 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3450 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3450 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3449 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3449 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 862 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 862 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3450 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 3449 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 3990 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7440 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3450 # number of overall misses +system.cpu.l2cache.demand_misses::total 7439 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3449 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3990 # number of overall misses -system.cpu.l2cache.overall_misses::total 7440 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 243810500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 243810500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 262807000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 262807000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71863500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 71863500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 262807000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 315674000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 578481000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 262807000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 315674000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 578481000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 655 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 655 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 2132 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 2132 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 3188 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 3188 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4060 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 4060 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 988 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 988 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4060 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 4176 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 8236 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4060 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4176 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 8236 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981179 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.981179 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.849754 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.849754 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.872470 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.872470 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.849754 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.955460 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.903351 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.849754 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.955460 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.903351 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77944.533248 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77944.533248 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76175.942029 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76175.942029 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83368.329466 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83368.329466 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76175.942029 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79116.290727 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77752.822581 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76175.942029 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79116.290727 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77752.822581 # average overall miss latency +system.cpu.l2cache.overall_misses::total 7439 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 245628000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 245628000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 265369000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 265369000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 73132500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 73132500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 265369000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 318760500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 584129500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 265369000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 318760500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 584129500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 658 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 658 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 2131 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 2131 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 3190 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 3190 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4058 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 4058 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 989 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 989 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4058 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4179 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8237 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4058 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4179 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 8237 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.980564 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.980564 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.849926 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.849926 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.871587 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.871587 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.849926 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.954774 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.903120 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.849926 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.954774 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.903120 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78525.575448 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78525.575448 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76940.852421 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76940.852421 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84840.487239 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84840.487239 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76940.852421 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79889.849624 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78522.583681 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76940.852421 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79889.849624 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78522.583681 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -917,116 +916,122 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3128 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 3128 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3450 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3450 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3449 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3449 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 862 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 862 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3450 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3449 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 3990 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7440 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3450 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7439 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3449 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3990 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7440 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 212530500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 212530500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 228307000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 228307000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 63243500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 63243500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 228307000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 275774000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 504081000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 228307000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 275774000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 504081000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981179 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981179 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.849754 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.849754 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.872470 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.872470 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.849754 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955460 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.903351 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.849754 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955460 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.903351 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67944.533248 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67944.533248 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66175.942029 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66175.942029 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73368.329466 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73368.329466 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66175.942029 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69116.290727 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67752.822581 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66175.942029 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69116.290727 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67752.822581 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 11144 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2908 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_misses::total 7439 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 214348000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 214348000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 230879000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 230879000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 64512500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 64512500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 230879000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 278860500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 509739500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 230879000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 278860500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 509739500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980564 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980564 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.849926 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.849926 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.871587 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.871587 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.849926 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.954774 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.903120 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.849926 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.954774 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.903120 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68525.575448 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68525.575448 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66940.852421 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66940.852421 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74840.487239 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74840.487239 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66940.852421 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69889.849624 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68522.583681 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66940.852421 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69889.849624 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68522.583681 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 11147 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2910 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 5048 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 655 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2132 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 5047 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 658 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2131 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 121 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3188 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3188 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 4060 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 988 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10252 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9128 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 19380 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 396288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309184 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 705472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 3190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4058 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 989 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10247 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9137 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 19384 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 396096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 705664 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 8236 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 8237 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 8236 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 8237 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8236 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 8359000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 8237 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 8362500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6090499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6087499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6264000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6268500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4312 # Transaction distribution +system.membus.snoop_filter.tot_requests 7439 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 4311 # Transaction distribution system.membus.trans_dist::ReadExReq 3128 # Transaction distribution system.membus.trans_dist::ReadExResp 3128 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4312 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14880 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14880 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476160 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 476160 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 4311 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14878 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14878 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 476096 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 7440 # Request fanout histogram +system.membus.snoop_fanout::samples 7439 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7440 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7439 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7440 # Request fanout histogram -system.membus.reqLayer0.occupancy 9246500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7439 # Request fanout histogram +system.membus.reqLayer0.occupancy 9245500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 39238750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 39234750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 9532c68be..33645e09f 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.567385 # Number of seconds simulated -sim_ticks 567385356500 # Number of ticks simulated -final_tick 567385356500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.567393 # Number of seconds simulated +sim_ticks 567392530500 # Number of ticks simulated +final_tick 567392530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1154582 # Simulator instruction rate (inst/s) -host_op_rate 1154582 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1643217424 # Simulator tick rate (ticks/s) -host_mem_usage 254440 # Number of bytes of host memory used -host_seconds 345.29 # Real time elapsed on the host +host_inst_rate 646502 # Simulator instruction rate (inst/s) +host_op_rate 646502 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 920122456 # Simulator tick rate (ticks/s) +host_mem_usage 259072 # Number of bytes of host memory used +host_seconds 616.65 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory system.physmem.bytes_read::total 459136 # Number of bytes read from this memory @@ -22,15 +22,15 @@ system.physmem.bytes_inst_read::total 205120 # Nu system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7174 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 361518 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 447696 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 809214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 361518 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 361518 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 361518 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 447696 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 809214 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 361513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 447690 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 809203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 361513 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 361513 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 361513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 447690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 809203 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -65,8 +65,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 567385356500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1134770713 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 567392530500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1134785061 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664609 # Number of instructions committed @@ -85,7 +85,7 @@ system.cpu.num_mem_refs 168275276 # nu system.cpu.num_load_insts 94754511 # Number of load instructions system.cpu.num_store_insts 73520765 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1134770713 # Number of busy cycles +system.cpu.num_busy_cycles 1134785061 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 44587535 # Number of branches fetched @@ -124,16 +124,16 @@ system.cpu.op_class::MemWrite 73520765 18.44% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 398664665 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 764 # number of replacements -system.cpu.dcache.tags.tagsinuse 3288.807028 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3288.789389 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3288.807028 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.802931 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.802931 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3288.789389 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.802927 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.802927 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id @@ -143,7 +143,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 3112 system.cpu.dcache.tags.occ_task_id_percent::1024 0.827148 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 336554592 # Number of tag accesses system.cpu.dcache.tags.data_accesses 336554592 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 4152 # n system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses system.cpu.dcache.overall_misses::total 4152 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 52888500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 52888500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 195593000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 195593000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 248481500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 248481500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 248481500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 248481500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 53715500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 53715500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 198735000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 198735000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 252450500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 252450500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 252450500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 252450500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55672.105263 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55672.105263 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61084.634603 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61084.634603 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59846.218690 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59846.218690 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59846.218690 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59846.218690 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56542.631579 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56542.631579 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62065.896315 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62065.896315 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60802.143545 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60802.143545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60802.143545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60802.143545 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -208,14 +208,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51938500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 51938500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 192391000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 192391000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 244329500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 244329500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 244329500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 244329500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52765500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 52765500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 195533000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 195533000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 248298500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 248298500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 248298500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 248298500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -224,34 +224,34 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54672.105263 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54672.105263 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60084.634603 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60084.634603 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58846.218690 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58846.218690 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55542.631579 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55542.631579 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61065.896315 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61065.896315 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59802.143545 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 59802.143545 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59802.143545 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 59802.143545 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1769 # number of replacements -system.cpu.icache.tags.tagsinuse 1795.084430 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1795.076643 # Cycle average of tags in use system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1795.084430 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.876506 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.876506 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1795.076643 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.876502 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.876502 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1904 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 251 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1375 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.929688 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 797333005 # Number of tag accesses system.cpu.icache.tags.data_accesses 797333005 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits @@ -264,12 +264,12 @@ system.cpu.icache.demand_misses::cpu.inst 3673 # n system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses system.cpu.icache.overall_misses::total 3673 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 204815000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 204815000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 204815000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 204815000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 204815000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 204815000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 208020000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 208020000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 208020000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 208020000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 208020000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 208020000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses @@ -282,12 +282,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55762.319630 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55762.319630 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55762.319630 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55762.319630 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55762.319630 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55762.319630 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56634.903349 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56634.903349 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56634.903349 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56634.903349 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56634.903349 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56634.903349 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -302,48 +302,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3673 system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 201142000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 201142000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 201142000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 201142000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 201142000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 201142000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 204347000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 204347000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 204347000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 204347000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 204347000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 204347000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54762.319630 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54762.319630 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54762.319630 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54762.319630 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55634.903349 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55634.903349 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55634.903349 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 55634.903349 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55634.903349 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 55634.903349 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3772.330397 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2561 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4566 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.560885 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 6481.659208 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3184 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 7174 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.443825 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 371.516873 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.363420 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 630.450105 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011338 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084545 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.019240 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.115122 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 4566 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 77 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 497 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3787 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.139343 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 90632 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 90632 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.348214 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3711.310994 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084544 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.113260 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.197805 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 7174 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 392 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6535 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.218933 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 90038 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 90038 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 649 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 649 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1769 # number of WritebackClean hits @@ -372,18 +370,18 @@ system.cpu.l2cache.demand_misses::total 7174 # nu system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7174 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 186953000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 186953000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 190709000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 190709000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49213500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 49213500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 190709000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 236166500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 426875500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 190709000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 236166500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 426875500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 190095000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 190095000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 193914000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 193914000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50040500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 50040500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 193914000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 240135500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 434049500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 193914000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 240135500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 434049500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 649 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 649 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 1769 # number of WritebackClean accesses(hits+misses) @@ -412,18 +410,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.916805 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916805 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59501.273074 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59501.273074 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.588144 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.588144 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59508.464329 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59508.464329 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.588144 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59502.771479 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59503.136326 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.588144 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59502.771479 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59503.136326 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60501.273074 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60501.273074 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60503.588144 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60503.588144 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60508.464329 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60508.464329 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60503.588144 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60502.771479 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60503.136326 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60503.588144 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60502.771479 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60503.136326 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -442,18 +440,18 @@ system.cpu.l2cache.demand_mshr_misses::total 7174 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7174 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 155533000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 155533000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 158659000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 158659000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 40943500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 40943500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 158659000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 196476500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 355135500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 158659000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 196476500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 355135500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 158675000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158675000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 161864000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 161864000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 41770500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 41770500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 161864000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 200445500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 362309500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 161864000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 200445500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 362309500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981262 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadCleanReq accesses @@ -466,25 +464,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.916805 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.916805 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49501.273074 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49501.273074 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.588144 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.588144 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49508.464329 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49508.464329 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.588144 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49502.771479 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.136326 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.588144 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49502.771479 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.136326 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50501.273074 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50501.273074 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.588144 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.588144 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50508.464329 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50508.464329 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.588144 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50502.771479 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50503.136326 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.588144 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50502.771479 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50503.136326 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 10358 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2533 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 649 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1769 # Transaction distribution @@ -518,7 +516,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 5509500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6228000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 7174 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4032 # Transaction distribution system.membus.trans_dist::ReadExReq 3142 # Transaction distribution system.membus.trans_dist::ReadExResp 3142 # Transaction distribution diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 0b49d498f..a1a985a56 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.225030 # Number of seconds simulated -sim_ticks 225030243000 # Number of ticks simulated -final_tick 225030243000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.225041 # Number of seconds simulated +sim_ticks 225040911000 # Number of ticks simulated +final_tick 225040911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131394 # Simulator instruction rate (inst/s) -host_op_rate 157754 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 108291606 # Simulator tick rate (ticks/s) -host_mem_usage 275248 # Number of bytes of host memory used -host_seconds 2078.00 # Real time elapsed on the host +host_inst_rate 161529 # Simulator instruction rate (inst/s) +host_op_rate 193933 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 133133968 # Simulator tick rate (ticks/s) +host_mem_usage 280148 # Number of bytes of host memory used +host_seconds 1690.33 # Real time elapsed on the host sim_insts 273037855 # Number of instructions simulated sim_ops 327812212 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 219136 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 266432 # Number of bytes read from this memory system.physmem.bytes_read::total 485568 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 219136 # Nu system.physmem.num_reads::cpu.inst 3424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4163 # Number of read requests responded to by this memory system.physmem.num_reads::total 7587 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 973807 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1183983 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2157790 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 973807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 973807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 973807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1183983 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2157790 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 973761 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1183927 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2157688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 973761 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 973761 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 973761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1183927 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2157688 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7587 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7587 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 225029996000 # Total gap between requests +system.physmem.totGap 225040663000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1511 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 320.084712 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 189.611752 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 331.049486 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 552 36.53% 36.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 328 21.71% 58.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 178 11.78% 70.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 86 5.69% 75.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 72 4.77% 80.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 49 3.24% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 32 2.12% 85.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 31 2.05% 87.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 183 12.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1511 # Bytes accessed per row activation -system.physmem.totQLat 51456750 # Total ticks spent queuing -system.physmem.totMemAccLat 193713000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1537 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 314.836695 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 187.294672 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.034747 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 563 36.63% 36.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 357 23.23% 59.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 158 10.28% 70.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 85 5.53% 75.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 84 5.47% 81.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 48 3.12% 84.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 39 2.54% 86.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 28 1.82% 88.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 175 11.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1537 # Bytes accessed per row activation +system.physmem.totQLat 55497500 # Total ticks spent queuing +system.physmem.totMemAccLat 197753750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37935000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6782.23 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7314.81 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25532.23 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26064.81 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s @@ -217,48 +217,48 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6068 # Number of row buffer hits during reads +system.physmem.readRowHits 6044 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.98 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.66 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 29659944.11 # Average gap between requests -system.physmem.pageHitRate 79.98 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5012280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2734875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 29881800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 29661350.07 # Average gap between requests +system.physmem.pageHitRate 79.66 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5110560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2788500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 29967600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14697384000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5831471925 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 129898404750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 150464889630 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.664832 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 216095628500 # Time in different power states -system.physmem_0.memoryStateTime::REF 7514000000 # Time in different power states +system.physmem_0.refreshEnergy 14698401120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5878157490 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 129866796000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 150481221270 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.691134 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 216043617250 # Time in different power states +system.physmem_0.memoryStateTime::REF 7514520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1413270250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1481090250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6380640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3481500 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 6501600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3547500 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 29000400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14697384000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 6004643625 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 129746499750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 150487389915 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.764823 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 215845139250 # Time in different power states -system.physmem_1.memoryStateTime::REF 7514000000 # Time in different power states +system.physmem_1.refreshEnergy 14698401120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6069721950 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 129698757000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 150505929570 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.800930 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 215760799500 # Time in different power states +system.physmem_1.memoryStateTime::REF 7514520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1668675750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1763151750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 32430290 # Number of BP lookups +system.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 32430292 # Number of BP lookups system.cpu.branchPred.condPredicted 16924100 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 738493 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17494980 # Number of BTB lookups -system.cpu.branchPred.BTBHits 12858502 # Number of BTB hits +system.cpu.branchPred.BTBLookups 17494982 # Number of BTB lookups +system.cpu.branchPred.BTBHits 12858504 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 73.498238 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 73.498241 # BTB Hit Percentage system.cpu.branchPred.usedRAS 6523127 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 2303930 # Number of indirect predictor lookups. @@ -266,7 +266,7 @@ system.cpu.branchPred.indirectHits 2264813 # Nu system.cpu.branchPred.indirectMisses 39117 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 128237 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,16 +387,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 225030243000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 450060486 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 450081822 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 273037855 # Number of instructions committed system.cpu.committedOps 327812212 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2063972 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2063975 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.648345 # CPI: cycles per instruction -system.cpu.ipc 0.606669 # IPC: instructions per cycle +system.cpu.cpi 1.648423 # CPI: cycles per instruction +system.cpu.ipc 0.606640 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 104312542 31.82% 31.82% # Class of committed instruction system.cpu.op_class_0::IntMult 2145905 0.65% 32.48% # Class of committed instruction @@ -432,18 +432,18 @@ system.cpu.op_class_0::MemWrite 82375599 25.13% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 327812212 # Class of committed instruction -system.cpu.tickCycles 434886518 # Number of cycles that the object actually ticked -system.cpu.idleCycles 15173968 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 434887274 # Number of cycles that the object actually ticked +system.cpu.idleCycles 15194548 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1355 # number of replacements -system.cpu.dcache.tags.tagsinuse 3086.261687 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168654217 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3086.207714 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168654219 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4512 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37379.037456 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37379.037899 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3086.261687 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.753482 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.753482 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3086.207714 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.753469 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.753469 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id @@ -451,43 +451,43 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 7 system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 337326818 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 337326818 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 86521433 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86521433 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82047456 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047456 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 337326820 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337326820 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 86521434 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86521434 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82047457 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047457 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 63538 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 63538 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168568889 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168568889 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168632427 # number of overall hits -system.cpu.dcache.overall_hits::total 168632427 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 168568891 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168568891 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168632429 # number of overall hits +system.cpu.dcache.overall_hits::total 168632429 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1710 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1710 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5221 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5221 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5220 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5220 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 6931 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6931 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 6936 # number of overall misses -system.cpu.dcache.overall_misses::total 6936 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 114932500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 114932500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 393586500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 393586500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 508519000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 508519000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 508519000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 508519000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86523143 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86523143 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 6930 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6930 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6935 # number of overall misses +system.cpu.dcache.overall_misses::total 6935 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 116252000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 116252000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 401349000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 401349000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 517601000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 517601000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 517601000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 517601000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86523144 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86523144 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 63543 # number of SoftPFReq accesses(hits+misses) @@ -496,10 +496,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168575820 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168575820 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168639363 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168639363 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168575821 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168575821 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168639364 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168639364 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses @@ -510,14 +510,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000041 system.cpu.dcache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000041 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67211.988304 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67211.988304 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75385.271021 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75385.271021 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73368.777954 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73368.777954 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73315.888120 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73315.888120 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67983.625731 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67983.625731 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76886.781609 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76886.781609 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 74689.898990 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 74689.898990 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 74636.049027 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 74636.049027 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -528,12 +528,12 @@ system.cpu.dcache.writebacks::writebacks 1010 # nu system.cpu.dcache.writebacks::total 1010 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 71 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2351 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2351 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2422 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2422 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2422 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2422 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2350 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2350 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2421 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2421 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2421 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2421 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1639 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1639 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses @@ -544,16 +544,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4509 system.cpu.dcache.demand_mshr_misses::total 4509 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4512 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4512 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 110662500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 110662500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219478500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 219478500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 238000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 238000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 330141000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 330141000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 330379000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 330379000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 111802000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 111802000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 223602000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 223602000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 241000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 241000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 335404000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 335404000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 335645000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 335645000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -564,72 +564,72 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67518.303844 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67518.303844 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76473.344948 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76473.344948 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79333.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79333.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73218.230206 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73218.230206 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73222.296099 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73222.296099 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68213.544844 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68213.544844 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77910.104530 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77910.104530 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74385.451320 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74385.451320 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74389.406028 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74389.406028 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 38188 # number of replacements -system.cpu.icache.tags.tagsinuse 1925.010528 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 69819783 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1924.983594 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 69819782 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 40125 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1740.056897 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1740.056872 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1925.010528 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939947 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939947 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.983594 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939933 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939933 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 277 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 139759943 # Number of tag accesses -system.cpu.icache.tags.data_accesses 139759943 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 69819783 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 69819783 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 69819783 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 69819783 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 69819783 # number of overall hits -system.cpu.icache.overall_hits::total 69819783 # number of overall hits +system.cpu.icache.tags.tag_accesses 139759941 # Number of tag accesses +system.cpu.icache.tags.data_accesses 139759941 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 69819782 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 69819782 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 69819782 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 69819782 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 69819782 # number of overall hits +system.cpu.icache.overall_hits::total 69819782 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 40126 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 40126 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 40126 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 40126 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 40126 # number of overall misses system.cpu.icache.overall_misses::total 40126 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 756662500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 756662500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 756662500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 756662500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 756662500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 756662500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 69859909 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 69859909 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 69859909 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 69859909 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 69859909 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 69859909 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 763080000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 763080000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 763080000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 763080000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 763080000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 763080000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 69859908 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 69859908 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 69859908 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 69859908 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 69859908 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 69859908 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000574 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000574 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000574 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000574 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000574 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000574 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18857.162438 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18857.162438 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18857.162438 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18857.162438 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18857.162438 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18857.162438 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19017.096147 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19017.096147 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19017.096147 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19017.096147 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19017.096147 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19017.096147 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -644,48 +644,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 40126 system.cpu.icache.demand_mshr_misses::total 40126 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 40126 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 40126 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 716537500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 716537500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 716537500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 716537500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 716537500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 716537500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 722955000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 722955000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 722955000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 722955000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 722955000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 722955000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000574 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000574 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000574 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17857.187360 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17857.187360 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17857.187360 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17857.187360 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17857.187360 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17857.187360 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18017.121069 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18017.121069 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18017.121069 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18017.121069 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18017.121069 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18017.121069 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4201.230054 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 60569 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5649 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.722075 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 6597.313111 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 61516 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 7587 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 8.108080 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 354.127692 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3168.434045 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 678.668317 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.010807 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096693 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.020711 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.128211 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5649 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3168.373403 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.939708 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096691 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.104643 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.201334 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 7587 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1257 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4262 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172394 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 561687 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 561687 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 789 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6671 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.231537 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 560755 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 560755 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 1010 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 1010 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 23270 # number of WritebackClean hits @@ -714,18 +712,18 @@ system.cpu.l2cache.demand_misses::total 7630 # nu system.cpu.l2cache.overall_misses::cpu.inst 3426 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses system.cpu.l2cache.overall_misses::total 7630 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 214976500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 214976500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 256075000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 256075000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 105174500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 105174500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 256075000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 320151000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 576226000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 256075000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 320151000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 576226000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 219100000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 219100000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 262492500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 262492500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 106317000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 106317000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 262492500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 325417000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 587909500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 262492500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 325417000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 587909500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 1010 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 1010 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 23270 # number of WritebackClean accesses(hits+misses) @@ -754,18 +752,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.170931 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085381 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.931738 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.170931 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75324.632095 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75324.632095 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74744.600117 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74744.600117 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77907.037037 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77907.037037 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74744.600117 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76153.901047 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75521.100917 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74744.600117 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76153.901047 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75521.100917 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76769.446391 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76769.446391 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76617.775832 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76617.775832 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78753.333333 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78753.333333 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76617.775832 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77406.517602 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77052.359109 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76617.775832 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77406.517602 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77052.359109 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -794,18 +792,18 @@ system.cpu.l2cache.demand_mshr_misses::total 7587 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3424 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4163 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7587 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 186436500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 186436500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 221700500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 221700500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 89390500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 89390500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 221700500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 275827000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 497527500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 221700500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 275827000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 497527500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 190560000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 190560000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 228116000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 228116000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 90492000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 90492000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 228116000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 281052000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 509168000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 228116000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 281052000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 509168000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for ReadCleanReq accesses @@ -818,25 +816,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.169967 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.169967 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65324.632095 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65324.632095 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64748.977804 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64748.977804 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68289.152024 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68289.152024 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64748.977804 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66256.785972 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65576.314749 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64748.977804 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66256.785972 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65576.314749 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66769.446391 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66769.446391 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66622.663551 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66622.663551 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69130.634072 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69130.634072 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66622.663551 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67511.890464 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67110.583894 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66622.663551 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67511.890464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67110.583894 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 84181 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 39645 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15035 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 41767 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 38188 # Transaction distribution @@ -870,7 +868,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 60188498 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6789457 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 7587 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4733 # Transaction distribution system.membus.trans_dist::ReadExReq 2854 # Transaction distribution system.membus.trans_dist::ReadExResp 2854 # Transaction distribution @@ -891,9 +895,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7587 # Request fanout histogram -system.membus.reqLayer0.occupancy 9083500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9083000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 40284000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40294250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 01e70293e..3bab29953 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.111754 # Number of seconds simulated -sim_ticks 111753553500 # Number of ticks simulated -final_tick 111753553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.120480 # Number of seconds simulated +sim_ticks 120480458500 # Number of ticks simulated +final_tick 120480458500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 142273 # Simulator instruction rate (inst/s) -host_op_rate 170814 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58231903 # Simulator tick rate (ticks/s) -host_mem_usage 288696 # Number of bytes of host memory used -host_seconds 1919.11 # Real time elapsed on the host -sim_insts 273037220 # Number of instructions simulated -sim_ops 327811602 # Number of ops (including micro ops) simulated +host_inst_rate 129515 # Simulator instruction rate (inst/s) +host_op_rate 155497 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57149813 # Simulator tick rate (ticks/s) +host_mem_usage 293332 # Number of bytes of host memory used +host_seconds 2108.15 # Real time elapsed on the host +sim_insts 273037218 # Number of instructions simulated +sim_ops 327811600 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 620544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 4626112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 168832 # Number of bytes read from this memory -system.physmem.bytes_read::total 5415488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 620544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 620544 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 9696 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 72283 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 2638 # Number of read requests responded to by this memory -system.physmem.num_reads::total 84617 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 5552790 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 41395659 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 1510753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48459202 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5552790 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5552790 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5552790 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 41395659 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 1510753 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 48459202 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 84617 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1888064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 14651392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 167808 # Number of bytes read from this memory +system.physmem.bytes_read::total 16707264 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1888064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1888064 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 29501 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 228928 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2622 # Number of read requests responded to by this memory +system.physmem.num_reads::total 261051 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 15671122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 121608037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1392823 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 138671982 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 15671122 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 15671122 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 15671122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 121608037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1392823 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 138671982 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 261052 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 84617 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 261052 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5415488 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 16707328 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5415488 # Total read bytes from the system interface side +system.physmem.bytesReadSys 16707328 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 956 # Per bank write bursts -system.physmem.perBankRdBursts::1 811 # Per bank write bursts -system.physmem.perBankRdBursts::2 834 # Per bank write bursts -system.physmem.perBankRdBursts::3 2907 # Per bank write bursts -system.physmem.perBankRdBursts::4 10637 # Per bank write bursts -system.physmem.perBankRdBursts::5 59817 # Per bank write bursts -system.physmem.perBankRdBursts::6 152 # Per bank write bursts -system.physmem.perBankRdBursts::7 259 # Per bank write bursts -system.physmem.perBankRdBursts::8 225 # Per bank write bursts -system.physmem.perBankRdBursts::9 303 # Per bank write bursts -system.physmem.perBankRdBursts::10 3870 # Per bank write bursts -system.physmem.perBankRdBursts::11 811 # Per bank write bursts -system.physmem.perBankRdBursts::12 1141 # Per bank write bursts -system.physmem.perBankRdBursts::13 693 # Per bank write bursts -system.physmem.perBankRdBursts::14 638 # Per bank write bursts -system.physmem.perBankRdBursts::15 563 # Per bank write bursts +system.physmem.perBankRdBursts::0 1258 # Per bank write bursts +system.physmem.perBankRdBursts::1 69992 # Per bank write bursts +system.physmem.perBankRdBursts::2 1296 # Per bank write bursts +system.physmem.perBankRdBursts::3 10757 # Per bank write bursts +system.physmem.perBankRdBursts::4 42908 # Per bank write bursts +system.physmem.perBankRdBursts::5 121820 # Per bank write bursts +system.physmem.perBankRdBursts::6 160 # Per bank write bursts +system.physmem.perBankRdBursts::7 266 # Per bank write bursts +system.physmem.perBankRdBursts::8 224 # Per bank write bursts +system.physmem.perBankRdBursts::9 562 # Per bank write bursts +system.physmem.perBankRdBursts::10 7776 # Per bank write bursts +system.physmem.perBankRdBursts::11 812 # Per bank write bursts +system.physmem.perBankRdBursts::12 1213 # Per bank write bursts +system.physmem.perBankRdBursts::13 743 # Per bank write bursts +system.physmem.perBankRdBursts::14 656 # Per bank write bursts +system.physmem.perBankRdBursts::15 609 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 111753395000 # Total gap between requests +system.physmem.totGap 120480449000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 84617 # Read request sizes (log2) +system.physmem.readPktSize::6 261052 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,19 +95,19 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 64967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 17796 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 204297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 43283 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12075 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 234 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 208 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 53 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 216 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 31 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 21 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see @@ -191,86 +191,86 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 21291 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 254.217463 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 213.921670 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 155.515771 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 2572 12.08% 12.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 7102 33.36% 45.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8141 38.24% 83.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1445 6.79% 90.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1060 4.98% 95.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 699 3.28% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 33 0.15% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 27 0.13% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 212 1.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 21291 # Bytes accessed per row activation -system.physmem.totQLat 818886094 # Total ticks spent queuing -system.physmem.totMemAccLat 2405454844 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 423085000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9677.56 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 67045 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 249.160415 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 181.717328 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 205.520754 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18369 27.40% 27.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 21159 31.56% 58.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11457 17.09% 76.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6629 9.89% 85.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4618 6.89% 92.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2220 3.31% 96.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1372 2.05% 98.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 491 0.73% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 730 1.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67045 # Bytes accessed per row activation +system.physmem.totQLat 2500931533 # Total ticks spent queuing +system.physmem.totMemAccLat 7395656533 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1305260000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9580.20 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28427.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 48.46 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28330.20 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 138.67 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 48.46 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 138.67 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.38 # Data bus utilization in percentage -system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads +system.physmem.busUtil 1.08 # Data bus utilization in percentage +system.physmem.busUtilRead 1.08 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.36 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.60 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 63316 # Number of row buffer hits during reads +system.physmem.readRowHits 193998 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.83 # Row buffer hit rate for reads +system.physmem.readRowHitRate 74.31 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1320696.73 # Average gap between requests -system.physmem.pageHitRate 74.83 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 137093040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 74802750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 595467600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 461518.97 # Average gap between requests +system.physmem.pageHitRate 74.31 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 469687680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 256278000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1937777400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 7298853120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 61580578995 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 13031079750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 82717875255 # Total energy per rank (pJ) -system.physmem_0.averagePower 740.214288 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 21327892271 # Time in different power states -system.physmem_0.memoryStateTime::REF 3731520000 # Time in different power states +system.physmem_0.refreshEnergy 7868948880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 73664414550 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 7668236250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 91865342760 # Total energy per rank (pJ) +system.physmem_0.averagePower 762.514125 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 12350213739 # Time in different power states +system.physmem_0.memoryStateTime::REF 4022980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 86689152979 # Time in different power states +system.physmem_0.memoryStateTime::ACT 104104852261 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 23821560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 12997875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 64092600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 37134720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 20262000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 98069400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 7298853120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10878672015 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 57506417250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 75784854420 # Total energy per rank (pJ) -system.physmem_1.averagePower 678.173227 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 95612479879 # Time in different power states -system.physmem_1.memoryStateTime::REF 3731520000 # Time in different power states +system.physmem_1.refreshEnergy 7868948880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 16939770435 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 57426696000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 82390881435 # Total energy per rank (pJ) +system.physmem_1.averagePower 683.872818 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 95444315624 # Time in different power states +system.physmem_1.memoryStateTime::REF 4022980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 12405217621 # Time in different power states +system.physmem_1.memoryStateTime::ACT 21009739880 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 35971731 # Number of BP lookups -system.cpu.branchPred.condPredicted 19265386 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 984189 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17894968 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13923402 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 35971487 # Number of BP lookups +system.cpu.branchPred.condPredicted 19266966 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 984300 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17894295 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13923321 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 77.806241 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6951964 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4431 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2517343 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2473442 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 43901 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 128855 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 77.808715 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6951891 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4417 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 2517210 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2473355 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 43855 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 128902 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -300,7 +300,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -330,7 +330,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -360,7 +360,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -391,131 +391,131 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 223507108 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 240960918 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12083599 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 309381854 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35971731 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23348808 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 209499863 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1989645 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1258 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 12852393 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 309387545 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35971487 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23348567 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 224289895 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1990323 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1871 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 93 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 2666 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 82203342 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 33398 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 222582301 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.671920 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.267628 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3026 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 82204082 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 34266 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 238142439 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.562665 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.293284 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 62373241 28.02% 28.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 40203334 18.06% 46.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 28080746 12.62% 58.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 91924980 41.30% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 77933727 32.73% 32.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 40203358 16.88% 49.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 28082672 11.79% 61.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 91922682 38.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 222582301 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.160942 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.384215 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 26238985 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 73050782 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 98117127 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 24314460 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 860947 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6686817 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 134221 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 348541423 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3410145 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 860947 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42548430 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 23450678 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 285531 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 105165670 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 50271045 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 344601348 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1453656 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 7084396 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 85832 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7483674 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 23725025 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 3279176 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 394880845 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2218133140 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 335914250 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 192916662 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22650794 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11588 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11554 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 57533645 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89989968 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 84391268 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1975718 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1902358 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 343283622 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22608 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 339469619 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 966789 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 15494628 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 37288530 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 488 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 222582301 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.525142 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.109331 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 238142439 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.149283 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.283974 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 26809492 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 87975457 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 98235303 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 24260898 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 861289 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6686645 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 134215 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 348536073 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3411178 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 861289 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 43087679 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 34729777 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 287359 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 105264108 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53912227 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 344595535 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1451317 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7117459 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 85486 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7456793 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 27429966 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 3277218 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 394867605 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2218081796 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 335910446 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 192911530 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 372230048 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 22637557 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11606 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11573 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 57394706 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89984018 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 84392471 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1976841 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1898355 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343274386 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22623 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 339465004 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 967637 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 15485409 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 37250778 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 503 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 238142439 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.425470 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.136916 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 42440680 19.07% 19.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 76122495 34.20% 53.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 59389973 26.68% 79.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34692267 15.59% 95.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9226095 4.15% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 678749 0.30% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 32042 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 57979720 24.35% 24.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 76155774 31.98% 56.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 59457503 24.97% 81.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34550396 14.51% 95.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9286722 3.90% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 677796 0.28% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34528 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 222582301 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 238142439 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9228112 7.75% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7358 0.01% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 237798 0.20% 7.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 147681 0.12% 8.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 70485 0.06% 8.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 67886 0.06% 8.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 638269 0.54% 8.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 297789 0.25% 8.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 542439 0.46% 9.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 51542568 43.28% 52.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 56315471 47.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9217758 7.75% 7.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7319 0.01% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 238781 0.20% 7.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 138932 0.12% 8.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 70694 0.06% 8.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 68373 0.06% 8.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 637081 0.54% 8.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 296736 0.25% 8.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 541785 0.46% 9.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 51510154 43.32% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 56187310 47.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 108184507 31.87% 31.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148145 0.63% 32.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 108183295 31.87% 31.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148337 0.63% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.50% # Type of FU issued @@ -534,103 +534,103 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.50% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6792731 2.00% 34.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6792696 2.00% 34.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8635726 2.54% 37.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3210403 0.95% 37.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1592905 0.47% 38.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20864008 6.15% 44.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7178651 2.11% 46.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7141492 2.10% 48.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175295 0.05% 48.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 90027492 26.52% 75.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 83518264 24.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8634939 2.54% 37.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3210556 0.95% 37.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592986 0.47% 38.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20863290 6.15% 44.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7179112 2.11% 46.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7141893 2.10% 48.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175297 0.05% 48.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 90024001 26.52% 75.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 83518602 24.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 339469619 # Type of FU issued -system.cpu.iq.rate 1.518831 # Inst issue rate -system.cpu.iq.fu_busy_cnt 119095856 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.350829 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 738018306 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 235153924 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 219171367 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 283565878 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 123658767 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 116921576 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 293614389 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 164951086 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5389138 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 339465004 # Type of FU issued +system.cpu.iq.rate 1.408797 # Inst issue rate +system.cpu.iq.fu_busy_cnt 118914923 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.350301 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 753593457 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 235149136 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 219170609 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 283361550 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 123645361 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 116917491 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 293630516 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 164749411 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5409371 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4257693 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7295 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11836 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2015651 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4251743 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7382 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12082 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2016854 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 126905 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 613909 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 126951 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 613385 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 860947 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1344821 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 736472 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 343307622 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 861289 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1346418 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1223561 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343298428 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89989968 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 84391268 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11575 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7371 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 729404 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11836 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 437891 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 454375 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 892266 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 337441545 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 89439870 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2028074 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 89984018 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 84392471 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11590 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 7654 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1216581 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12082 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 438027 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 454511 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 892538 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 337435973 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 89435470 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2029031 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1392 # number of nop insts executed -system.cpu.iew.exec_refs 172567373 # number of memory reference insts executed -system.cpu.iew.exec_branches 31555849 # Number of branches executed -system.cpu.iew.exec_stores 83127503 # Number of stores executed -system.cpu.iew.exec_rate 1.509758 # Inst execution rate -system.cpu.iew.wb_sent 336239137 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 336092943 # cumulative count of insts written-back -system.cpu.iew.wb_producers 151867680 # num instructions producing a value -system.cpu.iew.wb_consumers 263704827 # num instructions consuming a value -system.cpu.iew.wb_rate 1.503724 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.575900 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 14172678 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1419 # number of nop insts executed +system.cpu.iew.exec_refs 172563167 # number of memory reference insts executed +system.cpu.iew.exec_branches 31555788 # Number of branches executed +system.cpu.iew.exec_stores 83127697 # Number of stores executed +system.cpu.iew.exec_rate 1.400376 # Inst execution rate +system.cpu.iew.wb_sent 336234414 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 336088100 # cumulative count of insts written-back +system.cpu.iew.wb_producers 151781597 # num instructions producing a value +system.cpu.iew.wb_consumers 263546089 # num instructions consuming a value +system.cpu.iew.wb_rate 1.394783 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.575921 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 14163176 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 850314 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 220392023 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.487405 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.078236 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 850428 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 235953046 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.389311 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.042233 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 89247998 40.50% 40.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 67546822 30.65% 71.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 20918501 9.49% 80.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13253983 6.01% 86.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8642695 3.92% 90.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4496391 2.04% 92.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3033426 1.38% 93.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2604506 1.18% 95.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10647701 4.83% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 104793604 44.41% 44.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 67594704 28.65% 73.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 20883417 8.85% 81.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13239055 5.61% 87.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8655759 3.67% 91.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4517031 1.91% 93.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3019754 1.28% 94.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2590982 1.10% 95.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10658740 4.52% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 220392023 # Number of insts commited each cycle -system.cpu.commit.committedInsts 273037832 # Number of instructions committed -system.cpu.commit.committedOps 327812214 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 235953046 # Number of insts commited each cycle +system.cpu.commit.committedInsts 273037830 # Number of instructions committed +system.cpu.commit.committedOps 327812212 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 168107892 # Number of memory references committed system.cpu.commit.loads 85732275 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 30563526 # Number of branches committed +system.cpu.commit.branches 30563525 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 258331704 # Number of committed integer instructions. +system.cpu.commit.int_insts 258331703 # Number of committed integer instructions. system.cpu.commit.function_calls 6225114 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 104312487 31.82% 31.82% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 104312485 31.82% 31.82% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 2145917 0.65% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction @@ -663,157 +663,157 @@ system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Cl system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 327812214 # Class of committed instruction -system.cpu.commit.bw_lim_events 10647701 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 551726691 # The number of ROB reads -system.cpu.rob.rob_writes 686162246 # The number of ROB writes -system.cpu.timesIdled 18335 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 924807 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 273037220 # Number of Instructions Simulated -system.cpu.committedOps 327811602 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.818596 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.818596 # CPI: Total CPI of All Threads -system.cpu.ipc 1.221604 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.221604 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 325161919 # number of integer regfile reads -system.cpu.int_regfile_writes 134094717 # number of integer regfile writes -system.cpu.fp_regfile_reads 186641875 # number of floating regfile reads -system.cpu.fp_regfile_writes 131668024 # number of floating regfile writes -system.cpu.cc_regfile_reads 1279432977 # number of cc regfile reads -system.cpu.cc_regfile_writes 80060950 # number of cc regfile writes -system.cpu.misc_regfile_reads 1056766062 # number of misc regfile reads +system.cpu.commit.op_class_0::total 327812212 # Class of committed instruction +system.cpu.commit.bw_lim_events 10658740 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 567267171 # The number of ROB reads +system.cpu.rob.rob_writes 686142351 # The number of ROB writes +system.cpu.timesIdled 39413 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2818479 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 273037218 # Number of Instructions Simulated +system.cpu.committedOps 327811600 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.882520 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.882520 # CPI: Total CPI of All Threads +system.cpu.ipc 1.133118 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.133118 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 325162337 # number of integer regfile reads +system.cpu.int_regfile_writes 134093699 # number of integer regfile writes +system.cpu.fp_regfile_reads 186638060 # number of floating regfile reads +system.cpu.fp_regfile_writes 131662989 # number of floating regfile writes +system.cpu.cc_regfile_reads 1279404689 # number of cc regfile reads +system.cpu.cc_regfile_writes 80058303 # number of cc regfile writes +system.cpu.misc_regfile_reads 1056730531 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1542955 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.836799 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 162076726 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1543467 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 105.008222 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 85416000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.836799 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999681 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999681 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1542807 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.846983 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 162052499 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1543319 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 105.002594 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 87321000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.846983 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999701 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999701 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 333528119 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 333528119 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 81065236 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 81065236 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80920030 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80920030 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 69611 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 69611 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10906 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10906 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 333478959 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 333478959 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 81039652 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 81039652 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80921351 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80921351 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 69633 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 69633 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10908 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10908 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 161985266 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 161985266 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 162054877 # number of overall hits -system.cpu.dcache.overall_hits::total 162054877 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2782957 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2782957 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1132669 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1132669 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 161961003 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 161961003 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 162030636 # number of overall hits +system.cpu.dcache.overall_hits::total 162030636 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2784011 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2784011 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1131348 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1131348 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3915626 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3915626 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3915644 # number of overall misses -system.cpu.dcache.overall_misses::total 3915644 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31092984500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31092984500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9127104911 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9127104911 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 182000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 182000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 40220089411 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 40220089411 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 40220089411 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 40220089411 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 83848193 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 83848193 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3915359 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3915359 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3915377 # number of overall misses +system.cpu.dcache.overall_misses::total 3915377 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 45256653500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 45256653500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9138834402 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9138834402 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 184000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 54395487902 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 54395487902 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 54395487902 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 54395487902 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 83823663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 83823663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 69629 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 69629 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10910 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10910 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 69651 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 69651 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10912 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10912 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 165900892 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 165900892 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 165970521 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 165970521 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033190 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.033190 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013804 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013804 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000259 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.000259 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 165876362 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 165876362 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 165946013 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 165946013 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033213 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.033213 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013788 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013788 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000258 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000258 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000367 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000367 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023602 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023602 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023592 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023592 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11172.642804 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11172.642804 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8058.051303 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8058.051303 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 45500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 45500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10271.688208 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10271.688208 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10271.640990 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10271.640990 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.023604 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023604 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023594 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023594 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16255.917631 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16255.917631 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8077.827867 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8077.827867 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 46000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 46000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13892.848115 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13892.848115 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13892.784246 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13892.784246 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1079488 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1086145 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 136770 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 136219 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7.892725 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1542955 # number of writebacks -system.cpu.dcache.writebacks::total 1542955 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1460236 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1460236 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911920 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 911920 # number of WriteReq MSHR hits +system.cpu.dcache.avg_blocked_cycles::no_targets 7.973521 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 1542807 # number of writebacks +system.cpu.dcache.writebacks::total 1542807 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1461430 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1461430 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910604 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 910604 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2372156 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2372156 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2372156 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2372156 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322721 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1322721 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220749 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 220749 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 2372034 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2372034 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2372034 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2372034 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322581 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1322581 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220744 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 220744 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1543470 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1543470 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1543481 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1543481 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15298451500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15298451500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1831859691 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1831859691 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 695500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 695500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17130311191 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17130311191 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17131006691 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17131006691 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015775 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015775 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1543325 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1543325 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1543336 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1543336 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25407816000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 25407816000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1834277181 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1834277181 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 705000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 705000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27242093181 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27242093181 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27242798181 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27242798181 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015778 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015778 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002690 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002690 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000158 # mshr miss rate for SoftPFReq accesses @@ -822,392 +822,396 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009304 system.cpu.dcache.demand_mshr_miss_rate::total 0.009304 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009300 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.009300 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11565.894471 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11565.894471 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8298.382738 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8298.382738 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 63227.272727 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 63227.272727 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11098.570877 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11098.570877 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11098.942385 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11098.942385 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 726201 # number of replacements -system.cpu.icache.tags.tagsinuse 511.803602 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 81470529 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 726713 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 112.108259 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 331355500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.803602 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999616 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999616 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19210.782553 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19210.782553 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8309.522257 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8309.522257 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 64090.909091 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 64090.909091 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17651.559575 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17651.559575 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17651.890568 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17651.890568 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 725593 # number of replacements +system.cpu.icache.tags.tagsinuse 511.815316 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 81471161 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 726105 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 112.203002 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 334835500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.815316 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999639 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999639 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 242 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 243 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 70 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 165133375 # Number of tag accesses -system.cpu.icache.tags.data_accesses 165133375 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 81470529 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 81470529 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 81470529 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 81470529 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 81470529 # number of overall hits -system.cpu.icache.overall_hits::total 81470529 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 732796 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 732796 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 732796 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 732796 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 732796 # number of overall misses -system.cpu.icache.overall_misses::total 732796 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 6565806949 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 6565806949 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 6565806949 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 6565806949 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 6565806949 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 6565806949 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 82203325 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 82203325 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 82203325 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 82203325 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 82203325 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 82203325 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008914 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008914 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008914 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008914 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008914 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008914 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8959.938303 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8959.938303 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8959.938303 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8959.938303 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8959.938303 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8959.938303 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 64284 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3051 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 165134244 # Number of tag accesses +system.cpu.icache.tags.data_accesses 165134244 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 81471161 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 81471161 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 81471161 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 81471161 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 81471161 # number of overall hits +system.cpu.icache.overall_hits::total 81471161 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 732901 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 732901 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 732901 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 732901 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 732901 # number of overall misses +system.cpu.icache.overall_misses::total 732901 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 8031652441 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 8031652441 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 8031652441 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 8031652441 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 8031652441 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 8031652441 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 82204062 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 82204062 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 82204062 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 82204062 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 82204062 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 82204062 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008916 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008916 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008916 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008916 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008916 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008916 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10958.713989 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10958.713989 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10958.713989 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10958.713989 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10958.713989 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10958.713989 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 128534 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 100 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4274 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.069813 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 31.333333 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 726201 # number of writebacks -system.cpu.icache.writebacks::total 726201 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 6071 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 6071 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 6071 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 6071 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 6071 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 6071 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726725 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 726725 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 726725 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 726725 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 726725 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 726725 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6109081458 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 6109081458 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6109081458 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 6109081458 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6109081458 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 6109081458 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008841 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008841 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008841 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.008841 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008841 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.008841 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8406.318013 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8406.318013 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8406.318013 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8406.318013 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 402434 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 402547 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 102 # number of redundant prefetches already in prefetch queue +system.cpu.icache.avg_blocked_cycles::no_mshrs 30.073467 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 33.333333 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 725593 # number of writebacks +system.cpu.icache.writebacks::total 725593 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 6780 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 6780 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 6780 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 6780 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 6780 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 6780 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726121 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 726121 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 726121 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 726121 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 726121 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 726121 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7527879949 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 7527879949 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7527879949 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 7527879949 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7527879949 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 7527879949 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008833 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.008833 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.008833 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10367.252771 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10367.252771 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10367.252771 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 10367.252771 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10367.252771 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 10367.252771 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 402848 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 402975 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 113 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 28085 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.pfSpanPage 27937 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 5603.177963 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3041133 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 6750 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 450.538222 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 5253.562311 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1811987 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 6314 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 286.979252 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 5495.535708 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 107.642255 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.335421 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006570 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.341991 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 497 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 6253 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 5154.206528 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 99.355783 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.314588 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006064 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.320652 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 192 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 6122 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 12 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 344 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 113 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 912 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 72 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5048 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.030334 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.381653 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 69530063 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 69530063 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 968360 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 968360 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1046226 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1046226 # number of WritebackClean hits +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 48 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 110 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 555 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1137 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 139 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4125 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011719 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.373657 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 70548606 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 70548606 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 968253 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 968253 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1045699 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1045699 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 219964 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 219964 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 716938 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 716938 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1251135 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1251135 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 716938 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1471099 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2188037 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 716938 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1471099 # number of overall hits -system.cpu.l2cache.overall_hits::total 2188037 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 781 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 781 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 9708 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 9708 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 71587 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 71587 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 9708 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 72368 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 82076 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 9708 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 72368 # number of overall misses -system.cpu.l2cache.overall_misses::total 82076 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 40000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 40000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56104500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 56104500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 688634000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 688634000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5061315000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 5061315000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 688634000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 5117419500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 5806053500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 688634000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 5117419500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 5806053500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 968360 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 968360 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1046226 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1046226 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 220745 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 220745 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 726646 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 726646 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1322722 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1322722 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 726646 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1543467 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2270113 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 726646 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1543467 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2270113 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.928571 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.928571 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003538 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.003538 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.013360 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.013360 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.054121 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.054121 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.013360 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.046887 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.036155 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.013360 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.046887 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.036155 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 3076.923077 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 3076.923077 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71836.747759 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71836.747759 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 70934.693037 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 70934.693037 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 70701.593865 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 70701.593865 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70934.693037 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70713.844517 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70739.966616 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70934.693037 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70713.844517 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70739.966616 # average overall miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.data 219932 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 219932 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 696525 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 696525 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1094373 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1094373 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 696525 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1314305 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2010830 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 696525 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1314305 # number of overall hits +system.cpu.l2cache.overall_hits::total 2010830 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 16 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 16 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 807 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 807 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 29515 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 29515 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 228207 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 228207 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 29515 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 229014 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 258529 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 29515 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 229014 # number of overall misses +system.cpu.l2cache.overall_misses::total 258529 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 43000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 43000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 59970500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 59970500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2262045500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 2262045500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 16271473000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 16271473000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 2262045500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 16331443500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 18593489000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 2262045500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 16331443500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 18593489000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 968253 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 968253 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1045699 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1045699 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 220739 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 220739 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 726040 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 726040 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1322580 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1322580 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 726040 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1543319 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2269359 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 726040 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1543319 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2269359 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.941176 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.941176 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003656 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.003656 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.040652 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.040652 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.172547 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.172547 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.040652 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.148391 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.113922 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.040652 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.148391 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.113922 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2687.500000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2687.500000 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74312.887237 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74312.887237 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76640.538709 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76640.538709 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 71301.375506 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 71301.375506 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76640.538709 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71311.987477 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71920.322285 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76640.538709 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71311.987477 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71920.322285 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 51 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 51 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 12 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 34 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 34 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 85 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 97 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 85 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 97 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 51651 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 51651 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 730 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 730 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 9696 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 9696 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 71553 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 71553 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 9696 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 72283 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 81979 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 9696 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 72283 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 51651 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 133630 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 178131300 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 178131300 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 187000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 187000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 50303500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 50303500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 629910500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 629910500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4630072500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4630072500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 629910500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4680376000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5310286500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 629910500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4680376000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 178131300 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5488417800 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 50 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 50 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 36 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 36 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 86 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 99 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 86 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 99 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 54157 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 54157 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 16 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 16 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 757 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 757 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 29502 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 29502 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 228171 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 228171 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 29502 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 228928 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 258430 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 29502 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 228928 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 54157 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 312587 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 187753381 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 187753381 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 251000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 251000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53315000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53315000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2084473500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2084473500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 14900259000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 14900259000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2084473500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14953574000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17038047500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2084473500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14953574000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 187753381 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17225800881 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.928571 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.928571 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003307 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003307 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013343 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013343 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.054095 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.054095 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013343 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.046832 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.036112 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013343 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.046832 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.941176 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.941176 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003429 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003429 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040634 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040634 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172520 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172520 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040634 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148335 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.113878 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040634 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148335 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.058865 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3448.748330 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3448.748330 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14384.615385 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14384.615385 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68908.904110 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68908.904110 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64966.016914 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64966.016914 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64708.293153 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64708.293153 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64966.016914 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64750.715936 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64776.180485 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64966.016914 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64750.715936 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3448.748330 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41071.748859 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4539362 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2269187 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254586 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 130262 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 52910 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 77352 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 2049447 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 968360 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1300796 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 81249 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 53022 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 14 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 220745 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 220745 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 726725 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322722 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2179572 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629917 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6809489 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92982208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197531008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 290513216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 134350 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5056 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2404477 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.192237 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.468638 # Request fanout histogram +system.cpu.l2cache.overall_mshr_miss_rate::total 0.137742 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3466.834961 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3466.834961 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15687.500000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15687.500000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70429.326288 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70429.326288 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70655.328452 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70655.328452 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65303.035881 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65303.035881 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70655.328452 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65319.987070 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65929.062028 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70655.328452 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65319.987070 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3466.834961 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55107.220969 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4537857 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2268434 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254467 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 51535 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51534 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 2048700 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 968253 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1300147 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 55525 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 220739 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 220739 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 726121 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322580 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2177753 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629479 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6807232 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92904448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197512064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 290416512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 55606 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5184 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2324982 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.131629 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.338088 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2019600 83.99% 83.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 307525 12.79% 96.78% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 77352 3.22% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2018948 86.84% 86.84% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 306033 13.16% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2404477 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4538837000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 4.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1090392888 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2315538337 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 83887 # Transaction distribution -system.membus.trans_dist::UpgradeReq 13 # Transaction distribution -system.membus.trans_dist::ReadExReq 730 # Transaction distribution -system.membus.trans_dist::ReadExResp 730 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 83887 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 169247 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 169247 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 5415488 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 5415488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoop_fanout::total 2324982 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4537328500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 3.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1089458442 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2315007958 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 261068 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 253748 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 260294 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16 # Transaction distribution +system.membus.trans_dist::ReadExReq 757 # Transaction distribution +system.membus.trans_dist::ReadExResp 757 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 260295 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522119 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 522119 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16707264 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 16707264 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 84630 # Request fanout histogram +system.membus.snoop_fanout::samples 261068 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 84630 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 261068 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 84630 # Request fanout histogram -system.membus.reqLayer0.occupancy 108151910 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 445724357 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.snoop_fanout::total 261068 # Request fanout histogram +system.membus.reqLayer0.occupancy 329929457 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1377865586 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index e42324626..ec456bd8f 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.201717 # Nu sim_ticks 201717314000 # Number of ticks simulated final_tick 201717314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 732440 # Simulator instruction rate (inst/s) -host_op_rate 879375 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 541118678 # Simulator tick rate (ticks/s) -host_mem_usage 263976 # Number of bytes of host memory used -host_seconds 372.78 # Real time elapsed on the host +host_inst_rate 781022 # Simulator instruction rate (inst/s) +host_op_rate 937704 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 577011080 # Simulator tick rate (ticks/s) +host_mem_usage 268872 # Number of bytes of host memory used +host_seconds 349.59 # Real time elapsed on the host sim_insts 273037595 # Number of instructions simulated sim_ops 327811950 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -220,6 +220,12 @@ system.cpu.op_class::MemWrite 82375594 25.13% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812145 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 434895828 # Transaction distribution system.membus.trans_dist::ReadResp 434906723 # Transaction distribution @@ -239,14 +245,14 @@ system.membus.pkt_size::total 2275398075 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 517024352 # Request fanout histogram -system.membus.snoop_fanout::mean 0.674359 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 168364078 32.56% 32.56% # Request fanout histogram -system.membus.snoop_fanout::1 348660274 67.44% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 517024352 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 517024352 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index fd046e3e7..81799693e 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.517291 # Number of seconds simulated -sim_ticks 517291025500 # Number of ticks simulated -final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.517298 # Number of seconds simulated +sim_ticks 517297855500 # Number of ticks simulated +final_tick 517297855500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 451771 # Simulator instruction rate (inst/s) -host_op_rate 542368 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 856851233 # Simulator tick rate (ticks/s) -host_mem_usage 273716 # Number of bytes of host memory used -host_seconds 603.71 # Real time elapsed on the host +host_inst_rate 565388 # Simulator instruction rate (inst/s) +host_op_rate 678769 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1072356714 # Simulator tick rate (ticks/s) +host_mem_usage 278352 # Number of bytes of host memory used +host_seconds 482.39 # Real time elapsed on the host sim_insts 272739286 # Number of instructions simulated sim_ops 327433744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory system.physmem.bytes_read::total 437248 # Number of bytes read from this memory @@ -22,17 +22,17 @@ system.physmem.bytes_inst_read::total 166912 # Nu system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 322666 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 522599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 845265 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 322666 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 322666 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 322661 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 522593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 845254 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 322661 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 322661 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 322661 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 522593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 845254 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -62,7 +62,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -92,7 +92,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -122,7 +122,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -153,8 +153,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 517291025500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1034582051 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 517297855500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1034595711 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 272739286 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 168107847 # nu system.cpu.num_load_insts 85732248 # Number of load instructions system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1034582050.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1034595710.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 30563503 # Number of branches fetched @@ -214,16 +214,16 @@ system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812214 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1332 # number of replacements -system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3078.320204 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3078.335714 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.751547 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.751547 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3078.320204 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.751543 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.751543 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id @@ -233,7 +233,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits @@ -258,14 +258,14 @@ system.cpu.dcache.demand_misses::cpu.data 4476 # n system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses system.cpu.dcache.overall_misses::total 4479 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88052000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88052000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 177422500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 177422500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 265474500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 265474500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 265474500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 265474500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 89418000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 89418000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 180278500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 180278500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 269696500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 269696500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 269696500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 269696500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) @@ -290,14 +290,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54895.261845 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54895.261845 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61776.636490 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61776.636490 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59310.656836 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59310.656836 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59270.931011 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59270.931011 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55746.882793 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55746.882793 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62771.065460 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62771.065460 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60253.909741 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60253.909741 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60213.552132 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60213.552132 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -322,16 +322,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4475 system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86402000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 86402000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 174550500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 174550500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 183000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 183000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260952500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 260952500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 261135500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 261135500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 87767000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 87767000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 177406500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 177406500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 186000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 186000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 265173500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 265173500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 265359500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 265359500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -342,26 +342,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53900.187149 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53900.187149 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54751.715533 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54751.715533 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61771.065460 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61771.065460 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59256.648045 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 59256.648045 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59258.485931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 59258.485931 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 13796 # number of replacements -system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1765.939670 # Cycle average of tags in use system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1765.939670 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.862275 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.862275 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id @@ -371,7 +371,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 348644750 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 348644750 # number of demand (read+write) hits @@ -384,12 +384,12 @@ system.cpu.icache.demand_misses::cpu.inst 15603 # n system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses system.cpu.icache.overall_misses::total 15603 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 338446000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 338446000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 338446000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 338446000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 338446000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 338446000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 341054000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 341054000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 341054000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 341054000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 341054000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 341054000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses @@ -402,12 +402,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21691.085048 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21691.085048 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21691.085048 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21691.085048 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21858.232391 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21858.232391 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21858.232391 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21858.232391 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21858.232391 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21858.232391 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,48 +422,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603 system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322843000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 322843000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322843000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 322843000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322843000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 322843000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 325451000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 325451000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 325451000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 325451000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 325451000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 325451000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20858.232391 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20858.232391 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20858.232391 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20858.232391 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20858.232391 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20858.232391 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 5901.352793 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 20712 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 6832 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 3.031616 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 341.605293 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 738.688437 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073466 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.022543 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.106434 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.314356 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3494.038437 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073465 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.106630 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.180095 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 6832 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 758 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5967 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.208496 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 227184 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 227184 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits @@ -492,18 +490,18 @@ system.cpu.l2cache.demand_misses::total 6832 # nu system.cpu.l2cache.overall_misses::cpu.inst 2608 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4224 # number of overall misses system.cpu.l2cache.overall_misses::total 6832 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 170070500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 170070500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155292000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 155292000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 81591000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 81591000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 155292000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 251661500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 406953500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 155292000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 251661500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 406953500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 172926500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 172926500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 157900000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 157900000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 82959000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 82959000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 157900000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 255885500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 413785500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 157900000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 255885500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 413785500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 998 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 998 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 6212 # number of WritebackClean accesses(hits+misses) @@ -532,18 +530,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.340222 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167147 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.943278 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.494398 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.494398 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.478528 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.478528 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59642.543860 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59642.543860 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59565.793326 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59565.793326 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60548.494398 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60548.494398 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60544.478528 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60544.478528 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60642.543860 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60642.543860 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60544.478528 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60578.953598 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60565.793326 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60544.478528 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60578.953598 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60565.793326 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -562,18 +560,18 @@ system.cpu.l2cache.demand_mshr_misses::total 6832 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2608 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4224 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141510500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141510500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129212000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129212000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 67911000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 67911000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129212000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 209421500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 338633500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129212000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 209421500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 338633500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 144366500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 144366500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 131820000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 131820000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 69279000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 69279000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 131820000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 213645500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 345465500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 131820000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 213645500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 345465500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadCleanReq accesses @@ -586,25 +584,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.494398 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.494398 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.478528 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.478528 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50548.494398 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50548.494398 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50544.478528 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50544.478528 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50642.543860 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50642.543860 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50544.478528 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50578.953598 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50565.793326 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50544.478528 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50578.953598 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50565.793326 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution @@ -638,7 +636,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 23404500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 6833 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3976 # Transaction distribution system.membus.trans_dist::ReadExReq 2856 # Transaction distribution system.membus.trans_dist::ReadExResp 2856 # Transaction distribution |