diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
| commit | 2823982a3cbd60a1b21db1a73b78440468df158a (patch) | |
| tree | b955647023da451506138be5a325dfaa2bfd8ee5 /tests/long/se/30.eon | |
| parent | 9fb93e5cd226ca928ef9cd45bcefcbd94649f4ea (diff) | |
| download | gem5-2823982a3cbd60a1b21db1a73b78440468df158a.tar.xz | |
stats: updates due to changes to ticksToCycles()
Diffstat (limited to 'tests/long/se/30.eon')
4 files changed, 840 insertions, 696 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini index 14dada76e..427d7de3e 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,26 +173,31 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -193,16 +206,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -211,22 +227,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -235,22 +255,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -259,10 +283,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -271,124 +297,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -397,10 +444,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -409,16 +458,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -427,10 +479,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -441,6 +495,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -463,17 +518,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -482,6 +541,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -504,12 +564,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -519,6 +581,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -528,7 +591,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 @@ -542,11 +606,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -566,6 +632,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -577,17 +644,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index c079ee28b..68636d517 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.077516 # Nu sim_ticks 77516381000 # Number of ticks simulated final_tick 77516381000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 185827 # Simulator instruction rate (inst/s) -host_op_rate 185827 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38353496 # Simulator tick rate (ticks/s) -host_mem_usage 262456 # Number of bytes of host memory used -host_seconds 2021.10 # Real time elapsed on the host +host_inst_rate 154118 # Simulator instruction rate (inst/s) +host_op_rate 154118 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31808931 # Simulator tick rate (ticks/s) +host_mem_usage 282024 # Number of bytes of host memory used +host_seconds 2436.94 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 221184 # Number of bytes read from this memory @@ -210,14 +210,14 @@ system.physmem.bytesPerActivate::7232-7233 1 0.09% 99.66% # system.physmem.bytesPerActivate::8000-8001 1 0.09% 99.74% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 3 0.26% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1164 # Bytes accessed per row activation -system.physmem.totQLat 59913750 # Total ticks spent queuing -system.physmem.totMemAccLat 199861250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 59914250 # Total ticks spent queuing +system.physmem.totMemAccLat 199861750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37235000 # Total ticks spent in databus transfers system.physmem.totBankLat 102712500 # Total ticks spent accessing banks -system.physmem.avgQLat 8045.35 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8045.42 # Average queueing delay per DRAM burst system.physmem.avgBankLat 13792.47 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26837.82 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26837.89 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.15 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.15 # Average system read bandwidth in MiByte/s @@ -248,15 +248,15 @@ system.membus.data_through_bus 476608 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 9290500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 69563000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 69562000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.branchPred.lookups 50307165 # Number of BP lookups +system.cpu.branchPred.lookups 50307155 # Number of BP lookups system.cpu.branchPred.condPredicted 29267262 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1212205 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26317362 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 26317352 # Number of BTB lookups system.cpu.branchPred.BTBHits 23268236 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.414014 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 88.414047 # BTB Hit Percentage system.cpu.branchPred.usedRAS 9019862 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1049 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits @@ -295,23 +295,23 @@ system.cpu.workload.num_syscalls 215 # Nu system.cpu.numCycles 155032764 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 51194246 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 449183514 # Number of instructions fetch has processed -system.cpu.fetch.Branches 50307165 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 51194259 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 449183474 # Number of instructions fetch has processed +system.cpu.fetch.Branches 50307155 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 32288098 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 78871438 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6172162 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19742012 # Number of cycles fetch has spent blocked +system.cpu.fetch.Cycles 78871433 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6172161 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19742008 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 181 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 10560 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 50297233 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 412893 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 154739148 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 412894 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 154739151 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.902843 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.324835 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 75867710 49.03% 49.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 75867718 49.03% 49.03% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 4287409 2.77% 51.80% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 6889018 4.45% 56.25% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 5374428 3.47% 59.73% # Number of instructions fetched each cycle (Total) @@ -319,24 +319,24 @@ system.cpu.fetch.rateDist::4 11763624 7.60% 67.33% # Nu system.cpu.fetch.rateDist::5 7816659 5.05% 72.38% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 5616009 3.63% 76.01% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 1833388 1.18% 77.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35290903 22.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35290898 22.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154739148 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 154739151 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.324494 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.897346 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 56553427 # Number of cycles decode is idle +system.cpu.fetch.rate 2.897345 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 56553436 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 15088868 # Number of cycles decode is blocked system.cpu.decode.RunCycles 74238964 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3941388 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4916501 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9487391 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4280 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 445247205 # Number of instructions handled by decode +system.cpu.decode.UnblockCycles 3941383 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4916500 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9487386 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4275 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 445247195 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 12161 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4916501 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 59699524 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 4916500 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 59699528 # Number of cycles rename is idle system.cpu.rename.BlockCycles 4890372 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 419538 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 75126102 # Number of cycles rename is running @@ -360,28 +360,28 @@ system.cpu.memDep0.conflictingLoads 8938676 # Nu system.cpu.memDep0.conflictingStores 6410471 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 408405086 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 279 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 401961013 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 974296 # Number of squashed instructions issued +system.cpu.iq.iqInstsIssued 401961016 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 974295 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 32695397 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15321619 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 15321612 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 64 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154739148 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.597669 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 154739151 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.597668 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.996651 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 28425453 18.37% 18.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 28425455 18.37% 18.37% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 25900888 16.74% 35.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25580332 16.53% 51.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25580333 16.53% 51.64% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 24228882 15.66% 67.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21279906 13.75% 81.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15505584 10.02% 91.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21279905 13.75% 81.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15505585 10.02% 91.07% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 8490760 5.49% 96.56% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 3998033 2.58% 99.14% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 1329310 0.86% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154739148 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154739151 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 33873 0.29% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available @@ -412,12 +412,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.09% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5077907 42.90% 74.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5077908 42.90% 74.99% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 2960216 25.01% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 155836210 38.77% 38.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 155836212 38.77% 38.78% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 2126206 0.53% 39.31% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 32826139 8.17% 47.47% # Type of FU issued @@ -446,21 +446,21 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.55% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103415840 25.73% 80.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103415841 25.73% 80.27% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 79289575 19.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 401961013 # Type of FU issued +system.cpu.iq.FU_type_0::total 401961016 # Type of FU issued system.cpu.iq.rate 2.592749 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11837270 # FU busy when requested +system.cpu.iq.fu_busy_cnt 11837271 # FU busy when requested system.cpu.iq.fu_busy_rate 0.029449 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 634505765 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 634505774 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 260497209 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 234812476 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 234812479 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 336966975 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 180652533 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 161419314 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 241576218 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 241576222 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 172188484 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 15052407 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -473,11 +473,11 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 260897 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 3921 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4916501 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 4916500 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 2514816 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 370985 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 433209224 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 130314 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 130318 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 104720393 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 80633883 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 279 # Number of dispatched non-speculative instructions @@ -489,17 +489,17 @@ system.cpu.iew.predictedNotTakenIncorrect 408580 # N system.cpu.iew.branchMispredicts 1365211 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 398393230 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 101955347 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3567783 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 3567786 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 24803859 # number of nop insts executed system.cpu.iew.exec_refs 180422830 # number of memory reference insts executed system.cpu.iew.exec_branches 46575028 # Number of branches executed system.cpu.iew.exec_stores 78467483 # Number of stores executed system.cpu.iew.exec_rate 2.569736 # Inst execution rate -system.cpu.iew.wb_sent 396861812 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 396231790 # cumulative count of insts written-back -system.cpu.iew.wb_producers 193564450 # num instructions producing a value -system.cpu.iew.wb_consumers 271143007 # num instructions consuming a value +system.cpu.iew.wb_sent 396861814 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 396231793 # cumulative count of insts written-back +system.cpu.iew.wb_producers 193564452 # num instructions producing a value +system.cpu.iew.wb_consumers 271143010 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.555794 # insts written-back per cycle system.cpu.iew.wb_fanout 0.713883 # average fanout of values written-back @@ -507,13 +507,13 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 34575269 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1208013 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149822647 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 149822651 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 2.660910 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.995203 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 55444792 37.01% 37.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 22572343 15.07% 52.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13039784 8.70% 60.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 55444795 37.01% 37.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22572345 15.07% 52.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13039783 8.70% 60.78% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 11474023 7.66% 68.43% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 8200661 5.47% 73.91% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 5438800 3.63% 77.54% # Number of insts commited each cycle @@ -523,7 +523,7 @@ system.cpu.commit.committed_per_cycle::8 25200113 16.82% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149822647 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 149822651 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -536,10 +536,10 @@ system.cpu.commit.int_insts 316365839 # Nu system.cpu.commit.function_calls 8007752 # Number of function calls committed. system.cpu.commit.bw_lim_events 25200113 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 557859409 # The number of ROB reads +system.cpu.rob.rob_reads 557859413 # The number of ROB reads system.cpu.rob.rob_writes 871404727 # The number of ROB writes system.cpu.timesIdled 3579 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 293616 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 293613 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated @@ -548,7 +548,7 @@ system.cpu.cpi_total 0.412788 # CP system.cpu.ipc 2.422551 # IPC: Instructions Per Cycle system.cpu.ipc_total 2.422551 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 398219851 # number of integer regfile reads -system.cpu.int_regfile_writes 170183529 # number of integer regfile writes +system.cpu.int_regfile_writes 170183531 # number of integer regfile writes system.cpu.fp_regfile_reads 156589680 # number of floating regfile reads system.cpu.fp_regfile_writes 104065109 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads @@ -575,31 +575,31 @@ system.cpu.toL2Bus.respLayer1.occupancy 6675000 # La system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.icache.tags.replacements 2141 # number of replacements system.cpu.icache.tags.tagsinuse 1831.580097 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 50291613 # Total number of references to valid blocks. +system.cpu.icache.tags.total_refs 50291612 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4069 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12359.698452 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 12359.698206 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 1831.580097 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.894326 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.894326 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 50291613 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 50291613 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 50291613 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 50291613 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 50291613 # number of overall hits -system.cpu.icache.overall_hits::total 50291613 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5620 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5620 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5620 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5620 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5620 # number of overall misses -system.cpu.icache.overall_misses::total 5620 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 330576500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 330576500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 330576500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 330576500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 330576500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 330576500 # number of overall miss cycles +system.cpu.icache.ReadReq_hits::cpu.inst 50291612 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 50291612 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 50291612 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 50291612 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 50291612 # number of overall hits +system.cpu.icache.overall_hits::total 50291612 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5621 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5621 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5621 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5621 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5621 # number of overall misses +system.cpu.icache.overall_misses::total 5621 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 330634250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 330634250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 330634250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 330634250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 330634250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 330634250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 50297233 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 50297233 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 50297233 # number of demand (read+write) accesses @@ -612,12 +612,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000112 system.cpu.icache.demand_miss_rate::total 0.000112 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000112 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000112 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58821.441281 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 58821.441281 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 58821.441281 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 58821.441281 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 58821.441281 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 58821.441281 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58821.250667 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 58821.250667 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 58821.250667 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 58821.250667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 58821.250667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 58821.250667 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 892 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked @@ -626,36 +626,36 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 148.666667 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1551 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1551 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1551 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1551 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1551 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1551 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1552 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1552 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1552 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1552 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1552 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1552 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4069 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 4069 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 4069 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 4069 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4069 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4069 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249127500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 249127500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249127500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 249127500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249127500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 249127500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249126500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 249126500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249126500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 249126500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249126500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 249126500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000081 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000081 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61225.731138 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61225.731138 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61225.731138 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61225.731138 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61225.731138 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61225.731138 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61225.485377 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61225.485377 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61225.485377 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61225.485377 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61225.485377 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61225.485377 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 4006.698259 # Cycle average of tags in use @@ -694,17 +694,17 @@ system.cpu.l2cache.demand_misses::total 7447 # nu system.cpu.l2cache.overall_misses::cpu.inst 3456 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3991 # number of overall misses system.cpu.l2cache.overall_misses::total 7447 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 238916500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 238915500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 66414500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 305331000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 305330000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 225828500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 225828500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 238916500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 238915500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 292243000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 531159500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 238916500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 531158500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 238915500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 292243000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 531159500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 531158500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 4069 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 5061 # number of ReadReq accesses(hits+misses) @@ -729,17 +729,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.902557 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.849349 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.954328 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.902557 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69130.931713 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69130.642361 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77136.469222 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70727.588603 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70727.356961 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72149.680511 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72149.680511 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69130.931713 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69130.642361 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73225.507392 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71325.298778 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69130.931713 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71325.164496 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69130.642361 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73225.507392 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71325.298778 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71325.164496 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index dd0636ebe..8cc45b24c 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,18 +173,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -202,16 +216,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -220,22 +237,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -244,22 +265,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -268,10 +293,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -280,124 +307,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -406,10 +454,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -418,16 +468,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -436,10 +489,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -450,6 +505,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -472,14 +528,17 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -498,12 +557,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -514,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -536,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -560,7 +625,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/eon +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 @@ -574,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -598,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -609,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 93aa60ef6..356503ef7 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068515 # Number of seconds simulated -sim_ticks 68515366500 # Number of ticks simulated -final_tick 68515366500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.068510 # Number of seconds simulated +sim_ticks 68509635500 # Number of ticks simulated +final_tick 68509635500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128186 # Simulator instruction rate (inst/s) -host_op_rate 163879 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32166693 # Simulator tick rate (ticks/s) -host_mem_usage 283052 # Number of bytes of host memory used -host_seconds 2130.01 # Real time elapsed on the host +host_inst_rate 105106 # Simulator instruction rate (inst/s) +host_op_rate 134373 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26372946 # Simulator tick rate (ticks/s) +host_mem_usage 303620 # Number of bytes of host memory used +host_seconds 2597.72 # Real time elapsed on the host sim_insts 273036725 # Number of instructions simulated sim_ops 349064449 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 194304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272128 # Number of bytes read from this memory -system.physmem.bytes_read::total 466432 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 194304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 194304 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3036 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4252 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7288 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2835919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3971781 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6807699 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2835919 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2835919 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2835919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3971781 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6807699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7289 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 194560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272384 # Number of bytes read from this memory +system.physmem.bytes_read::total 466944 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 194560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 194560 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3040 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4256 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7296 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2839892 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3975849 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6815742 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2839892 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2839892 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2839892 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3975849 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6815742 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7296 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7289 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7296 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 466496 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 466944 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 466496 # Total read bytes from the system interface side +system.physmem.bytesReadSys 466944 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -43,13 +43,13 @@ system.physmem.perBankRdBursts::0 607 # Pe system.physmem.perBankRdBursts::1 801 # Per bank write bursts system.physmem.perBankRdBursts::2 608 # Per bank write bursts system.physmem.perBankRdBursts::3 526 # Per bank write bursts -system.physmem.perBankRdBursts::4 443 # Per bank write bursts -system.physmem.perBankRdBursts::5 353 # Per bank write bursts -system.physmem.perBankRdBursts::6 161 # Per bank write bursts -system.physmem.perBankRdBursts::7 217 # Per bank write bursts +system.physmem.perBankRdBursts::4 444 # Per bank write bursts +system.physmem.perBankRdBursts::5 356 # Per bank write bursts +system.physmem.perBankRdBursts::6 162 # Per bank write bursts +system.physmem.perBankRdBursts::7 220 # Per bank write bursts system.physmem.perBankRdBursts::8 207 # Per bank write bursts system.physmem.perBankRdBursts::9 294 # Per bank write bursts -system.physmem.perBankRdBursts::10 325 # Per bank write bursts +system.physmem.perBankRdBursts::10 324 # Per bank write bursts system.physmem.perBankRdBursts::11 416 # Per bank write bursts system.physmem.perBankRdBursts::12 529 # Per bank write bursts system.physmem.perBankRdBursts::13 687 # Per bank write bursts @@ -73,14 +73,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 68515346000 # Total gap between requests +system.physmem.totGap 68509447000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7289 # Read request sizes (log2) +system.physmem.readPktSize::6 7296 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -88,9 +88,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 569 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 570 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 177 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -152,80 +152,80 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1271 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 365.973249 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 166.155512 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 760.469459 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 520 40.91% 40.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 218 17.15% 58.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 133 10.46% 68.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 73 5.74% 74.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 41 3.23% 77.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 37 2.91% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 29 2.28% 82.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 36 2.83% 85.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 15 1.18% 86.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 25 1.97% 88.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 5 0.39% 89.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 14 1.10% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 4 0.31% 90.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 8 0.63% 91.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 5 0.39% 91.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 8 0.63% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 8 0.63% 92.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 6 0.47% 93.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 5 0.39% 93.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 7 0.55% 94.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 2 0.16% 94.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 5 0.39% 94.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 5 0.39% 95.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 2 0.16% 95.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.24% 95.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 3 0.24% 95.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 3 0.24% 95.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 2 0.16% 96.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 2 0.16% 96.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 4 0.31% 96.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 4 0.31% 96.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 3 0.24% 97.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.08% 97.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 2 0.16% 97.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.08% 97.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 2 0.16% 97.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.08% 97.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.08% 97.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.08% 97.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 2 0.16% 98.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.08% 98.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 2 0.16% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.08% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 2 0.16% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.08% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 2 0.16% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.08% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.16% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 1 0.08% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 1 0.08% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 3 0.24% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 1278 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 364.419405 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 165.521659 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 755.556461 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 528 41.31% 41.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 217 16.98% 58.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 132 10.33% 68.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 73 5.71% 74.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 38 2.97% 77.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 36 2.82% 80.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 30 2.35% 82.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 40 3.13% 85.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 15 1.17% 86.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 24 1.88% 88.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 7 0.55% 89.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 13 1.02% 90.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 4 0.31% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 10 0.78% 91.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 5 0.39% 91.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 6 0.47% 92.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 7 0.55% 92.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 7 0.55% 93.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 3 0.23% 93.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 4 0.31% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 3 0.23% 94.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 6 0.47% 94.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 5 0.39% 94.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 5 0.39% 95.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 2 0.16% 95.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 5 0.39% 95.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 4 0.31% 96.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 2 0.16% 96.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 2 0.16% 96.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 3 0.23% 96.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 4 0.31% 97.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 2 0.16% 97.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.08% 97.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 2 0.16% 97.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.08% 97.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 2 0.16% 97.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.08% 97.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.08% 97.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.08% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 2 0.16% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.08% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 2 0.16% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 2 0.16% 98.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 2 0.16% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.08% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 2 0.16% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.08% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.08% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.08% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 1 0.08% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 3 0.23% 99.45% # Bytes accessed per row activation system.physmem.bytesPerActivate::4736-4737 1 0.08% 99.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::6464-6465 1 0.08% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::6528-6529 1 0.08% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.08% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.08% 99.77% # Bytes accessed per row activation system.physmem.bytesPerActivate::7552-7553 1 0.08% 99.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 2 0.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1271 # Bytes accessed per row activation -system.physmem.totQLat 60705750 # Total ticks spent queuing -system.physmem.totMemAccLat 196384500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 36445000 # Total ticks spent in databus transfers -system.physmem.totBankLat 99233750 # Total ticks spent accessing banks -system.physmem.avgQLat 8328.41 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13614.18 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::total 1278 # Bytes accessed per row activation +system.physmem.totQLat 61296000 # Total ticks spent queuing +system.physmem.totMemAccLat 197202250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36480000 # Total ticks spent in databus transfers +system.physmem.totBankLat 99426250 # Total ticks spent accessing banks +system.physmem.avgQLat 8401.32 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13627.50 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26942.58 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27028.82 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.82 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.81 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.82 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage @@ -235,37 +235,37 @@ system.physmem.avgRdQLen 0.00 # Av system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 6018 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.56 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.48 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9399827.96 # Average gap between requests -system.physmem.pageHitRate 82.56 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.15 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 6807699 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4464 # Transaction distribution -system.membus.trans_dist::ReadResp 4463 # Transaction distribution +system.physmem.avgGap 9390000.96 # Average gap between requests +system.physmem.pageHitRate 82.48 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.14 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 6815742 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4471 # Transaction distribution +system.membus.trans_dist::ReadResp 4471 # Transaction distribution system.membus.trans_dist::UpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::ReadExReq 2825 # Transaction distribution system.membus.trans_dist::ReadExResp 2825 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14581 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14581 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 466432 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 466432 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14596 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14596 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466944 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 466944 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 466944 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8930000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8937500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 67824498 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 67899498 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.branchPred.lookups 35429100 # Number of BP lookups -system.cpu.branchPred.condPredicted 21225812 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1661684 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19625450 # Number of BTB lookups -system.cpu.branchPred.BTBHits 16825398 # Number of BTB hits +system.cpu.branchPred.lookups 35425567 # Number of BP lookups +system.cpu.branchPred.condPredicted 21222314 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1660593 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19605313 # Number of BTB lookups +system.cpu.branchPred.BTBHits 16823422 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 85.732546 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6780528 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 8438 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 85.810525 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6781780 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 8434 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -309,100 +309,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 137030734 # number of cpu cycles simulated +system.cpu.numCycles 137019272 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39012994 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 318080298 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35429100 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23605926 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70957862 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6891670 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 21493708 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 111 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1614 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 39008530 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 318058207 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35425567 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23605202 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70950828 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6887573 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 21494775 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 105 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1573 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 61 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37614130 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 516506 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 136684696 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.983709 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.454255 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 37609299 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 515132 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 136671204 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.983776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.454359 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66359879 48.55% 48.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6789497 4.97% 53.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5708838 4.18% 57.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6107274 4.47% 62.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4922167 3.60% 65.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4085695 2.99% 68.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3186230 2.33% 71.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4137086 3.03% 74.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35388030 25.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66353464 48.55% 48.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6794042 4.97% 53.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5704725 4.17% 57.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6102503 4.47% 62.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4920388 3.60% 65.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4084365 2.99% 68.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3186134 2.33% 71.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4139625 3.03% 74.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35385958 25.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 136684696 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258549 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.321233 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45532866 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16645865 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 66825856 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2530463 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5149646 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7344267 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 69062 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401846627 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 213953 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5149646 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 51082336 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1907734 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 332489 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 63745566 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14466925 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 394259426 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 53 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1660076 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10182958 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1156 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 432806895 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2333828888 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1575589736 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 200458039 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 136671204 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258544 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.321266 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45524127 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16648036 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 66820925 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2531461 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5146655 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7342433 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69027 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401839978 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 214083 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5146655 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 51074305 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1910036 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 332499 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 63741314 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14466395 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 394244633 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 55 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1658642 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10186296 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1132 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 432779208 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2333721873 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1575557795 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 200430073 # Number of floating rename lookups system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 48240702 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 48213015 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 11816 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 11815 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 36507596 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 103616420 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 91395607 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4296163 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5310753 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 384620101 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22788 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 374263749 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1212133 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 34826495 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 87778881 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 668 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 136684696 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.738154 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.024883 # Number of insts issued each cycle +system.cpu.rename.skidInsts 36510705 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 103606610 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 91402094 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4304684 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5331956 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 384603029 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22794 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 374241110 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1211414 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 34812310 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 87759919 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 674 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 136671204 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.738259 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.024772 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 25139035 18.39% 18.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19926957 14.58% 32.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20565636 15.05% 48.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18170176 13.29% 61.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24039516 17.59% 78.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15735356 11.51% 90.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8814568 6.45% 96.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3374876 2.47% 99.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 918576 0.67% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 25129949 18.39% 18.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19927179 14.58% 32.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20562891 15.05% 48.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18173263 13.30% 61.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 24036101 17.59% 78.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15736190 11.51% 90.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8814920 6.45% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3372202 2.47% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 918509 0.67% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 136684696 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 136671204 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8700 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4687 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8708 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4694 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -421,22 +421,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 46352 0.26% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 46360 0.26% 0.34% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7624 0.04% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 437 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7648 0.04% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 433 0.00% 0.38% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 190912 1.08% 1.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 4399 0.02% 1.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 241386 1.36% 2.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 190801 1.08% 1.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 4328 0.02% 1.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241338 1.36% 2.85% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9273710 52.31% 55.15% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7950548 44.85% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9265240 52.28% 55.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7952555 44.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 126477598 33.79% 33.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2175809 0.58% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 126474576 33.79% 33.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2175710 0.58% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.38% # Type of FU issued @@ -455,93 +455,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.38% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6782032 1.81% 36.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6781686 1.81% 36.19% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8476848 2.26% 38.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3430270 0.92% 39.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1595622 0.43% 39.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20869694 5.58% 45.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7174273 1.92% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7130259 1.91% 49.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8476200 2.26% 38.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3430464 0.92% 39.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1596092 0.43% 39.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20867035 5.58% 45.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7174148 1.92% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7130628 1.91% 49.19% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101673859 27.17% 76.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88302195 23.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101661693 27.16% 76.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88297588 23.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 374263749 # Type of FU issued -system.cpu.iq.rate 2.731239 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17728757 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047370 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654715892 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 289089659 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 250133425 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 249437192 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 130393861 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118075733 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 263363212 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 128629294 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11082647 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 374241110 # Type of FU issued +system.cpu.iq.rate 2.731303 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17722107 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047355 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654665747 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 289075917 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 250124446 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249421198 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 130376340 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118073548 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 263342959 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128620258 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11085750 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 8967672 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 108753 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14263 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9020024 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8957862 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 109225 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14255 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9026511 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 174668 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1902 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 173986 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1905 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5149646 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 272927 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 35696 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 384644450 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 871710 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 103616420 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 91395607 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11754 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 342 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 5146655 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 274797 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 35672 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 384627381 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 873173 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 103606610 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 91402094 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11760 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 340 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 365 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14263 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1301323 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 370771 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1672094 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 370296137 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100380791 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3967612 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 14255 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1300817 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 370830 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1671647 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 370280641 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100372061 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3960469 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1561 # number of nop insts executed -system.cpu.iew.exec_refs 187597519 # number of memory reference insts executed -system.cpu.iew.exec_branches 32011770 # Number of branches executed -system.cpu.iew.exec_stores 87216728 # Number of stores executed -system.cpu.iew.exec_rate 2.702285 # Inst execution rate -system.cpu.iew.wb_sent 368879898 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 368209158 # cumulative count of insts written-back -system.cpu.iew.wb_producers 183085663 # num instructions producing a value -system.cpu.iew.wb_consumers 363859128 # num instructions consuming a value +system.cpu.iew.exec_nop 1558 # number of nop insts executed +system.cpu.iew.exec_refs 187586293 # number of memory reference insts executed +system.cpu.iew.exec_branches 32011507 # Number of branches executed +system.cpu.iew.exec_stores 87214232 # Number of stores executed +system.cpu.iew.exec_rate 2.702398 # Inst execution rate +system.cpu.iew.wb_sent 368867964 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 368197994 # cumulative count of insts written-back +system.cpu.iew.wb_producers 183086265 # num instructions producing a value +system.cpu.iew.wb_consumers 363871713 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.687055 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.503177 # average fanout of values written-back +system.cpu.iew.wb_rate 2.687199 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.503162 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 35579507 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 35562440 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1592984 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 131535050 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.653780 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.659242 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1591916 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 131524549 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.653992 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.659233 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 34731076 26.40% 26.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 28455457 21.63% 48.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13342482 10.14% 58.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11433888 8.69% 66.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13770355 10.47% 77.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7412668 5.64% 82.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3873056 2.94% 85.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3888664 2.96% 88.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14627404 11.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34720675 26.40% 26.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 28457654 21.64% 48.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13339371 10.14% 58.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11431101 8.69% 66.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13773309 10.47% 77.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7413510 5.64% 82.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3874860 2.95% 85.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3887136 2.96% 88.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14626933 11.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 131535050 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 131524549 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037337 # Number of instructions committed system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -552,220 +552,220 @@ system.cpu.commit.branches 30563497 # Nu system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14627404 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14626933 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 501549691 # The number of ROB reads -system.cpu.rob.rob_writes 774443009 # The number of ROB writes -system.cpu.timesIdled 6642 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 346038 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 501522594 # The number of ROB reads +system.cpu.rob.rob_writes 774405807 # The number of ROB writes +system.cpu.timesIdled 6645 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 348068 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273036725 # Number of Instructions Simulated system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated -system.cpu.cpi 0.501877 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.501877 # CPI: Total CPI of All Threads -system.cpu.ipc 1.992522 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.992522 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1770065591 # number of integer regfile reads -system.cpu.int_regfile_writes 233053939 # number of integer regfile writes -system.cpu.fp_regfile_reads 188169392 # number of floating regfile reads -system.cpu.fp_regfile_writes 132536105 # number of floating regfile writes -system.cpu.misc_regfile_reads 566956802 # number of misc regfile reads +system.cpu.cpi 0.501835 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.501835 # CPI: Total CPI of All Threads +system.cpu.ipc 1.992688 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.992688 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1769988396 # number of integer regfile reads +system.cpu.int_regfile_writes 233047297 # number of integer regfile writes +system.cpu.fp_regfile_reads 188164665 # number of floating regfile reads +system.cpu.fp_regfile_writes 132532739 # number of floating regfile writes +system.cpu.misc_regfile_reads 566941334 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.toL2Bus.throughput 20102702 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 17643 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 17642 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1037 # Transaction distribution +system.cpu.toL2Bus.throughput 20093174 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 17631 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 17631 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1036 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2842 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2842 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31749 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10257 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 42006 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1015808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 1377088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 1377088 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31714 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10268 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 41982 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1014720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 1376320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 1376320 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 11799000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 11791500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24347988 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24322738 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7401462 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7408962 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 13986 # number of replacements -system.cpu.icache.tags.tagsinuse 1848.638823 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 37596770 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15875 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 2368.300472 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 13968 # number of replacements +system.cpu.icache.tags.tagsinuse 1848.251388 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 37591948 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15858 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2370.535250 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1848.638823 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.902656 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.902656 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 37596770 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37596770 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37596770 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37596770 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37596770 # number of overall hits -system.cpu.icache.overall_hits::total 37596770 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17358 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17358 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17358 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17358 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17358 # number of overall misses -system.cpu.icache.overall_misses::total 17358 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 450239984 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 450239984 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 450239984 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 450239984 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 450239984 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 450239984 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37614128 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37614128 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37614128 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37614128 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37614128 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37614128 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1848.251388 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.902466 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.902466 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37591948 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37591948 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37591948 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37591948 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37591948 # number of overall hits +system.cpu.icache.overall_hits::total 37591948 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17349 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17349 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17349 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17349 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17349 # number of overall misses +system.cpu.icache.overall_misses::total 17349 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 451171984 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 451171984 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 451171984 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 451171984 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 451171984 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 451171984 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37609297 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37609297 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37609297 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37609297 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37609297 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37609297 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000461 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000461 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000461 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000461 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000461 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000461 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25938.471252 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25938.471252 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25938.471252 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25938.471252 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25938.471252 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25938.471252 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2006 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26005.647818 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 26005.647818 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 26005.647818 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 26005.647818 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 26005.647818 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 26005.647818 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2002 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 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ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 164645000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176465000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 252777000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 429242000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176465000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 252777000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 429242000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191331 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.808041 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253076 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 165233500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 165233500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176370000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 254119500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 430489500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176370000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 254119500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 430489500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191738 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.807562 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253645 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994018 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994018 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191331 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922743 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.355891 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191331 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922743 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.355891 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58105.037866 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61760.336370 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59273.521505 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191738 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922410 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.356441 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191738 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922410 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.356441 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58016.447368 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62114.605171 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59328.114516 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58281.415929 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58281.415929 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58105.037866 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59448.965193 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58889.010838 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58105.037866 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59448.965193 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58889.010838 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58489.734513 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58489.734513 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58016.447368 # average overall mshr miss latency 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number of references to valid blocks. +system.cpu.dcache.tags.replacements 1417 # number of replacements +system.cpu.dcache.tags.tagsinuse 3102.941006 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 170982340 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4614 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37057.290854 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3101.535581 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.757211 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.757211 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88940583 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88940583 # number of ReadReq hits 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system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 170971964 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 170971964 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 170971964 # number of overall hits -system.cpu.dcache.overall_hits::total 170971964 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3947 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3947 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 170960424 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 170960424 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 170960424 # number of overall hits +system.cpu.dcache.overall_hits::total 170960424 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3956 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3956 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 21284 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 21284 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25231 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25231 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25231 # number of overall misses -system.cpu.dcache.overall_misses::total 25231 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 233964205 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 233964205 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1259611139 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1259611139 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 25240 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25240 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25240 # number of overall misses +system.cpu.dcache.overall_misses::total 25240 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 235586955 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 235586955 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1260992389 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1260992389 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170250 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 170250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1493575344 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1493575344 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1493575344 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1493575344 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88944530 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88944530 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 1496579344 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1496579344 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1496579344 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1496579344 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88932999 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88932999 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11005 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11005 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11011 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11011 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 170997195 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 170997195 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 170997195 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 170997195 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 170985664 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 170985664 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 170985664 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 170985664 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000044 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000259 # miss rate for WriteReq accesses @@ -899,52 +899,52 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000148 system.cpu.dcache.demand_miss_rate::total 0.000148 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000148 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000148 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59276.464403 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59276.464403 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59181.128500 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59181.128500 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59551.808645 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59551.808645 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59246.024666 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59246.024666 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59196.042329 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59196.042329 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59196.042329 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59196.042329 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 28298 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59293.951823 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59293.951823 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59293.951823 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59293.951823 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 28312 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1224 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 410 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 411 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.019512 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 68.885645 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 102 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1037 # number of writebacks -system.cpu.dcache.writebacks::total 1037 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2179 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2179 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1036 # number of writebacks +system.cpu.dcache.writebacks::total 1036 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2182 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2182 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18442 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 18442 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20621 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20621 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20621 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20621 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1768 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1768 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 20624 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20624 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20624 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20624 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1774 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1774 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2842 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 2842 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4610 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4610 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4610 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4610 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 113556540 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 113556540 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 202620998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 202620998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 316177538 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 316177538 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 316177538 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 316177538 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 4616 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4616 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4616 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4616 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 114384040 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 114384040 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 203208498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 203208498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 317592538 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 317592538 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 317592538 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 317592538 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -953,14 +953,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64228.812217 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64228.812217 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71295.213934 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71295.213934 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68585.149241 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68585.149241 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68585.149241 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68585.149241 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64478.038331 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64478.038331 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71501.934553 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71501.934553 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68802.542894 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68802.542894 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68802.542894 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68802.542894 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |