diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
| commit | 8b4b1dcb86b0799a8c32056427581a8b6249a3bf (patch) | |
| tree | 96016b415513dc6c2c29877e1a76220e0edae629 /tests/long/se/30.eon | |
| parent | a00383a40aeb8347af7e05f3966ab141484921a5 (diff) | |
| download | gem5-8b4b1dcb86b0799a8c32056427581a8b6249a3bf.tar.xz | |
stats: Update stats for DRAM changes
This patch updates the stats to reflect the changes to the DRAM
controller.
Diffstat (limited to 'tests/long/se/30.eon')
| -rw-r--r-- | tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt | 545 | ||||
| -rw-r--r-- | tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt | 1300 | ||||
| -rw-r--r-- | tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt | 1382 |
3 files changed, 1579 insertions, 1648 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index eb5995295..4b6099b52 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.139926 # Nu sim_ticks 139926186500 # Number of ticks simulated final_tick 139926186500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 138827 # Simulator instruction rate (inst/s) -host_op_rate 138827 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48726388 # Simulator tick rate (ticks/s) -host_mem_usage 236592 # Number of bytes of host memory used -host_seconds 2871.67 # Real time elapsed on the host +host_inst_rate 124689 # Simulator instruction rate (inst/s) +host_op_rate 124689 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43764124 # Simulator tick rate (ticks/s) +host_mem_usage 271420 # Number of bytes of host memory used +host_seconds 3197.28 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1820 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 581 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 229 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4589 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1831 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -154,79 +154,60 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1198 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 387.899833 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 185.568922 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 772.018563 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 419 34.97% 34.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 201 16.78% 51.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 128 10.68% 62.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 91 7.60% 70.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 61 5.09% 75.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 40 3.34% 78.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 30 2.50% 80.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 22 1.84% 82.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 25 2.09% 84.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 18 1.50% 86.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 20 1.67% 88.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 8 0.67% 88.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 17 1.42% 90.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 10 0.83% 90.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 8 0.67% 91.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 6 0.50% 92.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 10 0.83% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 7 0.58% 93.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 7 0.58% 94.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 1 0.08% 94.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 4 0.33% 94.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 4 0.33% 94.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 2 0.17% 95.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 5 0.42% 95.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 5 0.42% 95.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 4 0.33% 96.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 1 0.08% 96.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 2 0.17% 96.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 1 0.08% 96.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 2 0.17% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 1 0.08% 96.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 2 0.17% 96.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.08% 97.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 2 0.17% 97.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.08% 97.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.08% 97.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 4 0.33% 97.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 2 0.17% 98.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.08% 98.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 2 0.17% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.08% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.08% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 1 0.08% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 2 0.17% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.08% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.08% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.08% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.08% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.08% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.08% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.08% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 1 0.08% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 1 0.08% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 1 0.08% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 1 0.08% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 1 0.08% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.08% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 1 0.08% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 2 0.17% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1198 # Bytes accessed per row activation -system.physmem.totQLat 59880500 # Total ticks spent queuing -system.physmem.totMemAccLat 197624250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 558 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 480.917563 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 280.270360 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.877438 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 147 26.34% 26.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 107 19.18% 45.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 50 8.96% 54.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 28 5.02% 59.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15 2.69% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 15 2.69% 64.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7 1.25% 66.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5 0.90% 67.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 184 32.97% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 558 # Bytes accessed per row activation +system.physmem.totQLat 59527000 # Total ticks spent queuing +system.physmem.totMemAccLat 199924500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 36640000 # Total ticks spent in databus transfers -system.physmem.totBankLat 101103750 # Total ticks spent accessing banks -system.physmem.avgQLat 8171.47 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13796.91 # Average bank access latency per DRAM burst +system.physmem.totBankLat 103757500 # Total ticks spent accessing banks +system.physmem.avgQLat 8123.23 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14159.05 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26968.37 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27282.27 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.35 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.35 # Average system read bandwidth in MiByte/s @@ -235,15 +216,15 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6130 # Number of row buffer hits during reads +system.physmem.readRowHits 5962 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.65 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.36 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 19094720.66 # Average gap between requests -system.physmem.pageHitRate 83.65 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.42 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.pageHitRate 81.36 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.43 # Percentage of time for which DRAM has all the banks in precharge state system.membus.throughput 3351710 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 4183 # Transaction distribution system.membus.trans_dist::ReadResp 4183 # Transaction distribution @@ -257,7 +238,7 @@ system.membus.data_through_bus 468992 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 8743500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 68145750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 68133000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 53489673 # Number of BP lookups @@ -273,22 +254,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 94754637 # DTB read hits +system.cpu.dtb.read_hits 94754639 # DTB read hits system.cpu.dtb.read_misses 21 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 94754658 # DTB read accesses -system.cpu.dtb.write_hits 73521124 # DTB write hits +system.cpu.dtb.read_accesses 94754660 # DTB read accesses +system.cpu.dtb.write_hits 73521131 # DTB write hits system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73521159 # DTB write accesses -system.cpu.dtb.data_hits 168275761 # DTB hits +system.cpu.dtb.write_accesses 73521166 # DTB write accesses +system.cpu.dtb.data_hits 168275770 # DTB hits system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168275817 # DTB accesses -system.cpu.itb.fetch_hits 48611324 # ITB hits +system.cpu.dtb.data_accesses 168275826 # DTB accesses +system.cpu.itb.fetch_hits 48611322 # ITB hits system.cpu.itb.fetch_misses 44520 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 48655844 # ITB accesses +system.cpu.itb.fetch_accesses 48655842 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -307,13 +288,13 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 29230505 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 24259168 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 280386579 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 280386572 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 439722438 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 119631950 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 439722431 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 119631955 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 219828431 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100484574 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.floatRegFileAccesses 219828436 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 100484576 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 168485322 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken). @@ -324,12 +305,12 @@ system.cpu.execution_unit.executions 205475782 # Nu system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 279400617 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 279400810 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7206 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13545708 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 266306666 # Number of cycles cpu stages are processed. -system.cpu.activity 95.159695 # Percentage of cycles cpu is active +system.cpu.timesIdled 7266 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13545705 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 266306669 # Number of cycles cpu stages are processed. +system.cpu.activity 95.159696 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -350,27 +331,27 @@ system.cpu.ipc_total 1.424553 # IP system.cpu.stage0.idleCycles 78104700 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 201747674 # Number of cycles 1+ instructions are processed. system.cpu.stage0.utilization 72.090750 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 107200641 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 172651733 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.693860 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 107200637 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 172651737 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 61.693862 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage2.idleCycles 102637143 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 177215231 # Number of cycles 1+ instructions are processed. system.cpu.stage2.utilization 63.324541 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 181107759 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 98744615 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 35.284537 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 90384394 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 189467980 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.702831 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 181107747 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 98744627 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 35.284541 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 90384400 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 189467974 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 67.702829 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 1975 # number of replacements -system.cpu.icache.tags.tagsinuse 1830.939408 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 48606790 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1830.934233 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 48606787 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3903 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12453.699718 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 12453.698950 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1830.939408 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.894013 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.894013 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1830.934233 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894011 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894011 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1928 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id @@ -378,44 +359,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 322 system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1366 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 97226551 # Number of tag accesses -system.cpu.icache.tags.data_accesses 97226551 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 48606790 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 48606790 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 48606790 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 48606790 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 48606790 # number of overall hits -system.cpu.icache.overall_hits::total 48606790 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4534 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4534 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4534 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4534 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4534 # number of overall misses -system.cpu.icache.overall_misses::total 4534 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 280061250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 280061250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 280061250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 280061250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 280061250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 280061250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 48611324 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 48611324 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 48611324 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 48611324 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 48611324 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 48611324 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 97226547 # Number of tag accesses +system.cpu.icache.tags.data_accesses 97226547 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 48606787 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 48606787 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 48606787 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 48606787 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 48606787 # number of overall hits +system.cpu.icache.overall_hits::total 48606787 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4535 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4535 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4535 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4535 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4535 # number of overall misses +system.cpu.icache.overall_misses::total 4535 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 279787250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 279787250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 279787250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 279787250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 279787250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 279787250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 48611322 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 48611322 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 48611322 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 48611322 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 48611322 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 48611322 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61769.133216 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61769.133216 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61769.133216 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61769.133216 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61769.133216 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61769.133216 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61695.093716 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61695.093716 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61695.093716 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61695.093716 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61695.093716 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61695.093716 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 330 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -424,36 +405,36 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 110 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 631 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 631 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 631 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 631 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 631 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 631 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 632 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 632 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 632 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 632 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 632 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 632 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3903 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 3903 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 3903 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 3903 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3903 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3903 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 244179750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 244179750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 244179750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 244179750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 244179750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 244179750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243875500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 243875500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243875500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 243875500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243875500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 243875500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62562.067640 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62562.067640 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62562.067640 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 62562.067640 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62562.067640 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 62562.067640 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62484.114783 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62484.114783 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62484.114783 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 62484.114783 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62484.114783 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 62484.114783 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.throughput 3981070 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 4850 # Transaction distribution @@ -471,21 +452,21 @@ system.cpu.toL2Bus.data_through_bus 557056 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 5001000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6459750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6445500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6671999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6649999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3906.845611 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3906.832917 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 753 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4717 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.159635 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 370.534640 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.739390 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 627.571581 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 370.533355 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.730052 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 627.569510 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088768 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088767 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.019152 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.119227 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 4717 # Occupied blocks per task id @@ -520,17 +501,17 @@ system.cpu.l2cache.demand_misses::total 7328 # nu system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7328 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 234790750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 62080250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 296871000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 227075250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 227075250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 234790750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 289155500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 523946250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 234790750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 289155500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 523946250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 234486500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61133000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 295619500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 230289500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 230289500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 234486500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 291422500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 525909000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 234486500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 291422500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 525909000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3903 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4850 # number of ReadReq accesses(hits+misses) @@ -555,17 +536,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.909745 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.860620 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.909745 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69899.002679 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75340.109223 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70970.834329 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72201.987281 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72201.987281 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69899.002679 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72853.489544 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71499.215338 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69899.002679 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72853.489544 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71499.215338 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69808.425127 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74190.533981 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70671.647143 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73224.006359 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73224.006359 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69808.425127 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73424.666163 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71767.057860 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69808.425127 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73424.666163 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71767.057860 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -585,17 +566,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7328 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 192686250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 51812250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 244498500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 188269250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 188269250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192686250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 240081500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 432767750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192686250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 240081500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 432767750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 192420000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 50867000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 243287000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 191492500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 191492500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192420000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 242359500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 434779500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192420000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 242359500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 434779500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses @@ -607,27 +588,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57364.170884 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62878.944175 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58450.513985 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59863.036566 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59863.036566 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57364.170884 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60489.166037 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59056.734443 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57364.170884 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60489.166037 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59056.734443 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57284.906222 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61731.796117 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58160.889314 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60887.917329 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60887.917329 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57284.906222 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61063.114135 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59331.263646 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57284.906222 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61063.114135 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59331.263646 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 764 # number of replacements -system.cpu.dcache.tags.tagsinuse 3284.890275 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168254255 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3284.879976 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168254239 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40523.664499 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40523.660645 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3284.890275 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.801975 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.801975 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3284.879976 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.801973 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.801973 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id @@ -639,28 +620,28 @@ system.cpu.dcache.tags.tag_accesses 336554588 # Nu system.cpu.dcache.tags.data_accesses 336554588 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 94753181 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753181 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501074 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501074 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168254255 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168254255 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168254255 # number of overall hits -system.cpu.dcache.overall_hits::total 168254255 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501058 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501058 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168254239 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168254239 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168254239 # number of overall hits +system.cpu.dcache.overall_hits::total 168254239 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1308 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1308 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19655 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19655 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 20963 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20963 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 20963 # number of overall misses -system.cpu.dcache.overall_misses::total 20963 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88453749 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88453749 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1129220750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1129220750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1217674499 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1217674499 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1217674499 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1217674499 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 19671 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19671 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 20979 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20979 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 20979 # number of overall misses +system.cpu.dcache.overall_misses::total 20979 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 87087749 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 87087749 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1166784250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1166784250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1253871999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1253871999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1253871999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1253871999 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -671,25 +652,25 @@ system.cpu.dcache.overall_accesses::cpu.data 168275218 system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000014 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000267 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000267 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000268 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000268 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000125 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000125 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000125 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000125 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67625.190367 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67625.190367 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57452.085983 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57452.085983 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 58086.843438 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 58086.843438 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 58086.843438 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 58086.843438 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 33688 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66580.847859 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66580.847859 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59314.943318 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59314.943318 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59767.958387 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59767.958387 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59767.958387 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59767.958387 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33117 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 584 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 591 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.684932 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 56.035533 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -697,12 +678,12 @@ system.cpu.dcache.writebacks::writebacks 649 # nu system.cpu.dcache.writebacks::total 649 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 358 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 358 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16453 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16453 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 16811 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 16811 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 16811 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 16811 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16469 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16469 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16827 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16827 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16827 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16827 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses @@ -711,14 +692,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 64535001 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 64535001 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 230815000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 230815000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 295350001 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 295350001 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 295350001 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 295350001 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 63587751 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 63587751 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 234030250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 234030250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 297618001 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 297618001 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 297618001 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 297618001 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -727,14 +708,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67931.580000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67931.580000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72084.634603 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72084.634603 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71134.393304 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71134.393304 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71134.393304 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71134.393304 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66934.474737 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66934.474737 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73088.772642 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73088.772642 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71680.636079 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71680.636079 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71680.636079 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71680.636079 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 39e558e65..8d6cbc006 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.077516 # Number of seconds simulated -sim_ticks 77516381000 # Number of ticks simulated -final_tick 77516381000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.077418 # Number of seconds simulated +sim_ticks 77417500000 # Number of ticks simulated +final_tick 77417500000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 222910 # Simulator instruction rate (inst/s) -host_op_rate 222910 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46007212 # Simulator tick rate (ticks/s) -host_mem_usage 236600 # Number of bytes of host memory used -host_seconds 1684.87 # Real time elapsed on the host +host_inst_rate 187521 # Simulator instruction rate (inst/s) +host_op_rate 187521 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38653802 # Simulator tick rate (ticks/s) +host_mem_usage 273448 # Number of bytes of host memory used +host_seconds 2002.84 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 221184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255424 # Number of bytes read from this memory -system.physmem.bytes_read::total 476608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221184 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3456 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3991 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7447 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2853384 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3295097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6148481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2853384 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2853384 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2853384 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3295097 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6148481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7447 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 220992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255488 # Number of bytes read from this memory +system.physmem.bytes_read::total 476480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 220992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220992 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3453 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3992 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7445 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2854548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3300132 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6154681 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2854548 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2854548 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2854548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3300132 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6154681 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7445 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7447 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7445 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 476608 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 476480 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 476608 # Total read bytes from the system interface side +system.physmem.bytesReadSys 476480 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 524 # Per bank write bursts -system.physmem.perBankRdBursts::1 653 # Per bank write bursts +system.physmem.perBankRdBursts::1 654 # Per bank write bursts system.physmem.perBankRdBursts::2 449 # Per bank write bursts system.physmem.perBankRdBursts::3 600 # Per bank write bursts system.physmem.perBankRdBursts::4 447 # Per bank write bursts system.physmem.perBankRdBursts::5 455 # Per bank write bursts -system.physmem.perBankRdBursts::6 515 # Per bank write bursts +system.physmem.perBankRdBursts::6 518 # Per bank write bursts system.physmem.perBankRdBursts::7 524 # Per bank write bursts -system.physmem.perBankRdBursts::8 439 # Per bank write bursts -system.physmem.perBankRdBursts::9 407 # Per bank write bursts -system.physmem.perBankRdBursts::10 340 # Per bank write bursts +system.physmem.perBankRdBursts::8 436 # Per bank write bursts +system.physmem.perBankRdBursts::9 405 # Per bank write bursts +system.physmem.perBankRdBursts::10 339 # Per bank write bursts system.physmem.perBankRdBursts::11 306 # Per bank write bursts system.physmem.perBankRdBursts::12 414 # Per bank write bursts -system.physmem.perBankRdBursts::13 542 # Per bank write bursts -system.physmem.perBankRdBursts::14 453 # Per bank write bursts +system.physmem.perBankRdBursts::13 541 # Per bank write bursts +system.physmem.perBankRdBursts::14 454 # Per bank write bursts system.physmem.perBankRdBursts::15 379 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 77516291500 # Total gap between requests +system.physmem.totGap 77417410500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7447 # Read request sizes (log2) +system.physmem.readPktSize::6 7445 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4394 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2044 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 706 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4367 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2023 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 735 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 258 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -154,72 +154,60 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1164 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 404.618557 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.969320 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 801.678722 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 417 35.82% 35.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 184 15.81% 51.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 111 9.54% 61.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 97 8.33% 69.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 49 4.21% 73.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 38 3.26% 76.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 28 2.41% 79.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 28 2.41% 81.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 22 1.89% 83.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 22 1.89% 85.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 9 0.77% 86.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 13 1.12% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 15 1.29% 88.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 15 1.29% 90.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 6 0.52% 90.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 7 0.60% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 16 1.37% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 3 0.26% 92.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 5 0.43% 93.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 2 0.17% 93.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 3 0.26% 93.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 11 0.95% 94.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 4 0.34% 94.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 6 0.52% 95.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.26% 95.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 4 0.34% 96.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 3 0.26% 96.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 3 0.26% 96.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 3 0.26% 96.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 3 0.26% 97.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 2 0.17% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 5 0.43% 97.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.09% 97.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.09% 97.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 2 0.17% 98.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.09% 98.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.09% 98.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 1 0.09% 98.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 2 0.17% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 2 0.17% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.09% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 1 0.09% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 1 0.09% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.17% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 1 0.09% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.09% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 1 0.09% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 1 0.09% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.09% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.09% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 1 0.09% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.09% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 3 0.26% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1164 # Bytes accessed per row activation -system.physmem.totQLat 59914250 # Total ticks spent queuing -system.physmem.totMemAccLat 199861750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37235000 # Total ticks spent in databus transfers -system.physmem.totBankLat 102712500 # Total ticks spent accessing banks -system.physmem.avgQLat 8045.42 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13792.47 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 629 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 457.157393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 257.861215 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.549348 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 187 29.73% 29.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 122 19.40% 49.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53 8.43% 57.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 24 3.82% 61.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18 2.86% 64.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 15 2.38% 66.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7 1.11% 67.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 0.48% 68.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 200 31.80% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 629 # Bytes accessed per row activation +system.physmem.totQLat 62316500 # Total ticks spent queuing +system.physmem.totMemAccLat 205595250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37225000 # Total ticks spent in databus transfers +system.physmem.totBankLat 106053750 # Total ticks spent accessing banks +system.physmem.avgQLat 8370.25 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14244.96 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26837.89 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27615.21 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.15 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.15 # Average system read bandwidth in MiByte/s @@ -228,60 +216,60 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6283 # Number of row buffer hits during reads +system.physmem.readRowHits 6071 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.37 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.54 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 10409062.91 # Average gap between requests -system.physmem.pageHitRate 84.37 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.56 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 6148481 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4317 # Transaction distribution -system.membus.trans_dist::ReadResp 4317 # Transaction distribution -system.membus.trans_dist::ReadExReq 3130 # Transaction distribution -system.membus.trans_dist::ReadExResp 3130 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14894 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14894 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 476608 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 476608 # Total data (bytes) +system.physmem.avgGap 10398577.64 # Average gap between requests +system.physmem.pageHitRate 81.54 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.52 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 6154681 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4313 # Transaction distribution +system.membus.trans_dist::ReadResp 4313 # Transaction distribution +system.membus.trans_dist::ReadExReq 3132 # Transaction distribution +system.membus.trans_dist::ReadExResp 3132 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14890 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14890 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476480 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 476480 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 476480 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 9290500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9329500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 69562000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 69519750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 50307155 # Number of BP lookups -system.cpu.branchPred.condPredicted 29267262 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1212205 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26317352 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23268236 # Number of BTB hits +system.cpu.branchPred.lookups 50246060 # Number of BP lookups +system.cpu.branchPred.condPredicted 29233966 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1199560 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 25853120 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23225371 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.414047 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9019862 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1049 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.835853 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9012456 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1102 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 101828804 # DTB read hits -system.cpu.dtb.read_misses 77910 # DTB read misses -system.cpu.dtb.read_acv 48604 # DTB read access violations -system.cpu.dtb.read_accesses 101906714 # DTB read accesses -system.cpu.dtb.write_hits 78465960 # DTB write hits -system.cpu.dtb.write_misses 1494 # DTB write misses -system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 78467454 # DTB write accesses -system.cpu.dtb.data_hits 180294764 # DTB hits -system.cpu.dtb.data_misses 79404 # DTB misses -system.cpu.dtb.data_acv 48608 # DTB access violations -system.cpu.dtb.data_accesses 180374168 # DTB accesses -system.cpu.itb.fetch_hits 50297233 # ITB hits -system.cpu.itb.fetch_misses 369 # ITB misses +system.cpu.dtb.read_hits 101798719 # DTB read hits +system.cpu.dtb.read_misses 78049 # DTB read misses +system.cpu.dtb.read_acv 48607 # DTB read access violations +system.cpu.dtb.read_accesses 101876768 # DTB read accesses +system.cpu.dtb.write_hits 78433341 # DTB write hits +system.cpu.dtb.write_misses 1499 # DTB write misses +system.cpu.dtb.write_acv 2 # DTB write access violations +system.cpu.dtb.write_accesses 78434840 # DTB write accesses +system.cpu.dtb.data_hits 180232060 # DTB hits +system.cpu.dtb.data_misses 79548 # DTB misses +system.cpu.dtb.data_acv 48609 # DTB access violations +system.cpu.dtb.data_accesses 180311608 # DTB accesses +system.cpu.itb.fetch_hits 50221171 # ITB hits +system.cpu.itb.fetch_misses 373 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 50297602 # ITB accesses +system.cpu.itb.fetch_accesses 50221544 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -295,105 +283,105 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 155032764 # number of cpu cycles simulated +system.cpu.numCycles 154835002 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 51194259 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 449183474 # Number of instructions fetch has processed -system.cpu.fetch.Branches 50307155 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 32288098 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 78871433 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6172161 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19742008 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 181 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 10560 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 51111974 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 448661331 # Number of instructions fetch has processed +system.cpu.fetch.Branches 50246060 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 32237827 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 78769244 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6113875 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19767092 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 184 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 10735 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 50297233 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 412894 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 154739151 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.902843 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.324835 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 50221171 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 406319 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 154534598 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.903307 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.325117 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 75867718 49.03% 49.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4287409 2.77% 51.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6889018 4.45% 56.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5374428 3.47% 59.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11763624 7.60% 67.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 7816659 5.05% 72.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5616009 3.63% 76.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1833388 1.18% 77.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35290898 22.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 75765354 49.03% 49.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4278797 2.77% 51.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6878880 4.45% 56.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5365294 3.47% 59.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11742013 7.60% 67.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 7808130 5.05% 72.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5610858 3.63% 76.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1827134 1.18% 77.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35258138 22.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154739151 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.324494 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.897345 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 56553436 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 15088868 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74238964 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3941383 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4916500 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9487386 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4275 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 445247195 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12161 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4916500 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 59699528 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4890372 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 419538 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 75126102 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9687111 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 440708166 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 170 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 18989 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8005915 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 287519835 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 579387338 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 414037453 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 165349884 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 154534598 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.324514 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.897674 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 56469798 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 15107857 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74141890 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3943911 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4871142 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9469846 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4291 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 444777840 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12202 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4871142 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 59608441 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4896661 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 418311 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 75037002 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9703041 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 440308504 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 162 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 18256 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8013879 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 287257669 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 578877349 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 413693152 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 165184196 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27987506 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 36934 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 290 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 27862892 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104720393 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80633883 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8938676 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6410471 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 408405086 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 279 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 401961016 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 974295 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32695397 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15321612 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 64 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154739151 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.597668 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.996651 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 27725340 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 36879 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 302 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 27905569 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104673865 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80579462 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8919028 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6395315 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 408114726 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 290 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 401714158 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 971094 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32406044 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15222181 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 75 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154534598 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.599510 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.995704 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 28425455 18.37% 18.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 25900888 16.74% 35.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25580333 16.53% 51.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 24228882 15.66% 67.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21279905 13.75% 81.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15505585 10.02% 91.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8490760 5.49% 96.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3998033 2.58% 99.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1329310 0.86% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 28287072 18.30% 18.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 25862273 16.74% 35.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25616970 16.58% 51.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24199972 15.66% 67.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21258651 13.76% 81.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15520360 10.04% 91.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8472156 5.48% 96.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3988463 2.58% 99.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1328681 0.86% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154739151 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154534598 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 33873 0.29% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 33844 0.29% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 57850 0.49% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 5381 0.05% 0.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 5383 0.05% 0.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1948507 16.46% 17.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1748153 14.77% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 57389 0.49% 0.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 4757 0.04% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 5293 0.04% 0.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1937864 16.39% 17.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1755771 14.85% 32.09% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.09% # attempts to use FU when none available @@ -415,118 +403,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.09% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5077908 42.90% 74.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2960216 25.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5068587 42.87% 74.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2960872 25.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 155836212 38.77% 38.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126206 0.53% 39.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32826139 8.17% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7503461 1.87% 49.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2792900 0.69% 50.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16557877 4.12% 54.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1579224 0.39% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103415841 25.73% 80.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 79289575 19.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 155710180 38.76% 38.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126250 0.53% 39.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32800446 8.17% 47.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7495713 1.87% 49.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2793863 0.70% 50.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16555604 4.12% 54.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1576822 0.39% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103379318 25.73% 80.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 79242381 19.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 401961016 # Type of FU issued -system.cpu.iq.rate 2.592749 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11837271 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.029449 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 634505774 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 260497209 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 234812479 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 336966975 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 180652533 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 161419314 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 241576222 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 172188484 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 15052407 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 401714158 # Type of FU issued +system.cpu.iq.rate 2.594466 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11824377 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.029435 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 633974130 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 260128925 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 234699525 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 336784255 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 180440959 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 161353653 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 241409796 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172095158 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 15058802 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 9965906 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 111384 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 48996 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7113154 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 9919378 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 112340 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 48844 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7058733 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 260897 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3921 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 260875 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3830 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4916500 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2514816 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 370985 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 433209224 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 130318 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104720393 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80633883 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 279 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 90 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 76 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 48996 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 956631 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 408580 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1365211 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 398393230 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101955347 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3567786 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4871142 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2518143 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 371002 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 432897365 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 126094 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104673865 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80579462 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 290 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 87 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 80 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 48844 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 943634 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 406077 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1349711 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 398212292 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101925424 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3501866 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24803859 # number of nop insts executed -system.cpu.iew.exec_refs 180422830 # number of memory reference insts executed -system.cpu.iew.exec_branches 46575028 # Number of branches executed -system.cpu.iew.exec_stores 78467483 # Number of stores executed -system.cpu.iew.exec_rate 2.569736 # Inst execution rate -system.cpu.iew.wb_sent 396861814 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 396231793 # cumulative count of insts written-back -system.cpu.iew.wb_producers 193564452 # num instructions producing a value -system.cpu.iew.wb_consumers 271143010 # num instructions consuming a value +system.cpu.iew.exec_nop 24782349 # number of nop insts executed +system.cpu.iew.exec_refs 180360292 # number of memory reference insts executed +system.cpu.iew.exec_branches 46546611 # Number of branches executed +system.cpu.iew.exec_stores 78434868 # Number of stores executed +system.cpu.iew.exec_rate 2.571849 # Inst execution rate +system.cpu.iew.wb_sent 396683492 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 396053178 # cumulative count of insts written-back +system.cpu.iew.wb_producers 193508627 # num instructions producing a value +system.cpu.iew.wb_consumers 271030051 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.555794 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.713883 # average fanout of values written-back +system.cpu.iew.wb_rate 2.557905 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.713975 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 34575269 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 34263124 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1208013 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149822651 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.660910 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.995203 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1195351 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149663456 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.663740 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.995900 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 55444795 37.01% 37.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 22572345 15.07% 52.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13039783 8.70% 60.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11474023 7.66% 68.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8200661 5.47% 73.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5438800 3.63% 77.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5171862 3.45% 80.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3280269 2.19% 83.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 25200113 16.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 55327244 36.97% 36.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22535122 15.06% 52.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13022576 8.70% 60.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11475094 7.67% 68.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8197799 5.48% 73.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5452875 3.64% 77.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5172237 3.46% 80.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3274038 2.19% 83.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 25206471 16.84% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149822651 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 149663456 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -537,228 +525,228 @@ system.cpu.commit.branches 44587533 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 25200113 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 25206471 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 557859413 # The number of ROB reads -system.cpu.rob.rob_writes 871404727 # The number of ROB writes -system.cpu.timesIdled 3579 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 293613 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 557381715 # The number of ROB reads +system.cpu.rob.rob_writes 870735186 # The number of ROB writes +system.cpu.timesIdled 3600 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 300404 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated -system.cpu.cpi 0.412788 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.412788 # CPI: Total CPI of All Threads -system.cpu.ipc 2.422551 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.422551 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 398219851 # number of integer regfile reads -system.cpu.int_regfile_writes 170183531 # number of integer regfile writes -system.cpu.fp_regfile_reads 156589680 # number of floating regfile reads -system.cpu.fp_regfile_writes 104065109 # number of floating regfile writes +system.cpu.cpi 0.412261 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.412261 # CPI: Total CPI of All Threads +system.cpu.ipc 2.425645 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.425645 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 398046268 # number of integer regfile reads +system.cpu.int_regfile_writes 170097469 # number of integer regfile writes +system.cpu.fp_regfile_reads 156518592 # number of floating regfile reads +system.cpu.fp_regfile_writes 104028166 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 7356381 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 5061 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5061 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 659 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3190 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3190 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8138 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9023 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 17161 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 570240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 570240 # Total data (bytes) +system.cpu.toL2Bus.throughput 7364950 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 5055 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5055 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 661 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3193 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3193 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8124 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9033 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 17157 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 259968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 570176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 570176 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 5114000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 5115500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6775000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6740250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6675000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6663250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 2141 # number of replacements -system.cpu.icache.tags.tagsinuse 1831.580097 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 50291612 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4069 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12359.698206 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2135 # number of replacements +system.cpu.icache.tags.tagsinuse 1832.551439 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 50215552 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4062 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12362.272772 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1831.580097 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.894326 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.894326 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1928 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 336 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1334 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 100598535 # Number of tag accesses -system.cpu.icache.tags.data_accesses 100598535 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 50291612 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 50291612 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 50291612 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 50291612 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 50291612 # number of overall hits -system.cpu.icache.overall_hits::total 50291612 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5621 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5621 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5621 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5621 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5621 # number of overall misses -system.cpu.icache.overall_misses::total 5621 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 330634250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 330634250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 330634250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 330634250 # 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number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 332785750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 50221171 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 50221171 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 50221171 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 50221171 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 50221171 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 50221171 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000112 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000112 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000112 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000112 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 59225.084535 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 59225.084535 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 59225.084535 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 59225.084535 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 251 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 148.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 83.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4069 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4069 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249126500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 249126500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249126500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 249126500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249126500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 249126500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1557 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1557 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1557 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1557 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1557 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1557 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4062 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4062 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4062 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4062 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4062 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4062 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 250275250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 250275250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 250275250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 250275250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 250275250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 250275250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000081 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000081 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61225.485377 # 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Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86473896 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86473896 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73500850 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73500850 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 159974746 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 159974746 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 159974746 # number of overall hits +system.cpu.dcache.overall_hits::total 159974746 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1803 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1803 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19879 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19879 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21682 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21682 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21682 # number of overall misses +system.cpu.dcache.overall_misses::total 21682 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 116178750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 116178750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1100405079 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1100405079 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1216583829 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1216583829 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1216583829 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1216583829 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86475699 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86475699 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 160032782 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 160032782 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 160032782 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 160032782 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 159996428 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 159996428 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 159996428 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 159996428 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000270 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000270 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000135 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000135 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000135 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000135 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63957.586786 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63957.586786 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54710.187283 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54710.187283 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55473.643831 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55473.643831 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55473.643831 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55473.643831 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 40366 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.000136 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000136 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000136 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000136 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64436.356073 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64436.356073 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55355.152623 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55355.152623 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56110.314039 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56110.314039 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56110.314039 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56110.314039 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 40445 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 653 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 670 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 61.816233 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 60.365672 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 659 # number of writebacks -system.cpu.dcache.writebacks::total 659 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 794 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 794 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16657 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16657 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17451 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17451 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17451 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17451 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 992 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 992 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3190 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3190 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4182 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4182 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4182 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4182 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 68767000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 68767000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 229720000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 229720000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298487000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 298487000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298487000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 298487000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 661 # number of writebacks +system.cpu.dcache.writebacks::total 661 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 810 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 810 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16686 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16686 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17496 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17496 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17496 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17496 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 993 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 993 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3193 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3193 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4186 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4186 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4186 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4186 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 69211250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 69211250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 233753500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 233753500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 302964750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 302964750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 302964750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 302964750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -924,14 +912,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69321.572581 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69321.572581 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72012.539185 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72012.539185 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71374.222860 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71374.222860 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71374.222860 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71374.222860 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69699.144008 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69699.144008 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73208.111494 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73208.111494 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72375.716675 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72375.716675 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72375.716675 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72375.716675 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 634fe5f9a..648c5ea6f 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068504 # Number of seconds simulated -sim_ticks 68503867000 # Number of ticks simulated -final_tick 68503867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.068245 # Number of seconds simulated +sim_ticks 68245472000 # Number of ticks simulated +final_tick 68245472000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 147835 # Simulator instruction rate (inst/s) -host_op_rate 189000 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37091215 # Simulator tick rate (ticks/s) -host_mem_usage 278164 # Number of bytes of host memory used -host_seconds 1846.90 # Real time elapsed on the host +host_inst_rate 123424 # Simulator instruction rate (inst/s) +host_op_rate 157791 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 30849723 # Simulator tick rate (ticks/s) +host_mem_usage 321440 # Number of bytes of host memory used +host_seconds 2212.19 # Real time elapsed on the host sim_insts 273036725 # Number of instructions simulated sim_ops 349064449 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 193984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272256 # Number of bytes read from this memory -system.physmem.bytes_read::total 466240 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 193984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 193984 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3031 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4254 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7285 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2831723 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3974316 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6806039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2831723 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2831723 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2831723 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3974316 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6806039 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7286 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 193792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272576 # Number of bytes read from this memory +system.physmem.bytes_read::total 466368 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 193792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 193792 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3028 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4259 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7287 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2839632 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3994053 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6833684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2839632 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2839632 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2839632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3994053 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6833684 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7288 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7286 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7288 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 466304 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 466432 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 466304 # Total read bytes from the system interface side +system.physmem.bytesReadSys 466432 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 606 # Per bank write bursts -system.physmem.perBankRdBursts::1 800 # Per bank write bursts +system.physmem.perBankRdBursts::1 802 # Per bank write bursts system.physmem.perBankRdBursts::2 608 # Per bank write bursts system.physmem.perBankRdBursts::3 526 # Per bank write bursts -system.physmem.perBankRdBursts::4 443 # Per bank write bursts -system.physmem.perBankRdBursts::5 354 # Per bank write bursts -system.physmem.perBankRdBursts::6 164 # Per bank write bursts -system.physmem.perBankRdBursts::7 219 # Per bank write bursts -system.physmem.perBankRdBursts::8 207 # Per bank write bursts -system.physmem.perBankRdBursts::9 291 # Per bank write bursts -system.physmem.perBankRdBursts::10 322 # Per bank write bursts -system.physmem.perBankRdBursts::11 415 # Per bank write bursts -system.physmem.perBankRdBursts::12 529 # Per bank write bursts +system.physmem.perBankRdBursts::4 441 # Per bank write bursts +system.physmem.perBankRdBursts::5 356 # Per bank write bursts +system.physmem.perBankRdBursts::6 162 # Per bank write bursts +system.physmem.perBankRdBursts::7 220 # Per bank write bursts +system.physmem.perBankRdBursts::8 205 # Per bank write bursts +system.physmem.perBankRdBursts::9 290 # Per bank write bursts +system.physmem.perBankRdBursts::10 324 # Per bank write bursts +system.physmem.perBankRdBursts::11 417 # Per bank write bursts +system.physmem.perBankRdBursts::12 531 # Per bank write bursts system.physmem.perBankRdBursts::13 687 # Per bank write bursts system.physmem.perBankRdBursts::14 611 # Per bank write bursts -system.physmem.perBankRdBursts::15 504 # Per bank write bursts +system.physmem.perBankRdBursts::15 502 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 68503846500 # Total gap between requests +system.physmem.totGap 68245446000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7286 # Read request sizes (log2) +system.physmem.readPktSize::6 7288 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 567 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 176 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 66 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4342 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 590 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -154,124 +154,102 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1286 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 361.604977 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 163.647663 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 753.981601 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 537 41.76% 41.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 220 17.11% 58.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 131 10.19% 69.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 77 5.99% 75.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 39 3.03% 78.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 38 2.95% 81.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 26 2.02% 83.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 31 2.41% 85.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 17 1.32% 86.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 23 1.79% 88.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 6 0.47% 89.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 16 1.24% 90.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 3 0.23% 90.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 8 0.62% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 7 0.54% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 7 0.54% 92.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 5 0.39% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 8 0.62% 93.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 5 0.39% 93.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 6 0.47% 94.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 1 0.08% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 4 0.31% 94.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 4 0.31% 94.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 6 0.47% 95.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.23% 95.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 3 0.23% 95.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 3 0.23% 95.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 4 0.31% 96.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 2 0.16% 96.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 3 0.23% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 2 0.16% 96.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 4 0.31% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 2 0.16% 97.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.08% 97.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 2 0.16% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 1 0.08% 97.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 1 0.08% 97.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.08% 97.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.08% 97.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.08% 97.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 2 0.16% 98.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.08% 98.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 2 0.16% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 1 0.08% 98.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.08% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.08% 98.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.08% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 2 0.16% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.08% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 1 0.08% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.08% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 1 0.08% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 1 0.08% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 3 0.23% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 1 0.08% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.08% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 1 0.08% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 1 0.08% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 1 0.08% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 2 0.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1286 # Bytes accessed per row activation -system.physmem.totQLat 62980000 # Total ticks spent queuing -system.physmem.totMemAccLat 198080000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 36430000 # Total ticks spent in databus transfers -system.physmem.totBankLat 98670000 # Total ticks spent accessing banks -system.physmem.avgQLat 8643.97 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13542.41 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 580 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 479.779310 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 274.986956 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 421.744260 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 159 27.41% 27.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 117 20.17% 47.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 45 7.76% 55.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 23 3.97% 59.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 14 2.41% 61.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13 2.24% 63.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6 1.03% 65.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 0.34% 65.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 201 34.66% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 580 # Bytes accessed per row activation +system.physmem.totQLat 57907000 # Total ticks spent queuing +system.physmem.totMemAccLat 195684500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36440000 # Total ticks spent in databus transfers +system.physmem.totBankLat 101337500 # Total ticks spent accessing banks +system.physmem.avgQLat 7945.53 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13904.71 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27186.38 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26850.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.83 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.81 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.83 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6000 # Number of row buffer hits during reads +system.physmem.readRowHits 5839 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.35 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.12 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9402120.02 # Average gap between requests -system.physmem.pageHitRate 82.35 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.05 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 6806039 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4462 # Transaction distribution -system.membus.trans_dist::ReadResp 4461 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 2824 # Transaction distribution -system.membus.trans_dist::ReadExResp 2824 # Transaction distribution +system.physmem.avgGap 9364084.25 # Average gap between requests +system.physmem.pageHitRate 80.12 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.16 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 6833684 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4468 # Transaction distribution +system.membus.trans_dist::ReadResp 4467 # Transaction distribution +system.membus.trans_dist::ReadExReq 2820 # Transaction distribution +system.membus.trans_dist::ReadExResp 2820 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14575 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 14575 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466240 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 466240 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 466240 # Total data (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 466368 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 466368 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8931500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8915000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 67747998 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 67732500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 35407535 # Number of BP lookups -system.cpu.branchPred.condPredicted 21210003 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1658535 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19582924 # Number of BTB lookups -system.cpu.branchPred.BTBHits 16814113 # Number of BTB hits +system.cpu.branchPred.lookups 35342667 # Number of BP lookups +system.cpu.branchPred.condPredicted 21189046 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1621967 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18355176 # Number of BTB lookups +system.cpu.branchPred.BTBHits 16729462 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 85.861095 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6780652 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 8453 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 91.143021 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6774978 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 8404 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -357,100 +335,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 137007735 # number of cpu cycles simulated +system.cpu.numCycles 136490945 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 38995510 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 317974758 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35407535 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23594765 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70934448 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6878177 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 21511393 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 109 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1738 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 61 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37596145 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 512137 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 136651264 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.983546 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.454335 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 38825213 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 317051968 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35342667 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23504440 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70679896 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6716000 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 21545367 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 106 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1322 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 66 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 37451719 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 502899 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 136134435 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.985255 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.454681 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66349844 48.55% 48.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6791529 4.97% 53.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5702360 4.17% 57.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6103499 4.47% 62.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4918940 3.60% 65.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4085838 2.99% 68.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3180821 2.33% 71.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4138782 3.03% 74.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35379651 25.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66077496 48.54% 48.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6747770 4.96% 53.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5691244 4.18% 57.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6070617 4.46% 62.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4899295 3.60% 65.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4080163 3.00% 68.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3177720 2.33% 71.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4131471 3.03% 74.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35258659 25.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 136651264 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258435 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.320853 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45513422 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16662187 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 66798256 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2538078 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5139321 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7340905 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 69056 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401756741 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 208904 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5139321 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 51060721 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1905439 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 332675 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 63727748 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14485360 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 394162913 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 18 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1657895 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10187119 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 22377 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 432668253 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2737675688 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1575239963 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 200387111 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 136134435 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258938 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.322879 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45319095 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16701200 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 66547822 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2552537 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5013781 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7320658 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69067 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 400437341 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 211449 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5013781 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50843684 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1928767 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 335631 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 63516277 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14496295 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 392925979 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 32 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1658279 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10203172 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 22306 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 431444746 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2730832248 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1570013245 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 200164445 # Number of floating rename lookups system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 48102060 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11946 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11945 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 36528458 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 103595819 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 91394334 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4295156 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5297473 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 384542604 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22919 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 374214780 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1210476 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 34753044 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 100302329 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 799 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 136651264 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.738466 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.024544 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 46878553 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11940 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11939 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 36493417 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 103352368 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 91160183 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4261604 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5303451 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 383671023 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22900 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 373754233 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1199031 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 33881433 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 97712598 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 780 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 136134435 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.745479 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.022556 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 25105050 18.37% 18.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19938594 14.59% 32.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20566375 15.05% 48.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18171632 13.30% 61.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24028761 17.58% 78.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15737538 11.52% 90.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8814188 6.45% 96.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3372330 2.47% 99.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 916796 0.67% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24740289 18.17% 18.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19905513 14.62% 32.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20515084 15.07% 47.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18158642 13.34% 61.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 24030824 17.65% 78.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15691878 11.53% 90.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8802431 6.47% 96.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3372838 2.48% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 916936 0.67% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 136651264 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 136134435 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8713 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4693 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8938 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4692 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -469,127 +447,127 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 46317 0.26% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 46049 0.26% 0.34% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 3518 0.02% 0.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 440 0.00% 0.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 3482 0.02% 0.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 434 0.00% 0.36% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 186929 1.05% 1.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 4248 0.02% 1.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 241299 1.36% 2.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 186470 1.05% 1.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 3938 0.02% 1.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241178 1.36% 2.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9275439 52.33% 55.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7953254 44.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9277159 52.37% 55.16% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7942822 44.84% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 126461637 33.79% 33.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2175765 0.58% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 4 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6779975 1.81% 36.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8474577 2.26% 38.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3430301 0.92% 39.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1595259 0.43% 39.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20865413 5.58% 45.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7172902 1.92% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7130224 1.91% 49.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101650995 27.16% 76.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88302442 23.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 126226981 33.77% 33.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2175715 0.58% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 4 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6775957 1.81% 36.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8464752 2.26% 38.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3426733 0.92% 39.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1595441 0.43% 39.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20845390 5.58% 45.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7170609 1.92% 47.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7125607 1.91% 49.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101514689 27.16% 76.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88257068 23.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 374214780 # Type of FU issued -system.cpu.iq.rate 2.731341 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17724852 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047365 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654627146 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 288999508 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 250114053 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 249389006 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 130333197 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118063719 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 263337797 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 128601835 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11086522 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 373754233 # Type of FU issued +system.cpu.iq.rate 2.738308 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17715164 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047398 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 653197592 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 287339977 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 249810515 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249359504 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 130249499 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118015221 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 262881293 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128588104 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11104968 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 8947071 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 108758 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14277 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9018751 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8703620 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 109542 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14223 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8784600 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 174712 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1900 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 184473 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1790 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5139321 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 272764 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 35129 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 384567184 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 874047 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 103595819 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 91394334 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11885 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 347 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 280 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14277 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1299093 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 369514 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1668607 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 370257441 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100364532 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3957339 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 5013781 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 291002 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 36408 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 383695470 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 852736 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 103352368 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 91160183 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11866 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 327 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 282 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14223 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1256888 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 362770 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1619658 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 369836414 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100211998 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3917819 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1661 # number of nop insts executed -system.cpu.iew.exec_refs 187583075 # number of memory reference insts executed -system.cpu.iew.exec_branches 32009347 # Number of branches executed -system.cpu.iew.exec_stores 87218543 # Number of stores executed -system.cpu.iew.exec_rate 2.702456 # Inst execution rate -system.cpu.iew.wb_sent 368846220 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 368177772 # cumulative count of insts written-back -system.cpu.iew.wb_producers 183055174 # num instructions producing a value -system.cpu.iew.wb_consumers 363803620 # num instructions consuming a value +system.cpu.iew.exec_nop 1547 # number of nop insts executed +system.cpu.iew.exec_refs 187429987 # number of memory reference insts executed +system.cpu.iew.exec_branches 31988466 # Number of branches executed +system.cpu.iew.exec_stores 87217989 # Number of stores executed +system.cpu.iew.exec_rate 2.709604 # Inst execution rate +system.cpu.iew.wb_sent 368475660 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 367825736 # cumulative count of insts written-back +system.cpu.iew.wb_producers 182824140 # num instructions producing a value +system.cpu.iew.wb_consumers 363330392 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.687277 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.503170 # average fanout of values written-back +system.cpu.iew.wb_rate 2.694873 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.503190 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 35502239 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 34630475 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1589851 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 131511943 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.654246 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.658719 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1553283 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 131120654 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.662167 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.659302 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 34696225 26.38% 26.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 28452590 21.63% 48.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13345612 10.15% 58.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11442919 8.70% 66.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13780020 10.48% 77.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7417113 5.64% 82.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3869989 2.94% 85.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3892889 2.96% 88.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14614586 11.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34358811 26.20% 26.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 28410916 21.67% 47.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13299289 10.14% 58.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11469684 8.75% 66.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13783827 10.51% 77.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7406623 5.65% 82.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3875247 2.96% 85.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3903446 2.98% 88.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14612811 11.14% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 131511943 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 131120654 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037337 # Number of instructions committed system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -600,238 +578,230 @@ system.cpu.commit.branches 30563497 # Nu system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14614586 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14612811 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 501462134 # The number of ROB reads -system.cpu.rob.rob_writes 774278104 # The number of ROB writes -system.cpu.timesIdled 6640 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 356471 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 500200856 # The number of ROB reads +system.cpu.rob.rob_writes 772408679 # The number of ROB writes +system.cpu.timesIdled 6691 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 356510 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273036725 # Number of Instructions Simulated system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated -system.cpu.cpi 0.501792 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.501792 # CPI: Total CPI of All Threads -system.cpu.ipc 1.992856 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.992856 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1769894079 # number of integer regfile reads -system.cpu.int_regfile_writes 233026497 # number of integer regfile writes -system.cpu.fp_regfile_reads 188140638 # number of floating regfile reads -system.cpu.fp_regfile_writes 132514898 # number of floating regfile writes -system.cpu.misc_regfile_reads 1201076625 # number of misc regfile reads +system.cpu.cpi 0.499900 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.499900 # CPI: Total CPI of All Threads +system.cpu.ipc 2.000402 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.000402 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1768035388 # number of integer regfile reads +system.cpu.int_regfile_writes 232615737 # number of integer regfile writes +system.cpu.fp_regfile_reads 188041949 # number of floating regfile reads +system.cpu.fp_regfile_writes 132439422 # number of floating regfile writes +system.cpu.misc_regfile_reads 1200568638 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.toL2Bus.throughput 20069641 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 17607 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 17606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1035 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2841 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2841 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31671 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10259 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 41930 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1013312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 1374592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 1374592 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 11777500 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 20175639 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 17638 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 17637 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1039 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2838 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2838 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31713 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10277 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 41990 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1014784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 362112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 1376896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 1376896 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 11796500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24288488 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24305488 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7388212 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7381711 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 13947 # number of replacements -system.cpu.icache.tags.tagsinuse 1848.346697 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 37578823 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15836 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 2372.999684 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 13966 # number of replacements +system.cpu.icache.tags.tagsinuse 1849.581585 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 37434387 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15856 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2360.897263 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1848.346697 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.902513 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.902513 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1889 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1849.581585 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.903116 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.903116 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1890 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 205 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 206 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1530 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.922363 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 75208123 # Number of tag accesses -system.cpu.icache.tags.data_accesses 75208123 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 37578823 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37578823 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37578823 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37578823 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37578823 # number of overall hits -system.cpu.icache.overall_hits::total 37578823 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17320 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17320 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17320 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17320 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17320 # number of overall misses -system.cpu.icache.overall_misses::total 17320 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 450229234 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 450229234 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 450229234 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 450229234 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 450229234 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 450229234 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37596143 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37596143 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37596143 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37596143 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37596143 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37596143 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000461 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000461 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000461 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000461 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000461 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000461 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25994.759469 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25994.759469 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25994.759469 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25994.759469 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25994.759469 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25994.759469 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2351 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::4 1531 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.922852 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 74919290 # Number of tag accesses +system.cpu.icache.tags.data_accesses 74919290 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 37434387 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37434387 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37434387 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37434387 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37434387 # number of overall hits +system.cpu.icache.overall_hits::total 37434387 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17330 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17330 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17330 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17330 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17330 # number of overall misses +system.cpu.icache.overall_misses::total 17330 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 451723484 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 451723484 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 451723484 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 451723484 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 451723484 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 451723484 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37451717 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37451717 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37451717 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37451717 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37451717 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37451717 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000463 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000463 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000463 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000463 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000463 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000463 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26065.982920 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 26065.982920 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 26065.982920 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 26065.982920 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 26065.982920 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 26065.982920 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1035 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 25 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 94.040000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 39.807692 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1482 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1482 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1482 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1482 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1482 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1482 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15838 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15838 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15838 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -841,185 +811,177 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 39 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 40 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 39 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 51 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 40 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 52 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3032 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1430 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4462 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2824 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 2824 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3032 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 4254 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7286 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3032 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 4254 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7286 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 177153750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 90029000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 267182750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 164034250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 164034250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 177153750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 254063250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 431217000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 177153750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 254063250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 431217000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191487 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.808366 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253480 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994016 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994016 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191487 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922777 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.356388 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191487 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922777 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.356388 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58428.017810 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62957.342657 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59879.594352 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58085.782578 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58085.782578 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58428.017810 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59723.377997 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59184.326105 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58428.017810 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59723.377997 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59184.326105 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 39 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 51 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3029 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1439 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4468 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2820 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 2820 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3029 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4259 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7288 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3029 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 4259 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7288 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 176626500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 86490250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 263116750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 165285750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 165285750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176626500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 251776000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 428402500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176626500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 251776000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 428402500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191020 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.807973 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253317 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993658 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993658 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191020 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922061 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.355929 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191020 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922061 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.355929 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58311.819082 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60104.412787 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58889.156222 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58611.968085 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58611.968085 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58311.819082 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59116.224466 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58781.901756 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58311.819082 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59116.224466 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58781.901756 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1413 # number of replacements -system.cpu.dcache.tags.tagsinuse 3103.986618 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 170973728 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4610 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37087.576573 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1416 # number of replacements +system.cpu.dcache.tags.tagsinuse 3111.494128 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 170791722 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4619 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 36975.908638 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3103.986618 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.757809 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.757809 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3197 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 682 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2449 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.780518 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 342002086 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 342002086 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 88920204 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88920204 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82031597 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82031597 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11020 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11020 # number of LoadLockedReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 3111.494128 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.759642 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.759642 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3203 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 686 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2450 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.781982 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 341638239 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 341638239 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 88738255 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88738255 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82031563 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82031563 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11009 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11009 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 170951801 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 170951801 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 170951801 # number of overall hits -system.cpu.dcache.overall_hits::total 170951801 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3952 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3952 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 21068 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 21068 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 170769818 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 170769818 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 170769818 # number of overall hits +system.cpu.dcache.overall_hits::total 170769818 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3984 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3984 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 21102 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 21102 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25020 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25020 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25020 # number of overall misses -system.cpu.dcache.overall_misses::total 25020 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 237491705 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 237491705 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1258064893 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1258064893 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 25086 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25086 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25086 # number of overall misses +system.cpu.dcache.overall_misses::total 25086 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 232475203 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 232475203 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1255700879 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1255700879 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170250 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 170250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1495556598 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1495556598 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1495556598 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1495556598 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88924156 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88924156 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 1488176082 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1488176082 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1488176082 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1488176082 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88742239 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88742239 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11022 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11022 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11011 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11011 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 170976821 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 170976821 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 170976821 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 170976821 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000044 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 170794904 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 170794904 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 170794904 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 170794904 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000257 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000257 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000181 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000181 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000146 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000146 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000146 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000146 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60094.054909 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60094.054909 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59714.490839 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59714.490839 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000182 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000182 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58352.209588 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58352.209588 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59506.249597 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59506.249597 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59774.444365 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59774.444365 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59774.444365 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59774.444365 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 27944 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1224 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 406 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 68.827586 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 102 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59322.972255 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59322.972255 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59322.972255 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59322.972255 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 26768 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1267 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 424 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 63.132075 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 97.461538 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1035 # number of writebacks -system.cpu.dcache.writebacks::total 1035 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2181 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2181 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18227 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18227 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1039 # number of writebacks +system.cpu.dcache.writebacks::total 1039 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2202 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2202 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18265 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18265 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20408 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20408 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20408 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20408 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1771 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1771 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2841 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2841 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4612 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4612 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4612 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4612 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 115481540 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 115481540 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 201937248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 201937248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 317418788 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 317418788 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 317418788 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 317418788 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 20467 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20467 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20467 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20467 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1782 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1782 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2837 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2837 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4619 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4619 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4619 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4619 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 111706789 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 111706789 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 203137000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 203137000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 314843789 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 314843789 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 314843789 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 314843789 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -1028,14 +990,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65206.967815 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65206.967815 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71079.636748 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71079.636748 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68824.542064 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68824.542064 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68824.542064 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68824.542064 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62686.189113 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62686.189113 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71602.749383 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71602.749383 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68162.760121 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68162.760121 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68162.760121 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68162.760121 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |