diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:16 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:16 -0500 |
| commit | fce3433b2eb764d9519ffbc4c7e95049f3200ba3 (patch) | |
| tree | 26e90c5190c4751532683d1f4b5bf6094e6ba4b7 /tests/long/se/30.eon | |
| parent | c4898b15bcf5458e35f17cb0c3b4185cec0081aa (diff) | |
| download | gem5-fce3433b2eb764d9519ffbc4c7e95049f3200ba3.tar.xz | |
stats: Update stats for regressions using SimpleDDR3
This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.
Diffstat (limited to 'tests/long/se/30.eon')
| -rw-r--r-- | tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt | 528 | ||||
| -rw-r--r-- | tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt | 1132 | ||||
| -rw-r--r-- | tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt | 1124 |
3 files changed, 1392 insertions, 1392 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index 7980de17a..6c858f4a6 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.139847 # Number of seconds simulated -sim_ticks 139846906500 # Number of ticks simulated -final_tick 139846906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.139855 # Number of seconds simulated +sim_ticks 139855372500 # Number of ticks simulated +final_tick 139855372500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94955 # Simulator instruction rate (inst/s) -host_op_rate 94955 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33309069 # Simulator tick rate (ticks/s) -host_mem_usage 278532 # Number of bytes of host memory used -host_seconds 4198.46 # Real time elapsed on the host +host_inst_rate 164436 # Simulator instruction rate (inst/s) +host_op_rate 164436 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57685897 # Simulator tick rate (ticks/s) +host_mem_usage 230388 # Number of bytes of host memory used +host_seconds 2424.43 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 214976 # Nu system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1537224 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1816386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3353610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1537224 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1537224 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1537224 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1816386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3353610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1537131 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1816276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3353407 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1537131 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1537131 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1537131 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1816276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3353407 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7328 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 7328 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 468992 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 465 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 465 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 518 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 520 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 382 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 398 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 457 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 444 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 407 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 457 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 588 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 397 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 528 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 418 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 396 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 488 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 442 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 430 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 467 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 455 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 578 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 528 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 505 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 412 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 466 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 444 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 394 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 422 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 394 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 459 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 423 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 509 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 139846854500 # Total gap between requests +system.physmem.totGap 139855320500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,10 +98,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4654 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1888 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4560 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1887 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 585 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 230 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 65 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -164,56 +164,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 39390791 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 174626791 # Sum of mem lat for all requests -system.physmem.totBusLat 29312000 # Total cycles spent in databus access -system.physmem.totBankLat 105924000 # Total cycles spent in bank access -system.physmem.avgQLat 5375.38 # Average queueing delay per request -system.physmem.avgBankLat 14454.69 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23830.08 # Average memory access latency +system.physmem.totQLat 47661305 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 197340055 # Sum of mem lat for all requests +system.physmem.totBusLat 36640000 # Total cycles spent in databus access +system.physmem.totBankLat 113038750 # Total cycles spent in bank access +system.physmem.avgQLat 6504.00 # Average queueing delay per request +system.physmem.avgBankLat 15425.59 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 26929.59 # Average memory access latency system.physmem.avgRdBW 3.35 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 3.35 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6444 # Number of row buffer hits during reads +system.physmem.readRowHits 6132 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.94 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.68 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19083904.82 # Average gap between requests -system.cpu.branchPred.lookups 53489670 # Number of BP lookups -system.cpu.branchPred.condPredicted 30685393 # Number of conditional branches predicted +system.physmem.avgGap 19085060.11 # Average gap between requests +system.cpu.branchPred.lookups 53489671 # Number of BP lookups +system.cpu.branchPred.condPredicted 30685392 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 15149659 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 32882351 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15212538 # Number of BTB hits +system.cpu.branchPred.BTBLookups 32882352 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15212539 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 46.263535 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 46.263537 # BTB Hit Percentage system.cpu.branchPred.usedRAS 8007516 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 20 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 94754613 # DTB read hits +system.cpu.dtb.read_hits 94754610 # DTB read hits system.cpu.dtb.read_misses 21 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 94754634 # DTB read accesses -system.cpu.dtb.write_hits 73521103 # DTB write hits +system.cpu.dtb.read_accesses 94754631 # DTB read accesses +system.cpu.dtb.write_hits 73521101 # DTB write hits system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73521138 # DTB write accesses -system.cpu.dtb.data_hits 168275716 # DTB hits +system.cpu.dtb.write_accesses 73521136 # DTB write accesses +system.cpu.dtb.data_hits 168275711 # DTB hits system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168275772 # DTB accesses -system.cpu.itb.fetch_hits 48611354 # ITB hits +system.cpu.dtb.data_accesses 168275767 # DTB accesses +system.cpu.itb.fetch_hits 48611339 # ITB hits system.cpu.itb.fetch_misses 44520 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 48655874 # ITB accesses +system.cpu.itb.fetch_accesses 48655859 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -227,18 +227,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 279693814 # number of cpu cycles simulated +system.cpu.numCycles 279710746 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 29230505 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedTaken 29230506 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 24259165 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 280386588 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 280386586 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 439722447 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 119631948 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 439722445 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 119631954 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 219828429 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100484563 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.floatRegFileAccesses 219828435 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 100484559 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 168485322 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken). @@ -249,12 +249,12 @@ system.cpu.execution_unit.executions 205475782 # Nu system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 279400729 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 279400786 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7654 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13387179 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 266306635 # Number of cycles cpu stages are processed. -system.cpu.activity 95.213631 # Percentage of cycles cpu is active +system.cpu.timesIdled 7707 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13404116 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 266306630 # Number of cycles cpu stages are processed. +system.cpu.activity 95.207865 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -266,124 +266,124 @@ system.cpu.committedInsts 398664595 # Nu system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) -system.cpu.cpi 0.701577 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.701619 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.701577 # CPI: Total CPI of All Threads -system.cpu.ipc 1.425361 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.701619 # CPI: Total CPI of All Threads +system.cpu.ipc 1.425275 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.425361 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 77946120 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 201747694 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 72.131625 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 107042067 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 172651747 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.728840 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 102478598 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 177215216 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 63.360435 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 180949238 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 1.425275 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 77963056 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 201747690 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 72.127257 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 107059011 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 172651735 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 61.725099 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 102495582 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 177215164 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 63.356581 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 180966170 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 98744576 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 35.304526 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 90225845 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 189467969 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.741208 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 35.302389 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 90242832 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 189467914 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 67.737088 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1975 # number of replacements -system.cpu.icache.tagsinuse 1831.257835 # Cycle average of tags in use -system.cpu.icache.total_refs 48606847 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1831.214739 # Cycle average of tags in use +system.cpu.icache.total_refs 48606831 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 3903 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12453.714322 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 12453.710223 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1831.257835 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.894169 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.894169 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 48606847 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 48606847 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 48606847 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 48606847 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 48606847 # number of overall hits -system.cpu.icache.overall_hits::total 48606847 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4507 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4507 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4507 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4507 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4507 # number of overall misses -system.cpu.icache.overall_misses::total 4507 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 195448500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 195448500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 195448500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 195448500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 195448500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 195448500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 48611354 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 48611354 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 48611354 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 48611354 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 48611354 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 48611354 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1831.214739 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.894148 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.894148 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 48606831 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 48606831 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 48606831 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 48606831 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 48606831 # number of overall hits +system.cpu.icache.overall_hits::total 48606831 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4508 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4508 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4508 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4508 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4508 # number of overall misses +system.cpu.icache.overall_misses::total 4508 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 205410000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 205410000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 205410000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 205410000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 205410000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 205410000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 48611339 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 48611339 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 48611339 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 48611339 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 48611339 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 48611339 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43365.542489 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43365.542489 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43365.542489 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43365.542489 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43365.542489 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43365.542489 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 202 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45565.661047 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 45565.661047 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 45565.661047 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 45565.661047 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 45565.661047 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 45565.661047 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 206 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 67.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 68.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 604 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 604 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 604 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 604 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 604 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 604 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 605 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 605 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 605 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 605 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 605 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 605 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3903 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 3903 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 3903 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 3903 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3903 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3903 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170297500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 170297500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170297500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 170297500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170297500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 170297500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 179905000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 179905000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 179905000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 179905000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 179905000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 179905000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43632.462209 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43632.462209 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43632.462209 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 43632.462209 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43632.462209 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 43632.462209 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 46094.030233 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 46094.030233 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 46094.030233 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 46094.030233 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 46094.030233 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 46094.030233 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3907.773744 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3907.659379 # Cycle average of tags in use system.cpu.l2cache.total_refs 753 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 4717 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.159635 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 370.670185 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2909.388487 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 627.715072 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 370.655862 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2909.305713 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 627.697804 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.011312 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.088787 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.088785 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.019156 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.119256 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.119252 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 544 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 667 # number of ReadReq hits @@ -408,17 +408,17 @@ system.cpu.l2cache.demand_misses::total 7328 # nu system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7328 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 160908500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45014500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 205923000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 151967500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 151967500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 160908500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 196982000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 357890500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 160908500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 196982000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 357890500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 170516000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45771500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 216287500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 159323000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 159323000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 170516000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 205094500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 375610500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 170516000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 205094500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 375610500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3903 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4850 # number of ReadReq accesses(hits+misses) @@ -443,17 +443,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.909745 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.860620 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.909745 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47903.691575 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54629.247573 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49228.544107 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48320.349762 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48320.349762 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47903.691575 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 49630.133535 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 48838.769105 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47903.691575 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 49630.133535 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 48838.769105 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50763.917833 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55547.936893 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51706.311260 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50659.141494 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50659.141494 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50763.917833 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51674.099269 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51256.891376 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50763.917833 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51674.099269 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51256.891376 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -473,17 +473,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7328 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 118404553 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 34670717 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 153075270 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 112966799 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 112966799 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 118404553 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 147637516 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 266042069 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 118404553 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 147637516 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 266042069 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 128897344 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 35549956 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 164447300 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 120759327 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 120759327 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 128897344 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156309283 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 285206627 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 128897344 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156309283 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 285206627 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses @@ -495,51 +495,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35249.941352 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42076.112864 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36594.613913 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35919.490938 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35919.490938 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35249.941352 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37197.660872 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36304.867495 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35249.941352 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37197.660872 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36304.867495 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38373.725514 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43143.150485 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39313.244083 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38397.242289 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38397.242289 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38373.725514 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39382.535399 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38920.118313 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38373.725514 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39382.535399 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38920.118313 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3285.615449 # Cycle average of tags in use -system.cpu.dcache.total_refs 168254423 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3285.521075 # Cycle average of tags in use +system.cpu.dcache.total_refs 168254397 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 40523.704961 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 40523.698699 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3285.615449 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.802152 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.802152 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 94753185 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94753185 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501238 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501238 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168254423 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168254423 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168254423 # number of overall hits -system.cpu.dcache.overall_hits::total 168254423 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1304 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1304 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19491 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19491 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 20795 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20795 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 20795 # number of overall misses -system.cpu.dcache.overall_misses::total 20795 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 64310000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 64310000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 715525500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 715525500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 779835500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 779835500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 779835500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 779835500 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 3285.521075 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.802129 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.802129 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 94753186 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94753186 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501211 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501211 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168254397 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168254397 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168254397 # number of overall hits +system.cpu.dcache.overall_hits::total 168254397 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1303 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1303 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19518 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19518 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 20821 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20821 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 20821 # number of overall misses +system.cpu.dcache.overall_misses::total 20821 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 65740000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 65740000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 753340000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 753340000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 819080000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 819080000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 819080000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 819080000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -556,32 +556,32 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000124 system.cpu.dcache.demand_miss_rate::total 0.000124 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000124 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000124 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49317.484663 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49317.484663 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36710.558719 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36710.558719 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37501.106035 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37501.106035 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37501.106035 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37501.106035 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 16708 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50452.801228 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50452.801228 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38597.192335 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38597.192335 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39339.128764 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39339.128764 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39339.128764 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39339.128764 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 18390 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 535 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 537 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.229907 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.245810 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 649 # number of writebacks system.cpu.dcache.writebacks::total 649 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 354 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 354 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16289 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16289 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 16643 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 16643 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 16643 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 16643 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 353 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 353 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16316 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16316 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16669 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16669 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16669 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16669 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses @@ -590,14 +590,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47442500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 47442500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 155739500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 155739500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 203182000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 203182000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 203182000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 203182000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48200500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 48200500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 163094000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 163094000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211294500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 211294500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211294500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 211294500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -606,14 +606,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49939.473684 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49939.473684 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48638.194878 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48638.194878 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48935.934489 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 48935.934489 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48935.934489 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 48935.934489 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50737.368421 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50737.368421 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50935.040600 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50935.040600 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50889.812139 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50889.812139 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50889.812139 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50889.812139 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 078219244..f63466b63 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.077336 # Number of seconds simulated -sim_ticks 77336466500 # Number of ticks simulated -final_tick 77336466500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.077334 # Number of seconds simulated +sim_ticks 77333663500 # Number of ticks simulated +final_tick 77333663500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 141610 # Simulator instruction rate (inst/s) -host_op_rate 141610 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29159685 # Simulator tick rate (ticks/s) -host_mem_usage 279556 # Number of bytes of host memory used -host_seconds 2652.17 # Real time elapsed on the host +host_inst_rate 196388 # Simulator instruction rate (inst/s) +host_op_rate 196388 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40437661 # Simulator tick rate (ticks/s) +host_mem_usage 232448 # Number of bytes of host memory used +host_seconds 1912.42 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255488 # Number of bytes read from this memory -system.physmem.bytes_read::total 476288 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 220800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 220800 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3450 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3992 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7442 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2855057 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3303590 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6158647 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2855057 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2855057 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2855057 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3303590 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6158647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7442 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 221120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255552 # Number of bytes read from this memory +system.physmem.bytes_read::total 476672 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221120 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3455 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3993 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7448 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2859298 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3304538 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6163836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2859298 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2859298 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2859298 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3304538 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6163836 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7448 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7442 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 476288 # Total number of bytes read from memory +system.physmem.cpureqs 7448 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 476672 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 476288 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 476672 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 481 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 480 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 530 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 529 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 386 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 401 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 457 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 448 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 405 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 456 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 590 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 407 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 545 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 424 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 399 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 504 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 449 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 440 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 474 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 462 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 590 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 533 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 518 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 418 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 475 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 455 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 401 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 425 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 391 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 433 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 519 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 77336398000 # Total gap between requests +system.physmem.totGap 77333595000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7442 # Categorize read packet sizes +system.physmem.readPktSize::6 7448 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,13 +98,13 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2073 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 273 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2085 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 804 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 307 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -164,56 +164,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 40921923 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 178783923 # Sum of mem lat for all requests -system.physmem.totBusLat 29768000 # Total cycles spent in databus access -system.physmem.totBankLat 108094000 # Total cycles spent in bank access -system.physmem.avgQLat 5498.78 # Average queueing delay per request -system.physmem.avgBankLat 14524.86 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24023.64 # Average memory access latency +system.physmem.totQLat 53873160 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 207011910 # Sum of mem lat for all requests +system.physmem.totBusLat 37240000 # Total cycles spent in databus access +system.physmem.totBankLat 115898750 # Total cycles spent in bank access +system.physmem.avgQLat 7233.24 # Average queueing delay per request +system.physmem.avgBankLat 15561.06 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 27794.30 # Average memory access latency system.physmem.avgRdBW 6.16 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 6.16 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6502 # Number of row buffer hits during reads +system.physmem.readRowHits 6188 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.37 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.08 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 10391883.63 # Average gap between requests -system.cpu.branchPred.lookups 50254079 # Number of BP lookups -system.cpu.branchPred.condPredicted 29238788 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1202354 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26185724 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23237791 # Number of BTB hits +system.physmem.avgGap 10383135.74 # Average gap between requests +system.cpu.branchPred.lookups 50250166 # Number of BP lookups +system.cpu.branchPred.condPredicted 29237479 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1200857 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 25926395 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23227731 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.742213 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9009650 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1041 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.591056 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9011908 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1071 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 101791760 # DTB read hits -system.cpu.dtb.read_misses 77689 # DTB read misses -system.cpu.dtb.read_acv 48604 # DTB read access violations -system.cpu.dtb.read_accesses 101869449 # DTB read accesses -system.cpu.dtb.write_hits 78414713 # DTB write hits -system.cpu.dtb.write_misses 1485 # DTB write misses -system.cpu.dtb.write_acv 3 # DTB write access violations -system.cpu.dtb.write_accesses 78416198 # DTB write accesses -system.cpu.dtb.data_hits 180206473 # DTB hits -system.cpu.dtb.data_misses 79174 # DTB misses -system.cpu.dtb.data_acv 48607 # DTB access violations -system.cpu.dtb.data_accesses 180285647 # DTB accesses -system.cpu.itb.fetch_hits 50234226 # ITB hits -system.cpu.itb.fetch_misses 374 # ITB misses +system.cpu.dtb.read_hits 101791406 # DTB read hits +system.cpu.dtb.read_misses 78057 # DTB read misses +system.cpu.dtb.read_acv 48605 # DTB read access violations +system.cpu.dtb.read_accesses 101869463 # DTB read accesses +system.cpu.dtb.write_hits 78427886 # DTB write hits +system.cpu.dtb.write_misses 1487 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 78429373 # DTB write accesses +system.cpu.dtb.data_hits 180219292 # DTB hits +system.cpu.dtb.data_misses 79544 # DTB misses +system.cpu.dtb.data_acv 48609 # DTB access violations +system.cpu.dtb.data_accesses 180298836 # DTB accesses +system.cpu.itb.fetch_hits 50219857 # ITB hits +system.cpu.itb.fetch_misses 371 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 50234600 # ITB accesses +system.cpu.itb.fetch_accesses 50220228 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -227,238 +227,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 154672935 # number of cpu cycles simulated +system.cpu.numCycles 154667329 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 51121474 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 448760218 # Number of instructions fetch has processed -system.cpu.fetch.Branches 50254079 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 32247441 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 78789768 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6120508 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19691338 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 51106120 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 448669005 # Number of instructions fetch has processed +system.cpu.fetch.Branches 50250166 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 32239639 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 78764977 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6110488 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19721587 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9175 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 9420 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 50234226 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 409224 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 154491833 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.904750 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.325280 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 50219857 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 408750 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 154473509 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.904505 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.325354 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 75702065 49.00% 49.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4283300 2.77% 51.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6877325 4.45% 56.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5367764 3.47% 59.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11752749 7.61% 67.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 7805511 5.05% 72.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5606089 3.63% 75.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1832349 1.19% 77.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35264681 22.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 75708532 49.01% 49.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4277779 2.77% 51.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6877340 4.45% 56.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5358744 3.47% 59.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11737510 7.60% 67.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 7816086 5.06% 72.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5610591 3.63% 75.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1829118 1.18% 77.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35257809 22.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154491833 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.324905 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.901349 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 56470400 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 15041439 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74166392 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3937938 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4875664 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9475904 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4278 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 444843868 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12237 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4875664 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 59604786 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4871643 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 401502 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 75064420 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9673818 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 440376827 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 86 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 19255 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 7994088 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 287328410 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 578957076 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 306311574 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 272645502 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 154473509 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.324892 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.900865 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 56459553 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 15066363 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74129391 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3951215 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4866987 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9471001 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4302 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 444763327 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12199 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4866987 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 59590768 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4877628 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 403370 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 75043534 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9691222 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 440325296 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 81 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 19775 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8008636 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 287258509 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 578891151 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 306269628 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 272621523 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27796081 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 36810 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 298 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 27798585 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104665260 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80564409 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8907082 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6393839 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 408148309 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 288 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 401749536 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 973581 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32442077 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15221672 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 73 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154491833 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.600458 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.995634 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 27726180 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 36829 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 293 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 27858963 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104659356 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80576509 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8905764 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6378561 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 408090088 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 285 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 401700569 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 966818 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32383170 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15203599 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 70 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154473509 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.600450 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.995226 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 28272588 18.30% 18.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 25828142 16.72% 35.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25544882 16.53% 51.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 24283906 15.72% 67.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21283015 13.78% 81.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15483551 10.02% 91.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8467826 5.48% 96.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4000243 2.59% 99.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1327680 0.86% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 28241568 18.28% 18.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 25850506 16.73% 35.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25557985 16.55% 51.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24263587 15.71% 67.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21289313 13.78% 81.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15479662 10.02% 91.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8473783 5.49% 96.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3991768 2.58% 99.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1325337 0.86% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154491833 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154473509 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 34079 0.29% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 34109 0.29% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 57868 0.49% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 5831 0.05% 0.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 5354 0.05% 0.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1930027 16.34% 17.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1748928 14.81% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5061323 42.85% 74.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2967669 25.13% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 56920 0.48% 0.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 5994 0.05% 0.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 5359 0.05% 0.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1948290 16.45% 17.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1748478 14.77% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5072339 42.83% 74.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2970257 25.08% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 155748072 38.77% 38.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126114 0.53% 39.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32812204 8.17% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7499410 1.87% 49.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2793875 0.70% 50.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16556840 4.12% 54.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1578743 0.39% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103369723 25.73% 80.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 79230974 19.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 155713729 38.76% 38.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126194 0.53% 39.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32798014 8.16% 47.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7493329 1.87% 49.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2792591 0.70% 50.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16555292 4.12% 54.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1575667 0.39% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103367731 25.73% 80.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 79244441 19.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 401749536 # Type of FU issued -system.cpu.iq.rate 2.597413 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11811079 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.029399 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 634008068 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 260192564 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 234721556 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 336767497 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 180447135 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 161345688 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 241449037 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 172077997 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 15060402 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 401700569 # Type of FU issued +system.cpu.iq.rate 2.597191 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11841746 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.029479 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 633918884 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 260111127 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 234694704 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 336764327 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 180411325 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 161341889 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 241419354 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172089380 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 15066516 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 9910773 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 111367 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 49045 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7043680 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 9904869 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 112431 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 48930 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7055780 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 260907 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2589 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 260879 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2892 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4875664 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2512017 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 367237 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 432932337 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 125430 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104665260 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80564409 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 288 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 91 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 94 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 49045 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 948042 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 404840 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1352882 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 398223090 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101918095 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3526446 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4866987 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2513908 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 367539 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 432875837 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 130046 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104659356 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80576509 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 285 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 90 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 95 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 48930 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 945508 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 405299 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1350807 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 398189954 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101918110 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3510615 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24783740 # number of nop insts executed -system.cpu.iew.exec_refs 180334326 # number of memory reference insts executed -system.cpu.iew.exec_branches 46552042 # Number of branches executed -system.cpu.iew.exec_stores 78416231 # Number of stores executed -system.cpu.iew.exec_rate 2.574614 # Inst execution rate -system.cpu.iew.wb_sent 396695169 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 396067244 # cumulative count of insts written-back -system.cpu.iew.wb_producers 193570018 # num instructions producing a value -system.cpu.iew.wb_consumers 271138332 # num instructions consuming a value +system.cpu.iew.exec_nop 24785464 # number of nop insts executed +system.cpu.iew.exec_refs 180347520 # number of memory reference insts executed +system.cpu.iew.exec_branches 46544583 # Number of branches executed +system.cpu.iew.exec_stores 78429410 # Number of stores executed +system.cpu.iew.exec_rate 2.574493 # Inst execution rate +system.cpu.iew.wb_sent 396666494 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 396036593 # cumulative count of insts written-back +system.cpu.iew.wb_producers 193534236 # num instructions producing a value +system.cpu.iew.wb_consumers 271064264 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.560676 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.713916 # average fanout of values written-back +system.cpu.iew.wb_rate 2.560570 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.713979 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 34296903 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 34241397 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1198153 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149616169 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.664582 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.996061 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1196652 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149606522 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.664754 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.996488 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 55282421 36.95% 36.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 22517619 15.05% 52.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13057157 8.73% 60.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11465050 7.66% 68.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8178831 5.47% 73.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5460295 3.65% 77.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5171821 3.46% 80.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3274025 2.19% 83.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 25208950 16.85% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 55299818 36.96% 36.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22506360 15.04% 52.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13038976 8.72% 60.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11456394 7.66% 68.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8182427 5.47% 73.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5460458 3.65% 77.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5170598 3.46% 80.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3276425 2.19% 83.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 25215066 16.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149616169 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 149606522 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -469,192 +469,192 @@ system.cpu.commit.branches 44587533 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 25208950 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 25215066 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 557365728 # The number of ROB reads -system.cpu.rob.rob_writes 870806965 # The number of ROB writes -system.cpu.timesIdled 3403 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 181102 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 557294459 # The number of ROB reads +system.cpu.rob.rob_writes 870687579 # The number of ROB writes +system.cpu.timesIdled 3435 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 193820 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated -system.cpu.cpi 0.411830 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.411830 # CPI: Total CPI of All Threads -system.cpu.ipc 2.428187 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.428187 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 398054965 # number of integer regfile reads -system.cpu.int_regfile_writes 170113807 # number of integer regfile writes -system.cpu.fp_regfile_reads 156515246 # number of floating regfile reads -system.cpu.fp_regfile_writes 104037972 # number of floating regfile writes +system.cpu.cpi 0.411815 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.411815 # CPI: Total CPI of All Threads +system.cpu.ipc 2.428275 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.428275 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 398027050 # number of integer regfile reads +system.cpu.int_regfile_writes 170092718 # number of integer regfile writes +system.cpu.fp_regfile_reads 156507210 # number of floating regfile reads +system.cpu.fp_regfile_writes 104024348 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 2129 # number of replacements -system.cpu.icache.tagsinuse 1832.082194 # Cycle average of tags in use -system.cpu.icache.total_refs 50228789 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4056 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12383.823718 # Average number of references to valid blocks. +system.cpu.icache.replacements 2144 # number of replacements +system.cpu.icache.tagsinuse 1832.992748 # Cycle average of tags in use +system.cpu.icache.total_refs 50214380 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4071 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12334.654876 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1832.082194 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.894571 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.894571 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 50228789 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 50228789 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 50228789 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 50228789 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 50228789 # number of overall hits -system.cpu.icache.overall_hits::total 50228789 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5437 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5437 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5437 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5437 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5437 # number of overall misses -system.cpu.icache.overall_misses::total 5437 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 226400000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 226400000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 226400000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 226400000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 226400000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 226400000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 50234226 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 50234226 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 50234226 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 50234226 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 50234226 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 50234226 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000108 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000108 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000108 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000108 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000108 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000108 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41640.610631 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41640.610631 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41640.610631 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41640.610631 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41640.610631 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41640.610631 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 238 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1832.992748 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.895016 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.895016 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 50214380 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 50214380 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 50214380 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 50214380 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 50214380 # number of overall hits +system.cpu.icache.overall_hits::total 50214380 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5477 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5477 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5477 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5477 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5477 # number of overall misses +system.cpu.icache.overall_misses::total 5477 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 242175000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 242175000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 242175000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 242175000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 242175000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 242175000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 50219857 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 50219857 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 50219857 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 50219857 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 50219857 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 50219857 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000109 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000109 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000109 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000109 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000109 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000109 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44216.724484 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 44216.724484 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 44216.724484 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 44216.724484 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 44216.724484 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 44216.724484 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 692 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 59.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 138.400000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1381 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1381 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1381 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1381 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1381 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1381 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4056 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4056 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4056 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4056 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4056 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4056 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175832000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 175832000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175832000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 175832000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175832000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 175832000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1406 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1406 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1406 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1406 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1406 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1406 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4071 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4071 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4071 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4071 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4071 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4071 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 185126500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 185126500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 185126500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 185126500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 185126500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 185126500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000081 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000081 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43351.084813 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43351.084813 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43351.084813 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 43351.084813 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43351.084813 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 43351.084813 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45474.453451 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45474.453451 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45474.453451 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 45474.453451 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45474.453451 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 45474.453451 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 4007.668584 # Cycle average of tags in use -system.cpu.l2cache.total_refs 823 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4847 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.169796 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 4012.712180 # Cycle average of tags in use +system.cpu.l2cache.total_refs 831 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 4852 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.171270 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 372.532696 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2973.483231 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 661.652657 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 372.528713 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2978.555345 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 661.628123 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.011369 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.090744 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.020192 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.122304 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 606 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 130 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 736 # number of ReadReq hits +system.cpu.l2cache.occ_percent::cpu.inst 0.090898 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.020191 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.122458 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 616 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 129 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 745 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 657 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 657 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 606 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 190 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 796 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 606 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 190 # number of overall hits -system.cpu.l2cache.overall_hits::total 796 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3450 # number of ReadReq misses +system.cpu.l2cache.demand_hits::cpu.inst 616 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 189 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 805 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 616 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 189 # number of overall hits +system.cpu.l2cache.overall_hits::total 805 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3455 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 861 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4311 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 3131 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 3131 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3450 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3992 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7442 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3450 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3992 # number of overall misses -system.cpu.l2cache.overall_misses::total 7442 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 165703500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 49209000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 214912500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 151131500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 151131500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 165703500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 200340500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 366044000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 165703500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 200340500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 366044000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 4056 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 991 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5047 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_misses::total 4316 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 3132 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 3132 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3455 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3993 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7448 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3455 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3993 # number of overall misses +system.cpu.l2cache.overall_misses::total 7448 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 174877500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51530000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 226407500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163360500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 163360500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 174877500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 214890500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 389768000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 174877500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 214890500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 389768000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4071 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 990 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5061 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 657 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 657 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 3191 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 3191 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4056 # number of demand (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 3192 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 3192 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4071 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4182 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 8238 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4056 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8253 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4071 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4182 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 8238 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.850592 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.868819 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.854171 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981197 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.981197 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.850592 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.954567 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.903375 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.850592 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.954567 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.903375 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48030 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57153.310105 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49852.122477 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48269.402747 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48269.402747 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48030 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50185.495992 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 49186.240258 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48030 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50185.495992 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 49186.240258 # average overall miss latency +system.cpu.l2cache.overall_accesses::total 8253 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.848686 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.869697 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.852796 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981203 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.981203 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.848686 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.954806 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.902460 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.848686 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.954806 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.902460 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50615.774240 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59849.012776 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52457.715477 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52158.524904 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52158.524904 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50615.774240 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53816.804408 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52331.901182 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50615.774240 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53816.804408 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52331.901182 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -663,146 +663,146 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3450 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3455 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 861 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4311 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3131 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3131 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3450 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3992 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7442 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3450 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3992 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7442 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 122247748 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 38514499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 160762247 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 112485998 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 112485998 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 122247748 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151000497 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 273248245 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 122247748 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151000497 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 273248245 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.850592 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.868819 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.854171 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981197 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981197 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.850592 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.954567 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.903375 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.850592 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.954567 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.903375 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35434.129855 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44732.286876 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37291.173046 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35926.540402 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35926.540402 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35434.129855 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37825.775802 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36717.044477 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35434.129855 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37825.775802 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36717.044477 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::total 4316 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3132 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3132 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3455 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3993 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7448 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3455 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3993 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7448 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 131818904 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40942458 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 172761362 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 125001233 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 125001233 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 131818904 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 165943691 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 297762595 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 131818904 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 165943691 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 297762595 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.848686 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869697 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.852796 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981203 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981203 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.848686 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.954806 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.902460 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.848686 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.954806 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.902460 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38153.083647 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47552.216028 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40028.119092 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39910.993934 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39910.993934 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38153.083647 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41558.650388 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39978.866139 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38153.083647 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41558.650388 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39978.866139 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 780 # number of replacements -system.cpu.dcache.tagsinuse 3297.205890 # Cycle average of tags in use -system.cpu.dcache.total_refs 159967351 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3297.047040 # Cycle average of tags in use +system.cpu.dcache.total_refs 159960718 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4182 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 38251.399091 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 38249.813008 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3297.205890 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.804982 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.804982 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 86466482 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86466482 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73500862 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73500862 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 7 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 7 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 159967344 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 159967344 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 159967344 # number of overall hits -system.cpu.dcache.overall_hits::total 159967344 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1810 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1810 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19867 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19867 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21677 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21677 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21677 # number of overall misses -system.cpu.dcache.overall_misses::total 21677 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 83400000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 83400000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 721598130 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 721598130 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 804998130 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 804998130 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 804998130 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 804998130 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86468292 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86468292 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 3297.047040 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.804943 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.804943 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 86459752 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86459752 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73500960 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73500960 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 159960712 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 159960712 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 159960712 # number of overall hits +system.cpu.dcache.overall_hits::total 159960712 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1811 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1811 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19769 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19769 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21580 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21580 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21580 # number of overall misses +system.cpu.dcache.overall_misses::total 21580 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 89987500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 89987500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 779488110 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 779488110 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 869475610 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 869475610 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 869475610 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 869475610 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86461563 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86461563 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 159989021 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 159989021 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 159989021 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 159989021 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 159982292 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 159982292 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 159982292 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 159982292 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000270 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000270 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000135 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000135 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000135 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000135 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46077.348066 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 46077.348066 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36321.444103 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36321.444103 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37136.048807 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37136.048807 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37136.048807 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37136.048807 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23923 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49689.398123 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49689.398123 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39429.819920 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39429.819920 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40290.806766 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40290.806766 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40290.806766 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40290.806766 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 28165 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 631 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.912837 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.635499 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 657 # number of writebacks system.cpu.dcache.writebacks::total 657 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 819 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 819 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16676 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16676 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17495 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17495 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17495 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17495 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 991 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 991 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3191 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3191 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 821 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 821 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16577 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16577 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17398 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17398 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17398 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17398 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 990 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 990 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3192 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3192 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 4182 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 4182 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4182 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4182 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51550500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 51550500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 155023000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 155023000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 206573500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 206573500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 206573500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 206573500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53863000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 53863000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167256500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 167256500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 221119500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 221119500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 221119500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 221119500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -811,14 +811,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52018.668012 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52018.668012 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48581.322469 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48581.322469 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49395.863223 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 49395.863223 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49395.863223 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 49395.863223 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54407.070707 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54407.070707 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52398.652882 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52398.652882 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52874.103300 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52874.103300 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52874.103300 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52874.103300 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index cecd350a2..c2e0aed87 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068072 # Number of seconds simulated -sim_ticks 68071881000 # Number of ticks simulated -final_tick 68071881000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.068358 # Number of seconds simulated +sim_ticks 68358106500 # Number of ticks simulated +final_tick 68358106500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102151 # Simulator instruction rate (inst/s) -host_op_rate 130595 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25467625 # Simulator tick rate (ticks/s) -host_mem_usage 296712 # Number of bytes of host memory used -host_seconds 2672.88 # Real time elapsed on the host +host_inst_rate 148173 # Simulator instruction rate (inst/s) +host_op_rate 189432 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37097000 # Simulator tick rate (ticks/s) +host_mem_usage 250340 # Number of bytes of host memory used +host_seconds 1842.69 # Real time elapsed on the host sim_insts 273036725 # Number of instructions simulated sim_ops 349064449 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 193792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272448 # Number of bytes read from this memory -system.physmem.bytes_read::total 466240 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 193792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 193792 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3028 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4257 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7285 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2846873 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4002357 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6849230 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2846873 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2846873 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2846873 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4002357 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6849230 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7286 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 193152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272576 # Number of bytes read from this memory +system.physmem.bytes_read::total 465728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 193152 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 193152 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3018 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4259 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7277 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2825590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3987471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6813062 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2825590 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2825590 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2825590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3987471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6813062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7278 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7288 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 466240 # Total number of bytes read from memory +system.physmem.cpureqs 7280 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 465728 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 466240 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 465728 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 344 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 467 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 513 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 577 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 474 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 456 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 437 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 504 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 481 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 494 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 481 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 557 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 360 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 416 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 365 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 360 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 414 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 413 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 482 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 478 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 504 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 488 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 546 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 585 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 400 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 430 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 455 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 415 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 381 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 421 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 451 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 415 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 68071860500 # Total gap between requests +system.physmem.totGap 68358086000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7286 # Categorize read packet sizes +system.physmem.readPktSize::6 7278 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 2 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 572 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 184 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2167 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,36 +164,36 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 38841760 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 170087760 # Sum of mem lat for all requests -system.physmem.totBusLat 29144000 # Total cycles spent in databus access -system.physmem.totBankLat 102102000 # Total cycles spent in bank access -system.physmem.avgQLat 5331.01 # Average queueing delay per request -system.physmem.avgBankLat 14013.45 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23344.46 # Average memory access latency -system.physmem.avgRdBW 6.85 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 46727256 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 192182256 # Sum of mem lat for all requests +system.physmem.totBusLat 36390000 # Total cycles spent in databus access +system.physmem.totBankLat 109065000 # Total cycles spent in bank access +system.physmem.avgQLat 6420.34 # Average queueing delay per request +system.physmem.avgBankLat 14985.57 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 26405.92 # Average memory access latency +system.physmem.avgRdBW 6.81 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 6.85 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 6.81 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6372 # Number of row buffer hits during reads +system.physmem.readRowHits 6070 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.46 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.40 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9342830.15 # Average gap between requests -system.cpu.branchPred.lookups 41692065 # Number of BP lookups -system.cpu.branchPred.condPredicted 21046025 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1612310 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25558633 # Number of BTB lookups -system.cpu.branchPred.BTBHits 16675018 # Number of BTB hits +system.physmem.avgGap 9392427.32 # Average gap between requests +system.cpu.branchPred.lookups 41732744 # Number of BP lookups +system.cpu.branchPred.condPredicted 21038238 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1652729 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 26040996 # Number of BTB lookups +system.cpu.branchPred.BTBHits 16764116 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 65.242214 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6736046 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 7190 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 64.375863 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6744035 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 7274 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -237,100 +237,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 136143763 # number of cpu cycles simulated +system.cpu.numCycles 136716214 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 38720751 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 316654874 # Number of instructions fetch has processed -system.cpu.fetch.Branches 41692065 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23411064 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70618145 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6665842 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 21550456 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1364 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 38933938 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 317883912 # Number of instructions fetch has processed +system.cpu.fetch.Branches 41732744 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23508151 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70884226 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6817030 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 21520624 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1371 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37376595 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 521732 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 135933121 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.990728 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.456678 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 37551869 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 523991 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 136493185 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.988959 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.456313 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 65940392 48.51% 48.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6730475 4.95% 53.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5637804 4.15% 57.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5998950 4.41% 62.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4879102 3.59% 65.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4141679 3.05% 68.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3188425 2.35% 71.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4149669 3.05% 74.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35266625 25.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66238954 48.53% 48.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6780831 4.97% 53.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5636861 4.13% 57.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6036296 4.42% 62.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4884969 3.58% 65.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4157247 3.05% 68.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3216539 2.36% 71.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4148137 3.04% 74.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35393351 25.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 135933121 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.306236 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.325886 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45271721 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16691056 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 66469199 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2527476 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4973669 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7265289 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 69057 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 400237870 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 218381 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4973669 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50782794 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1926905 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 308736 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 63418534 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14522483 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 392567341 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 52 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1667501 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10227766 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1022 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 431145358 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2325492453 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1253893551 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1071598902 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 136493185 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.305251 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.325137 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45460656 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16697353 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 66694244 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2556726 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5084206 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7272433 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69135 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401643990 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 218444 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5084206 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50968262 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1914523 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 308341 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 63676495 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14541358 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 393775984 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 63 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1667283 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10312278 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1126 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 432122953 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2331950900 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1259654779 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1072296121 # Number of floating rename lookups system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 46579165 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11899 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11898 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 36419091 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 103284417 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 91190896 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4278404 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5313371 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 383399978 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22859 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 373603209 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1225399 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 33612220 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 83720105 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 739 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 135933121 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.748434 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.022451 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 47556760 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11781 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11780 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 36361756 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 103536184 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 91503384 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4302647 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5369286 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 384225176 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22747 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 374106691 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1237893 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 34434852 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 85933398 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 627 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 136493185 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.740845 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.023746 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24617806 18.11% 18.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19905628 14.64% 32.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20463769 15.05% 47.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18134866 13.34% 61.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 23975475 17.64% 78.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15748338 11.59% 90.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8799560 6.47% 96.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3376937 2.48% 99.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 910742 0.67% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24947846 18.28% 18.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19979954 14.64% 32.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20599928 15.09% 48.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18110176 13.27% 61.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 23967090 17.56% 78.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15779150 11.56% 90.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8840932 6.48% 96.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3358221 2.46% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 909888 0.67% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 135933121 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 136493185 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9041 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4688 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8903 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4693 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -349,127 +349,127 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 46127 0.26% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 46069 0.26% 0.34% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7573 0.04% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 401 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 189986 1.07% 1.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 6027 0.03% 1.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 241589 1.36% 2.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9303270 52.42% 55.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7940124 44.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7541 0.04% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 384 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 189821 1.07% 1.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 6023 0.03% 1.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241770 1.36% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9327128 52.38% 55.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7975640 44.79% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 126062452 33.74% 33.74% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2174186 0.58% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6778330 1.81% 36.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 126244558 33.75% 33.75% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2174203 0.58% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6782034 1.81% 36.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8468082 2.27% 38.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3426363 0.92% 39.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1600385 0.43% 39.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20905129 5.60% 45.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7170133 1.92% 47.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7133112 1.91% 49.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175289 0.05% 49.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101416985 27.15% 76.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88292763 23.63% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8468832 2.26% 38.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3426641 0.92% 39.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1600511 0.43% 39.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20905751 5.59% 45.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7170121 1.92% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7133236 1.91% 49.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101536664 27.14% 76.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88488853 23.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 373603209 # Type of FU issued -system.cpu.iq.rate 2.744182 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17748829 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047507 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 652552700 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 286781782 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 249670215 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 249561067 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 130267469 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118091463 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 262665125 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 128686913 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11143467 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 374106691 # Type of FU issued +system.cpu.iq.rate 2.736374 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17807974 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047601 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654078451 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 288293032 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 250000264 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249673983 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 130403978 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118157993 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 263169120 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128745545 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11104268 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 8635669 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 113833 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14304 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8815313 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8887436 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 113793 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14364 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9127801 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 179767 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1150 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 171663 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1472 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4973669 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 290169 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 43007 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 383424336 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 947805 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 103284417 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 91190896 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11825 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 324 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 376 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14304 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1257323 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 355165 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1612488 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 369752091 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100205261 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3851118 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 5084206 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 279212 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 42812 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 384249465 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 945099 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 103536184 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 91503384 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11713 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 308 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 361 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14364 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1301821 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 354554 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1656375 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 370204175 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100335709 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3902516 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1499 # number of nop insts executed -system.cpu.iew.exec_refs 187415465 # number of memory reference insts executed -system.cpu.iew.exec_branches 38269539 # Number of branches executed -system.cpu.iew.exec_stores 87210204 # Number of stores executed -system.cpu.iew.exec_rate 2.715894 # Inst execution rate -system.cpu.iew.wb_sent 368418252 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 367761678 # cumulative count of insts written-back -system.cpu.iew.wb_producers 182872307 # num instructions producing a value -system.cpu.iew.wb_consumers 363527613 # num instructions consuming a value +system.cpu.iew.exec_nop 1542 # number of nop insts executed +system.cpu.iew.exec_refs 187704225 # number of memory reference insts executed +system.cpu.iew.exec_branches 38278467 # Number of branches executed +system.cpu.iew.exec_stores 87368516 # Number of stores executed +system.cpu.iew.exec_rate 2.707829 # Inst execution rate +system.cpu.iew.wb_sent 368827623 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 368158257 # cumulative count of insts written-back +system.cpu.iew.wb_producers 183056844 # num instructions producing a value +system.cpu.iew.wb_consumers 364050324 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.701275 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.503049 # average fanout of values written-back +system.cpu.iew.wb_rate 2.692865 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.502834 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 34359338 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 35184491 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1543637 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 130959452 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.665444 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.660816 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1583973 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 131408979 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.656326 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.660791 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 34245793 26.15% 26.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 28403736 21.69% 47.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13297993 10.15% 57.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11400251 8.71% 66.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13789663 10.53% 77.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7417902 5.66% 82.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3851196 2.94% 85.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3914096 2.99% 88.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14638822 11.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34626776 26.35% 26.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 28501850 21.69% 48.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13315357 10.13% 58.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11364955 8.65% 66.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13794993 10.50% 77.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7395322 5.63% 82.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3829564 2.91% 85.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3937630 3.00% 88.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14642532 11.14% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 130959452 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 131408979 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037337 # Number of instructions committed system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -480,198 +480,198 @@ system.cpu.commit.branches 36546710 # Nu system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14638822 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14642532 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 499742506 # The number of ROB reads -system.cpu.rob.rob_writes 771826211 # The number of ROB writes -system.cpu.timesIdled 6299 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 210642 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 501013476 # The number of ROB reads +system.cpu.rob.rob_writes 773587232 # The number of ROB writes +system.cpu.timesIdled 6387 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 223029 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273036725 # Number of Instructions Simulated system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated -system.cpu.cpi 0.498628 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.498628 # CPI: Total CPI of All Threads -system.cpu.ipc 2.005503 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.005503 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1767787991 # number of integer regfile reads -system.cpu.int_regfile_writes 232574551 # number of integer regfile writes -system.cpu.fp_regfile_reads 188239368 # number of floating regfile reads -system.cpu.fp_regfile_writes 132566541 # number of floating regfile writes -system.cpu.misc_regfile_reads 566998882 # number of misc regfile reads +system.cpu.cpi 0.500725 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.500725 # CPI: Total CPI of All Threads +system.cpu.ipc 1.997106 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.997106 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1769939132 # number of integer regfile reads +system.cpu.int_regfile_writes 232882500 # number of integer regfile writes +system.cpu.fp_regfile_reads 188356577 # number of floating regfile reads +system.cpu.fp_regfile_writes 132592082 # number of floating regfile writes +system.cpu.misc_regfile_reads 567391435 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.icache.replacements 13918 # number of replacements -system.cpu.icache.tagsinuse 1846.260886 # Cycle average of tags in use -system.cpu.icache.total_refs 37359528 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15804 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2363.928626 # Average number of references to valid blocks. +system.cpu.icache.replacements 13893 # number of replacements +system.cpu.icache.tagsinuse 1849.968594 # Cycle average of tags in use +system.cpu.icache.total_refs 37534809 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 15782 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2378.330313 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1846.260886 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.901495 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.901495 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 37359528 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37359528 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37359528 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37359528 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37359528 # number of overall hits -system.cpu.icache.overall_hits::total 37359528 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17066 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17066 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17066 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17066 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17066 # number of overall misses -system.cpu.icache.overall_misses::total 17066 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 359194498 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 359194498 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 359194498 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 359194498 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 359194498 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 359194498 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37376594 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37376594 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37376594 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37376594 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37376594 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37376594 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000457 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000457 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000457 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000457 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000457 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000457 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21047.374780 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21047.374780 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21047.374780 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21047.374780 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21047.374780 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21047.374780 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 550 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1849.968594 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.903305 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.903305 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37534809 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37534809 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37534809 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37534809 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37534809 # number of overall hits +system.cpu.icache.overall_hits::total 37534809 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17059 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17059 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17059 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17059 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17059 # number of overall misses +system.cpu.icache.overall_misses::total 17059 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 362452498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 362452498 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 362452498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 362452498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 362452498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 362452498 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37551868 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37551868 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37551868 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37551868 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37551868 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37551868 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000454 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000454 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000454 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000454 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000454 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000454 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21246.995603 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21246.995603 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21246.995603 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21246.995603 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21246.995603 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21246.995603 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 477 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.947368 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.058824 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1259 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1259 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1259 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1259 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1259 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1259 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15807 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15807 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15807 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15807 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15807 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15807 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 293030998 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 293030998 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 293030998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 293030998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 293030998 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 293030998 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000423 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000423 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000423 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000423 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000423 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000423 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18538.052635 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18538.052635 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18538.052635 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18538.052635 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18538.052635 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18538.052635 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1275 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1275 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1275 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1275 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1275 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1275 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15784 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15784 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15784 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15784 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15784 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15784 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 296328498 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 296328498 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 296328498 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 296328498 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 296328498 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 296328498 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000420 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000420 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000420 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000420 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000420 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000420 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18773.979853 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18773.979853 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18773.979853 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18773.979853 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18773.979853 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18773.979853 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3947.622015 # Cycle average of tags in use -system.cpu.l2cache.total_refs 13172 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3956.608159 # Cycle average of tags in use +system.cpu.l2cache.total_refs 13151 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 5398 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.440163 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.436273 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 367.078870 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2774.586146 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 805.956999 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011202 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.084674 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.024596 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.120472 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 12765 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 296 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13061 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1039 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1039 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 17 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 17 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12765 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 313 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13078 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12765 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 313 # number of overall hits -system.cpu.l2cache.overall_hits::total 13078 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3040 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1500 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4540 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::writebacks 373.077110 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2771.508511 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 812.022538 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011385 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.084580 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.024781 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.120746 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 12748 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 293 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 13041 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1043 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1043 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 18 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 18 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 12748 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 311 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13059 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 12748 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 311 # number of overall hits +system.cpu.l2cache.overall_hits::total 13059 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3032 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1507 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4539 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 2797 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2797 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3040 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 4297 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7337 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3040 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 4297 # number of overall misses -system.cpu.l2cache.overall_misses::total 7337 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 149534000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 75407000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 224941000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 129040500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 129040500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 149534000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 204447500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 353981500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 149534000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 204447500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 353981500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 15805 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1796 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 17601 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1039 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1039 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 2792 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2792 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3032 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 4299 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7331 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3032 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 4299 # number of overall misses +system.cpu.l2cache.overall_misses::total 7331 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 153017500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 82832500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 235850000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 135162000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 135162000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 153017500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 217994500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 371012000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 153017500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 217994500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 371012000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 15780 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1800 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 17580 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1043 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1043 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2814 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2814 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 15805 # number of demand (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2810 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2810 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 15780 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4610 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 20415 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 15805 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 20390 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 15780 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4610 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 20415 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192344 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.835189 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.257940 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 20390 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192142 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.837222 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.258191 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993959 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.993959 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192344 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.932104 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.359393 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192344 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.932104 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.359393 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49188.815789 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50271.333333 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49546.475771 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46135.323561 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46135.323561 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49188.815789 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47579.124971 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 48246.081505 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49188.815789 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47579.124971 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 48246.081505 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993594 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.993594 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192142 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.932538 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.359539 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192142 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.932538 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.359539 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50467.513193 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54965.162575 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51960.784314 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48410.458453 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48410.458453 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50467.513193 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50708.187951 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 50608.648206 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50467.513193 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50708.187951 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 50608.648206 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -680,123 +680,123 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 13 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 40 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 51 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 53 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 40 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 51 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3029 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1460 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4489 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::total 53 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3019 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1467 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4486 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2797 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 2797 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3029 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 4257 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7286 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3029 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 4257 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7286 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110751088 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55451199 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 166202287 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2792 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 2792 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3019 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4259 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7278 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3019 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 4259 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7278 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115050359 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 62984754 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 178035113 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 94361392 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 94361392 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110751088 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 149812591 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 260563679 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110751088 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 149812591 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 260563679 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191648 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.812918 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255042 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100922692 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100922692 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115050359 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 163907446 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 278957805 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115050359 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 163907446 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 278957805 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.815000 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255176 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993959 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993959 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191648 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923427 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.356894 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191648 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923427 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.356894 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36563.581380 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37980.273288 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37024.345511 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993594 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993594 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923861 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.356940 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923861 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.356940 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38108.764160 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42934.392638 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39686.828578 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33736.643547 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33736.643547 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36563.581380 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35192.058022 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35762.239775 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36563.581380 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35192.058022 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35762.239775 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36147.095989 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36147.095989 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38108.764160 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38484.960319 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38328.909728 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38108.764160 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38484.960319 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38328.909728 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1413 # number of replacements -system.cpu.dcache.tagsinuse 3109.588822 # Cycle average of tags in use -system.cpu.dcache.total_refs 170749767 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3109.949983 # Cycle average of tags in use +system.cpu.dcache.total_refs 170925187 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4610 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37038.995011 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 37077.047072 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3109.588822 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.759177 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.759177 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88696383 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88696383 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82031533 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82031533 # number of WriteReq hits +system.cpu.dcache.occ_blocks::cpu.data 3109.949983 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.759265 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.759265 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 88871803 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88871803 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82031525 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82031525 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10952 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10952 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 170727916 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 170727916 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 170727916 # number of overall hits -system.cpu.dcache.overall_hits::total 170727916 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4041 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4041 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 21132 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 21132 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 170903328 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 170903328 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 170903328 # number of overall hits +system.cpu.dcache.overall_hits::total 170903328 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4023 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4023 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 21140 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 21140 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25173 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25173 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25173 # number of overall misses -system.cpu.dcache.overall_misses::total 25173 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 164980000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 164980000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 832721164 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 832721164 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 115000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 115000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 997701164 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 997701164 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 997701164 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 997701164 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88700424 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88700424 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 25163 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25163 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25163 # number of overall misses +system.cpu.dcache.overall_misses::total 25163 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 177641500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 177641500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 874574146 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 874574146 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 116000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 116000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1052215646 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1052215646 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1052215646 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1052215646 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88875826 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88875826 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10954 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10954 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 170753089 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 170753089 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 170753089 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 170753089 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 170928491 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 170928491 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 170928491 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 170928491 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000258 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000258 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000183 # miss rate for LoadLockedReq accesses @@ -805,52 +805,52 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40826.528087 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40826.528087 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39405.695817 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39405.695817 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39633.780797 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39633.780797 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39633.780797 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39633.780797 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 13427 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 751 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 430 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.225581 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 62.583333 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44156.475267 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 44156.475267 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41370.584011 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41370.584011 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 58000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 58000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41815.985614 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41815.985614 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41815.985614 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41815.985614 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15531 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 796 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 449 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.590200 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 61.230769 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1039 # number of writebacks -system.cpu.dcache.writebacks::total 1039 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2244 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2244 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18317 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18317 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1043 # number of writebacks +system.cpu.dcache.writebacks::total 1043 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2222 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2222 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18329 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18329 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20561 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20561 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20561 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20561 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1797 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1797 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2815 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2815 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 20551 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20551 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20551 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20551 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1801 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1801 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2811 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2811 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 4612 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 4612 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4612 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4612 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 80314500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 80314500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 132089500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 132089500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212404000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 212404000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212404000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 212404000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 87720000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 87720000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 138213500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 138213500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 225933500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 225933500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 225933500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 225933500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses @@ -859,14 +859,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44693.656093 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44693.656093 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46923.445826 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46923.445826 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46054.640069 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 46054.640069 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46054.640069 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 46054.640069 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48706.274292 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48706.274292 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49168.801138 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49168.801138 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48988.183001 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 48988.183001 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48988.183001 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 48988.183001 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |