diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-26 03:21:39 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-26 03:21:39 -0400 |
| commit | 4bc7dfb697bd779b12f1fd95fbe72144ae134055 (patch) | |
| tree | 532cea8e118ac27336792282c7023bb1b2d01be4 /tests/long/se/30.eon | |
| parent | cea1d14a937f27fa49423bd01eb900e578993a43 (diff) | |
| download | gem5-4bc7dfb697bd779b12f1fd95fbe72144ae134055.tar.xz | |
stats: Update MinorCPU regressions after accounting fix
Diffstat (limited to 'tests/long/se/30.eon')
| -rw-r--r-- | tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt | 678 | ||||
| -rw-r--r-- | tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt | 696 |
2 files changed, 687 insertions, 687 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index bccf5186d..5e6582f7a 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.226866 # Number of seconds simulated -sim_ticks 226865901500 # Number of ticks simulated -final_tick 226865901500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.226051 # Number of seconds simulated +sim_ticks 226051212500 # Number of ticks simulated +final_tick 226051212500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 324605 # Simulator instruction rate (inst/s) -host_op_rate 324605 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 184721178 # Simulator tick rate (ticks/s) -host_mem_usage 301676 # Number of bytes of host memory used -host_seconds 1228.15 # Real time elapsed on the host +host_inst_rate 313509 # Simulator instruction rate (inst/s) +host_op_rate 313509 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 177766322 # Simulator tick rate (ticks/s) +host_mem_usage 302576 # Number of bytes of host memory used +host_seconds 1271.62 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 249280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 249344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory -system.physmem.bytes_read::total 503872 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 249280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 249280 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3895 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 503936 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 249344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 249344 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3896 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1098799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1122214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2221012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1098799 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1098799 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1098799 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1122214 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2221012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7873 # Number of read requests accepted +system.physmem.num_reads::total 7874 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1103042 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1126258 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2229300 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1103042 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1103042 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1103042 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1126258 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2229300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7874 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7873 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7874 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 503872 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 503936 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 503872 # Total read bytes from the system interface side +system.physmem.bytesReadSys 503936 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -49,7 +49,7 @@ system.physmem.perBankRdBursts::4 475 # Pe system.physmem.perBankRdBursts::5 478 # Per bank write bursts system.physmem.perBankRdBursts::6 563 # Per bank write bursts system.physmem.perBankRdBursts::7 560 # Per bank write bursts -system.physmem.perBankRdBursts::8 469 # Per bank write bursts +system.physmem.perBankRdBursts::8 470 # Per bank write bursts system.physmem.perBankRdBursts::9 437 # Per bank write bursts system.physmem.perBankRdBursts::10 354 # Per bank write bursts system.physmem.perBankRdBursts::11 323 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 226865813000 # Total gap between requests +system.physmem.totGap 226051111000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7873 # Read request sizes (log2) +system.physmem.readPktSize::6 7874 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6816 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6818 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 82 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1561 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 321.065983 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 192.383190 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 328.308816 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 550 35.23% 35.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 344 22.04% 57.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 200 12.81% 70.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 103 6.60% 76.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 61 3.91% 80.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 52 3.33% 83.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 34 2.18% 86.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 30 1.92% 88.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 187 11.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1561 # Bytes accessed per row activation -system.physmem.totQLat 54380250 # Total ticks spent queuing -system.physmem.totMemAccLat 201999000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6907.18 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1564 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 321.964194 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 193.457187 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 327.645688 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 541 34.59% 34.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 357 22.83% 57.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 194 12.40% 69.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 101 6.46% 76.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 65 4.16% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 55 3.52% 83.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 35 2.24% 86.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 34 2.17% 88.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 182 11.64% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1564 # Bytes accessed per row activation +system.physmem.totQLat 54215500 # Total ticks spent queuing +system.physmem.totMemAccLat 201853000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 39370000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6885.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25657.18 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25635.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.23 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.22 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.23 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage @@ -216,70 +216,70 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6303 # Number of row buffer hits during reads +system.physmem.readRowHits 6308 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.06 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.11 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28815675.47 # Average gap between requests -system.physmem.pageHitRate 80.06 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6902280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3766125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 34164000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 28708548.51 # Average gap between requests +system.physmem.pageHitRate 80.11 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6872040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3749625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 34327800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14817404160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5855918085 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 130979493750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 151697648400 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.682686 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 217896983750 # Time in different power states -system.physmem_0.memoryStateTime::REF 7575360000 # Time in different power states +system.physmem_0.refreshEnergy 14764513920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5850636750 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 130498264500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 151158364635 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.692398 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 217093450250 # Time in different power states +system.physmem_0.memoryStateTime::REF 7548320000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1391017250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1408913500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4891320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2668875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 26910000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 4951800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2701875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 27042600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14817404160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5585732100 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 131216499000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 151654105455 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.490749 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 218290626750 # Time in different power states -system.physmem_1.memoryStateTime::REF 7575360000 # Time in different power states +system.physmem_1.refreshEnergy 14764513920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5592917520 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 130724334000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 151116461715 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.507029 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 217471574500 # Time in different power states +system.physmem_1.memoryStateTime::REF 7548320000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 994701750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1030789250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 46273750 # Number of BP lookups -system.cpu.branchPred.condPredicted 26730646 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1017469 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25595406 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21359943 # Number of BTB hits +system.cpu.branchPred.lookups 46270925 # Number of BP lookups +system.cpu.branchPred.condPredicted 26727379 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1017826 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 25620092 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21360644 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.452253 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 8341648 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 83.374580 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 8341960 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 95585469 # DTB read hits -system.cpu.dtb.read_misses 115 # DTB read misses +system.cpu.dtb.read_hits 95612151 # DTB read hits +system.cpu.dtb.read_misses 116 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 95585584 # DTB read accesses -system.cpu.dtb.write_hits 73606437 # DTB write hits -system.cpu.dtb.write_misses 857 # DTB write misses +system.cpu.dtb.read_accesses 95612267 # DTB read accesses +system.cpu.dtb.write_hits 73605971 # DTB write hits +system.cpu.dtb.write_misses 858 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73607294 # DTB write accesses -system.cpu.dtb.data_hits 169191906 # DTB hits -system.cpu.dtb.data_misses 972 # DTB misses +system.cpu.dtb.write_accesses 73606829 # DTB write accesses +system.cpu.dtb.data_hits 169218122 # DTB hits +system.cpu.dtb.data_misses 974 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 169192878 # DTB accesses -system.cpu.itb.fetch_hits 98781212 # ITB hits -system.cpu.itb.fetch_misses 1236 # ITB misses +system.cpu.dtb.data_accesses 169219096 # DTB accesses +system.cpu.itb.fetch_hits 98739643 # ITB hits +system.cpu.itb.fetch_misses 1232 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 98782448 # ITB accesses +system.cpu.itb.fetch_accesses 98740875 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,67 +293,67 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 453731803 # number of cpu cycles simulated +system.cpu.numCycles 452102425 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664665 # Number of instructions committed system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4467789 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 4488157 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.138129 # CPI: cycles per instruction -system.cpu.ipc 0.878635 # IPC: instructions per cycle -system.cpu.tickCycles 450174138 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3557665 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.134042 # CPI: cycles per instruction +system.cpu.ipc 0.881802 # IPC: instructions per cycle +system.cpu.tickCycles 448265843 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3836582 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.677539 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168028622 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3291.681680 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168032891 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40343.006483 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40344.031453 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3291.677539 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803632 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803632 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3291.681680 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803633 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803633 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336075633 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336075633 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 94513824 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94513824 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73514798 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73514798 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168028622 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168028622 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168028622 # number of overall hits -system.cpu.dcache.overall_hits::total 168028622 # number of overall hits +system.cpu.dcache.tags.tag_accesses 336084169 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336084169 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 94518092 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94518092 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73514799 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73514799 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168032891 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168032891 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168032891 # number of overall hits +system.cpu.dcache.overall_hits::total 168032891 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1180 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1180 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5932 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5932 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 7112 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7112 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7112 # number of overall misses -system.cpu.dcache.overall_misses::total 7112 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88706750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88706750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 435640500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 435640500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 524347250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 524347250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 524347250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 524347250 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 94515004 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94515004 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 5931 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5931 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 7111 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7111 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7111 # number of overall misses +system.cpu.dcache.overall_misses::total 7111 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88098000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88098000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 432683750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 432683750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 520781750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 520781750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 520781750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 520781750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 94519272 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94519272 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168035734 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168035734 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168035734 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168035734 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168040002 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168040002 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168040002 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168040002 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000012 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses @@ -362,14 +362,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75175.211864 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75175.211864 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73439.059339 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73439.059339 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73727.116142 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73727.116142 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73727.116142 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73727.116142 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74659.322034 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 74659.322034 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72952.916877 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 72952.916877 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73236.077907 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73236.077907 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73236.077907 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73236.077907 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,12 +382,12 @@ system.cpu.dcache.writebacks::writebacks 654 # nu system.cpu.dcache.writebacks::total 654 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 211 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2736 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2736 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2947 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2947 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2947 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2947 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2735 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2735 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2946 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2946 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2946 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2946 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses @@ -396,14 +396,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4165 system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70790750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 70790750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 240139250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 240139250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 310930000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 310930000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 310930000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 310930000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 69978250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 69978250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 238524000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 238524000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 308502250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 308502250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 308502250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 308502250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -412,68 +412,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73055.469556 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73055.469556 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75137.437422 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75137.437422 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74653.061224 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74653.061224 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74653.061224 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74653.061224 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72216.976264 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72216.976264 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74632.040050 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74632.040050 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74070.168067 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74070.168067 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74070.168067 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74070.168067 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 3196 # number of replacements -system.cpu.icache.tags.tagsinuse 1918.668562 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 98776038 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5174 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19090.846154 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 3197 # number of replacements +system.cpu.icache.tags.tagsinuse 1918.668517 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 98734468 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5175 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 19079.124251 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1918.668562 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1918.668517 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.936850 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.936850 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 397 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1281 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 197567598 # Number of tag accesses -system.cpu.icache.tags.data_accesses 197567598 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 98776038 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 98776038 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 98776038 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 98776038 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 98776038 # number of overall hits -system.cpu.icache.overall_hits::total 98776038 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5174 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5174 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5174 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5174 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5174 # number of overall misses -system.cpu.icache.overall_misses::total 5174 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 320697250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 320697250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 320697250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 320697250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 320697250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 320697250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 98781212 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 98781212 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 98781212 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 98781212 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 98781212 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 98781212 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 197484461 # Number of tag accesses +system.cpu.icache.tags.data_accesses 197484461 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 98734468 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 98734468 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 98734468 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 98734468 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 98734468 # number of overall hits +system.cpu.icache.overall_hits::total 98734468 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5175 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5175 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5175 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5175 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5175 # number of overall misses +system.cpu.icache.overall_misses::total 5175 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 322926000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 322926000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 322926000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 322926000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 322926000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 322926000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 98739643 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 98739643 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 98739643 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 98739643 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 98739643 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 98739643 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61982.460379 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61982.460379 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61982.460379 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61982.460379 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61982.460379 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61982.460379 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62401.159420 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62401.159420 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62401.159420 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62401.159420 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62401.159420 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62401.159420 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,52 +482,52 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5174 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 612 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4443 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160919 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 88415 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 88415 # Number of data accesses +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160950 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 88424 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 88424 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 1279 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 126 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1405 # 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number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 246135500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56978250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 303113750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 195592000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 195592000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 246135500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 252570250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 498705750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 246135500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 252570250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 498705750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.752850 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771210 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771247 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.752802 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.752850 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.843024 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.752802 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.843041 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.752850 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.843024 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62625.609756 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68716.706302 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63707.242399 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62865.556264 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62865.556264 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62625.609756 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64102.564103 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63371.872222 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62625.609756 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64102.564103 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63371.872222 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.843041 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63176.463039 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67750.594530 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63988.547604 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62350.015939 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62350.015939 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63176.463039 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63491.767220 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63335.756922 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63176.463039 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63491.767220 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63335.756922 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 6141 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 6141 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 6142 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 6142 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10348 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10350 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8984 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 19332 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 331136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 19334 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 331200 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 639552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 639616 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 9993 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 9994 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 9993 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 9994 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 9993 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5650500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 9994 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5651000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8584250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 8587500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7034000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7035750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 4736 # Transaction distribution -system.membus.trans_dist::ReadResp 4736 # Transaction distribution +system.membus.trans_dist::ReadReq 4737 # Transaction distribution +system.membus.trans_dist::ReadResp 4737 # Transaction distribution system.membus.trans_dist::ReadExReq 3137 # Transaction distribution system.membus.trans_dist::ReadExResp 3137 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15746 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15746 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 503872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 503872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15748 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15748 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 503936 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 503936 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7873 # Request fanout histogram +system.membus.snoop_fanout::samples 7874 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7873 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7874 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7873 # Request fanout histogram -system.membus.reqLayer0.occupancy 9289000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7874 # Request fanout histogram +system.membus.reqLayer0.occupancy 9179500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 41806250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 41811750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 592625271..572510825 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.216744 # Number of seconds simulated -sim_ticks 216744260000 # Number of ticks simulated -final_tick 216744260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.216140 # Number of seconds simulated +sim_ticks 216139917000 # Number of ticks simulated +final_tick 216139917000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 172626 # Simulator instruction rate (inst/s) -host_op_rate 207257 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 137034779 # Simulator tick rate (ticks/s) -host_mem_usage 322768 # Number of bytes of host memory used -host_seconds 1581.67 # Real time elapsed on the host +host_inst_rate 173188 # Simulator instruction rate (inst/s) +host_op_rate 207931 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 137097336 # Simulator tick rate (ticks/s) +host_mem_usage 323040 # Number of bytes of host memory used +host_seconds 1576.54 # Real time elapsed on the host sim_insts 273037857 # Number of instructions simulated sim_ops 327812214 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 218944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 219136 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 266368 # Number of bytes read from this memory -system.physmem.bytes_read::total 485312 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 218944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 218944 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3421 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 485504 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219136 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1010149 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1228951 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2239100 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1010149 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1010149 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1010149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1228951 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2239100 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7583 # Number of read requests accepted +system.physmem.num_reads::total 7586 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1013862 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1232387 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2246249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1013862 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1013862 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1013862 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1232387 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2246249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7586 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7583 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7586 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 485312 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 485504 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 485312 # Total read bytes from the system interface side +system.physmem.bytesReadSys 485504 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -46,7 +46,7 @@ system.physmem.perBankRdBursts::1 843 # Pe system.physmem.perBankRdBursts::2 628 # Per bank write bursts system.physmem.perBankRdBursts::3 541 # Per bank write bursts system.physmem.perBankRdBursts::4 466 # Per bank write bursts -system.physmem.perBankRdBursts::5 348 # Per bank write bursts +system.physmem.perBankRdBursts::5 349 # Per bank write bursts system.physmem.perBankRdBursts::6 173 # Per bank write bursts system.physmem.perBankRdBursts::7 228 # Per bank write bursts system.physmem.perBankRdBursts::8 209 # Per bank write bursts @@ -55,8 +55,8 @@ system.physmem.perBankRdBursts::10 342 # Pe system.physmem.perBankRdBursts::11 428 # Per bank write bursts system.physmem.perBankRdBursts::12 553 # Per bank write bursts system.physmem.perBankRdBursts::13 706 # Per bank write bursts -system.physmem.perBankRdBursts::14 637 # Per bank write bursts -system.physmem.perBankRdBursts::15 540 # Per bank write bursts +system.physmem.perBankRdBursts::14 638 # Per bank write bursts +system.physmem.perBankRdBursts::15 541 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 216744023500 # Total gap between requests +system.physmem.totGap 216139680500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7583 # Read request sizes (log2) +system.physmem.readPktSize::6 7586 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6627 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6624 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 901 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1519 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 318.314681 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.160813 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 331.826555 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 551 36.27% 36.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 356 23.44% 59.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 165 10.86% 70.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 80 5.27% 75.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 68 4.48% 80.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 50 3.29% 83.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 36 2.37% 85.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 26 1.71% 87.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 187 12.31% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1519 # Bytes accessed per row activation -system.physmem.totQLat 54921500 # Total ticks spent queuing -system.physmem.totMemAccLat 197102750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37915000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7242.71 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1523 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 318.319107 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.795582 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.243204 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 551 36.18% 36.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 346 22.72% 58.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 176 11.56% 70.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 81 5.32% 75.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 75 4.92% 80.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 50 3.28% 83.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 32 2.10% 86.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 28 1.84% 87.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 184 12.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1523 # Bytes accessed per row activation +system.physmem.totQLat 53007250 # Total ticks spent queuing +system.physmem.totMemAccLat 195244750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37930000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6987.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25992.71 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25737.51 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.24 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.25 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6057 # Number of row buffer hits during reads +system.physmem.readRowHits 6060 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 79.88 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28582885.86 # Average gap between requests +system.physmem.avgGap 28491916.75 # Average gap between requests system.physmem.pageHitRate 79.88 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5027400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2743125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ) +system.physmem_0.actEnergy 5004720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2730750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 30022200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14156276160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5639665500 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 125095914000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 144929531385 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.684406 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 208108813000 # Time in different power states -system.physmem_0.memoryStateTime::REF 7237360000 # Time in different power states +system.physmem_0.refreshEnergy 14117117040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5648540400 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 124728404250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 144531819360 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.699173 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 207494790250 # Time in different power states +system.physmem_0.memoryStateTime::REF 7217340000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1394961500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1426657250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6433560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3510375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 28984800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 6509160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3551625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 29062800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14156276160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5856004440 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 124906143000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 144957352335 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.812768 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 207790968250 # Time in different power states -system.physmem_1.memoryStateTime::REF 7237360000 # Time in different power states +system.physmem_1.refreshEnergy 14117117040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5781551040 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 124611728250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 144549519915 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.781068 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 207298156250 # Time in different power states +system.physmem_1.memoryStateTime::REF 7217340000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1713539250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1623563250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 33185861 # Number of BP lookups -system.cpu.branchPred.condPredicted 17151464 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1557357 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17401044 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15621725 # Number of BTB hits +system.cpu.branchPred.lookups 33139216 # Number of BP lookups +system.cpu.branchPred.condPredicted 17107199 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1560655 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17520877 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15610870 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.774642 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6610647 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 89.098679 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6611023 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,81 +377,81 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 433488520 # number of cpu cycles simulated +system.cpu.numCycles 432279834 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 273037857 # Number of instructions committed system.cpu.committedOps 327812214 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4013329 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 4207498 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.587650 # CPI: cycles per instruction -system.cpu.ipc 0.629862 # IPC: instructions per cycle -system.cpu.tickCycles 429966989 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3521531 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.583223 # CPI: cycles per instruction +system.cpu.ipc 0.631623 # IPC: instructions per cycle +system.cpu.tickCycles 428628441 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3651393 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 1354 # number of replacements -system.cpu.dcache.tags.tagsinuse 3085.753926 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168769445 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3085.737950 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168771151 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37412.867435 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37413.245622 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3085.753926 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.753358 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.753358 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3085.737950 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.753354 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.753354 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 337557971 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 337557971 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 86636657 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86636657 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82047457 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047457 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 63541 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 63541 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 337561379 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337561379 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86638362 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86638362 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82047459 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047459 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 63540 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 63540 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168684114 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168684114 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168747655 # number of overall hits -system.cpu.dcache.overall_hits::total 168747655 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 168685821 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168685821 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168749361 # number of overall hits +system.cpu.dcache.overall_hits::total 168749361 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 2059 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2059 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5220 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5220 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5218 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5218 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 6 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 6 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 7279 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7279 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7285 # number of overall misses -system.cpu.dcache.overall_misses::total 7285 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 137443456 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 137443456 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 400907250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 400907250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 538350706 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 538350706 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 538350706 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 538350706 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86638716 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86638716 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7277 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7277 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7283 # number of overall misses +system.cpu.dcache.overall_misses::total 7283 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 136967456 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 136967456 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 400451000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 400451000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 537418456 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 537418456 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 537418456 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 537418456 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86640421 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86640421 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 63547 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 63547 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 63546 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 63546 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168691393 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168691393 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168754940 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168754940 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168693098 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168693098 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168756644 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168756644 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses @@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66752.528412 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66752.528412 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76802.155172 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76802.155172 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73959.432065 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73959.432065 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73898.518325 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73898.518325 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66521.348227 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66521.348227 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76744.154849 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76744.154849 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73851.649856 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73851.649856 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73790.808183 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73790.808183 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,12 +482,12 @@ system.cpu.dcache.writebacks::writebacks 1010 # nu system.cpu.dcache.writebacks::total 1010 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2350 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2350 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2772 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2772 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2772 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2772 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2348 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2348 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2770 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2770 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2770 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2770 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1637 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1637 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses @@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4507 system.cpu.dcache.demand_mshr_misses::total 4507 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109995542 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 109995542 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 220772750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 220772750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 108888792 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 108888792 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 220256750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 220256750 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 320750 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 320750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 330768292 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 330768292 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 331089042 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 331089042 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329145542 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 329145542 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329466292 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 329466292 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -518,71 +518,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67193.367135 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67193.367135 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76924.303136 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76924.303136 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66517.282834 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66517.282834 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76744.512195 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76744.512195 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80187.500000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80187.500000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73389.902818 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73389.902818 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73395.930392 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73395.930392 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73029.851786 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73029.851786 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73036.198626 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73036.198626 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 36918 # number of replacements -system.cpu.icache.tags.tagsinuse 1924.846019 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 73120141 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 38855 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1881.872114 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 36928 # number of replacements +system.cpu.icache.tags.tagsinuse 1924.841098 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 73108223 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 38865 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1881.081256 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1924.846019 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939866 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939866 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.841098 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939864 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939864 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 274 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1490 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1487 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146356849 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146356849 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 73120141 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 73120141 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 73120141 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 73120141 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 73120141 # number of overall hits -system.cpu.icache.overall_hits::total 73120141 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 38856 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 38856 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 38856 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 38856 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 38856 # number of overall misses -system.cpu.icache.overall_misses::total 38856 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 728255248 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 728255248 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 728255248 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 728255248 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 728255248 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 728255248 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 73158997 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 73158997 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 73158997 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 73158997 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 73158997 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 73158997 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 146333043 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146333043 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 73108223 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 73108223 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 73108223 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 73108223 # 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miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000531 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000531 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000531 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18742.414247 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18742.414247 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18742.414247 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18742.414247 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18742.414247 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18742.414247 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18734.375753 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18734.375753 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18734.375753 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18734.375753 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18734.375753 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18734.375753 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,123 +591,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38856 # 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number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 668381252 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000531 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000531 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000531 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17205.251493 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17205.251493 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17205.251493 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17205.251493 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17205.251493 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17205.251493 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17197.068183 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17197.068183 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17197.068183 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17197.068183 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17197.068183 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17197.068183 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # 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number of ReadReq hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1252 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4261 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172363 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 363614 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 363614 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 35440 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 291 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 35724 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 35731 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 1010 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 1010 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 16 # 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number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 38856 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 7630 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 257404250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 104503500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 361907750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 217183750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 217183750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 257404250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 321687250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 579091500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 257404250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 321687250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 579091500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 38866 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1641 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 40497 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 40507 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 1010 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 1010 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 2870 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 2870 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 38856 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 38866 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4511 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 43367 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 38856 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 43377 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 38866 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4511 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 43367 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.088095 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 43377 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.088149 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.822669 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.117861 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.117906 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994425 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.994425 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088095 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088149 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.931944 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.175871 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088095 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.175900 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088149 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.931944 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.175871 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75265.483494 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78229.814815 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 76103.917871 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76278.819201 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76278.819201 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75265.483494 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76905.328259 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76169.365412 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75265.483494 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76905.328259 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76169.365412 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.175900 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75132.589025 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77410 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75776.329564 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76098.020322 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76098.020322 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75132.589025 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76519.326832 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75896.657929 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75132.589025 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76519.326832 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75896.657929 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -725,102 +725,102 @@ system.cpu.l2cache.demand_mshr_hits::total 44 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 42 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 44 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3421 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3424 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1308 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4729 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4732 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2854 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 2854 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3421 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3424 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 4162 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7583 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3421 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7586 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3424 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4162 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7583 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 214664750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 86513250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 301178000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 181997750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 181997750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 214664750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 268511000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 483175750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 214664750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 268511000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 483175750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088043 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 7586 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 214398750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 85427750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 299826500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 181482250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 181482250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 214398750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 266910000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 481308750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 214398750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 266910000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 481308750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088098 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.797075 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116774 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116819 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088043 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088098 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.174856 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088043 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.174885 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088098 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.174856 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62749.123063 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66141.628440 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63687.460351 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63769.358795 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63769.358795 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62749.123063 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64514.896684 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63718.284320 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62749.123063 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64514.896684 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63718.284320 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.174885 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62616.457360 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65311.735474 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63361.475063 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63588.735109 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63588.735109 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62616.457360 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64130.225853 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63446.974690 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62616.457360 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64130.225853 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63446.974690 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 40497 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 40496 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 40507 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 40506 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77711 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77731 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10032 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 87743 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2486720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 87763 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2487360 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2840064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2840704 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 44377 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 44387 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 44377 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 44387 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 44377 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 23198500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 44387 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 23203500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 59005248 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 59023248 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7577458 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7574708 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 4729 # Transaction distribution -system.membus.trans_dist::ReadResp 4729 # Transaction distribution +system.membus.trans_dist::ReadReq 4732 # Transaction distribution +system.membus.trans_dist::ReadResp 4732 # Transaction distribution system.membus.trans_dist::ReadExReq 2854 # Transaction distribution system.membus.trans_dist::ReadExResp 2854 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15166 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15166 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15172 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15172 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 485504 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7583 # Request fanout histogram +system.membus.snoop_fanout::samples 7586 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7583 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7586 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7583 # Request fanout histogram -system.membus.reqLayer0.occupancy 8950500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7586 # Request fanout histogram +system.membus.reqLayer0.occupancy 8848500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 40258250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40266750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |