diff options
| author | Andrew Bardsley <Andrew.Bardsley@arm.com> | 2014-07-23 16:09:05 -0500 |
|---|---|---|
| committer | Andrew Bardsley <Andrew.Bardsley@arm.com> | 2014-07-23 16:09:05 -0500 |
| commit | 5d0b25ba3f82b6d563b3fabd3de71f3ceabb140d (patch) | |
| tree | 0b8cdef424988f3486a9f2cebbb49f76b74ae8f9 /tests/long/se/30.eon | |
| parent | 0e8a90f06bd3db00f700891a33458353478cce76 (diff) | |
| download | gem5-5d0b25ba3f82b6d563b3fabd3de71f3ceabb140d.tar.xz | |
cpu: Minor CPU add regression tests for ARM and ALPHA
This patch adds regression tests results and test harnesses
for the Minor CPU on ARM and ALPHA.
Diffstat (limited to 'tests/long/se/30.eon')
8 files changed, 3007 insertions, 0 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini new file mode 100644 index 000000000..e4aa5eab5 --- /dev/null +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini @@ -0,0 +1,718 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=AlphaTLB +eventq_index=0 +size=64 + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=AlphaInterrupts +eventq_index=0 + +[system.cpu.isa] +type=AlphaISA +eventq_index=0 +system=system + +[system.cpu.itb] +type=AlphaTLB +eventq_index=0 +size=48 + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentBus +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook +cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/arm/projectscratch/pd/sysrandd/dist/cpu2000/binaries/alpha/tru64/eon +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.membus] +type=CoherentBus +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.physmem] +type=DRAMCtrl +activation_limit=4 +addr_mapping=RoRaBaChCo +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCL=13750 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=300000 +tRP=13750 +tRRD=6250 +tWTR=7500 +tXAW=40000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simerr new file mode 100644 index 000000000..abe1622a9 --- /dev/null +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simerr @@ -0,0 +1,51 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +getting pixel output filename pixels_out.cook +opening control file chair.control.cook +opening camera file chair.camera +opening surfaces file chair.surfaces +reading data +processing 8parts +Grid measure is 6 by 3.0001 by 6 +cell dimension is 0.863065 +Creating grid for list of length 21 +Grid size = 7 by 4 by 7 +Total occupancy = 236 +reading control stream +reading camera stream +Writing to chair.cook.ppm +calculating 15 by 15 image with 196 samples +col 0. . . +col 1. . . +col 2. . . +col 3. . . +col 4. . . +col 5. . . +col 6. . . +col 7. . . +col 8. . . +col 9. . . +col 10. . . +col 11. . . +col 12. . . +col 13. . . +col 14. . . +Writing to chair.cook.ppm +0 8 14 +1 8 14 +2 8 14 +3 8 14 +4 8 14 +5 8 14 +6 8 14 +7 8 14 +8 8 14 +9 8 14 +10 8 14 +11 8 14 +12 8 14 +13 8 14 +14 8 14 +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout new file mode 100644 index 000000000..2951870e8 --- /dev/null +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout @@ -0,0 +1,16 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 7 2014 10:41:53 +gem5 started May 7 2014 10:42:15 +gem5 executing on cz3212c2d7 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Eon, Version 1.1 +info: Increasing stack size by one page. +OO-style eon Time= 0.216667 +Exiting @ tick 220685290500 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt new file mode 100644 index 000000000..12f448f86 --- /dev/null +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -0,0 +1,631 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 220685053500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 266134 # Simulator instruction rate (inst/s) +host_mem_usage 254064 # Number of bytes of host memory used +host_op_rate 266134 # Simulator op (including micro ops) rate (op/s) +host_seconds 1497.99 # Real time elapsed on the host +host_tick_rate 147321061 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 398664665 # Number of instructions simulated +sim_ops 398664665 # Number of ops (including micro ops) simulated +sim_seconds 0.220685 # Number of seconds simulated +sim_ticks 220685053500 # Number of ticks simulated +system.clk_domain.clock 1000 # Clock period in ticks +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 83.751650 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 21330181 # Number of BTB hits +system.cpu.branchPred.BTBLookups 25468371 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 1012944 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 26708480 # Number of conditional branches predicted +system.cpu.branchPred.lookups 46221019 # Number of BP lookups +system.cpu.branchPred.usedRAS 8327448 # Number of times the RAS was used to get a target. +system.cpu.committedInsts 398664665 # Number of instructions committed +system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed +system.cpu.cpi 1.107121 # CPI: cycles per instruction +system.cpu.dcache.ReadReq_accesses::cpu.inst 94494338 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94494338 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68449.404762 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68449.404762 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66089.617769 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66089.617769 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits::cpu.inst 94493162 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94493162 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 80496500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 80496500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::cpu.inst 1176 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1176 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 208 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 208 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 63974750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 63974750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 968 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 968 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses::cpu.inst 73520730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66549.865343 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66549.865343 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67934.000626 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67934.000626 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits::cpu.inst 73514789 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73514789 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 395372750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 395372750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000081 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000081 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::cpu.inst 5941 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5941 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2744 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2744 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 217185000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 217185000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 3197 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3197 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses::cpu.inst 168015068 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168015068 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66863.741745 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66863.741745 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67505.342137 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67505.342137 # average overall mshr miss latency +system.cpu.dcache.demand_hits::cpu.inst 168007951 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168007951 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency::cpu.inst 475869250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 475869250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses +system.cpu.dcache.demand_misses::cpu.inst 7117 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7117 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits::cpu.inst 2952 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2952 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 281159750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 281159750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses::cpu.inst 4165 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses::cpu.inst 168015068 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168015068 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66863.741745 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66863.741745 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67505.342137 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67505.342137 # average overall mshr miss latency +system.cpu.dcache.overall_hits::cpu.inst 168007951 # number of overall hits +system.cpu.dcache.overall_hits::total 168007951 # number of overall hits +system.cpu.dcache.overall_miss_latency::cpu.inst 475869250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 475869250 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses +system.cpu.dcache.overall_misses::cpu.inst 7117 # number of overall misses +system.cpu.dcache.overall_misses::total 7117 # number of overall misses +system.cpu.dcache.overall_mshr_hits::cpu.inst 2952 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2952 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 281159750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 281159750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses::cpu.inst 4165 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses +system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 # Occupied blocks per task id +system.cpu.dcache.tags.avg_refs 40338.043457 # Average number of references to valid blocks. +system.cpu.dcache.tags.data_accesses 336034301 # Number of data accesses +system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.724304 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.803644 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803644 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.replacements 771 # number of replacements +system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. +system.cpu.dcache.tags.tag_accesses 336034301 # Number of tag accesses +system.cpu.dcache.tags.tagsinuse 3291.724304 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168007951 # Total number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks::writebacks 654 # number of writebacks +system.cpu.dcache.writebacks::total 654 # number of writebacks +system.cpu.discardedOps 4407642 # Number of ops (including micro ops) which were discarded before commit +system.cpu.dtb.data_accesses 169201829 # DTB accesses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_hits 169200862 # DTB hits +system.cpu.dtb.data_misses 967 # DTB misses +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.read_accesses 95596602 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 95596493 # DTB read hits +system.cpu.dtb.read_misses 109 # DTB read misses +system.cpu.dtb.write_accesses 73605227 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 73604369 # DTB write hits +system.cpu.dtb.write_misses 858 # DTB write misses +system.cpu.icache.ReadReq_accesses::cpu.inst 98039875 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 98039875 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56706.988208 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56706.988208 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54392.373864 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54392.373864 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::cpu.inst 98034702 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 98034702 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency::cpu.inst 293345250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 293345250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000053 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::cpu.inst 5173 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5173 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281371750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 281371750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5173 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 5173 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses::cpu.inst 98039875 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 98039875 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56706.988208 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56706.988208 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54392.373864 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54392.373864 # average overall mshr miss latency +system.cpu.icache.demand_hits::cpu.inst 98034702 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 98034702 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency::cpu.inst 293345250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 293345250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::cpu.inst 0.000053 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses +system.cpu.icache.demand_misses::cpu.inst 5173 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5173 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281371750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 281371750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses::cpu.inst 5173 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses::cpu.inst 98039875 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 98039875 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56706.988208 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56706.988208 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54392.373864 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54392.373864 # average overall mshr miss latency +system.cpu.icache.overall_hits::cpu.inst 98034702 # number of overall hits +system.cpu.icache.overall_hits::total 98034702 # number of overall hits +system.cpu.icache.overall_miss_latency::cpu.inst 293345250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 293345250 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::cpu.inst 0.000053 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses +system.cpu.icache.overall_misses::cpu.inst 5173 # number of overall misses +system.cpu.icache.overall_misses::total 5173 # number of overall misses +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281371750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 281371750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses::cpu.inst 5173 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 5173 # number of overall MSHR misses +system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 200 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 398 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1282 # Occupied blocks per task id +system.cpu.icache.tags.avg_refs 18951.227914 # Average number of references to valid blocks. +system.cpu.icache.tags.data_accesses 196084923 # Number of data accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1919.700868 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.937354 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.937354 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id +system.cpu.icache.tags.replacements 3195 # number of replacements +system.cpu.icache.tags.sampled_refs 5173 # Sample count of references to valid blocks. +system.cpu.icache.tags.tag_accesses 196084923 # Number of tag accesses +system.cpu.icache.tags.tagsinuse 1919.700868 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 98034702 # Total number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.idleCycles 3993538 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.ipc 0.903243 # IPC: instructions per cycle +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.fetch_accesses 98041099 # ITB accesses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_hits 98039875 # ITB hits +system.cpu.itb.fetch_misses 1224 # ITB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 3199 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 3199 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68031.548757 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68031.548757 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55379.700446 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55379.700446 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.inst 61 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 61 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 213483000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 213483000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.980932 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.980932 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 3138 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 3138 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 173781500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 173781500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.980932 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980932 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 3138 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3138 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses::cpu.inst 6139 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 6139 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68618.957146 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68618.957146 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56083.175005 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56083.175005 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits::cpu.inst 1402 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1402 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 325048000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 325048000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.771624 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.771624 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses::cpu.inst 4737 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4737 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 265666000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 265666000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.771624 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771624 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4737 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4737 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses::writebacks 654 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 654 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits::writebacks 654 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 654 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses::cpu.inst 9338 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9338 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68384.888889 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68384.888889 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55802.857143 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55802.857143 # average overall mshr miss latency +system.cpu.l2cache.demand_hits::cpu.inst 1463 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1463 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency::cpu.inst 538531000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 538531000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.843328 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.843328 # miss rate for demand accesses +system.cpu.l2cache.demand_misses::cpu.inst 7875 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7875 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 439447500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 439447500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.843328 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.843328 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7875 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7875 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses::cpu.inst 9338 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9338 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68384.888889 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68384.888889 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55802.857143 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55802.857143 # average overall mshr miss latency +system.cpu.l2cache.overall_hits::cpu.inst 1463 # number of overall hits +system.cpu.l2cache.overall_hits::total 1463 # number of overall hits +system.cpu.l2cache.overall_miss_latency::cpu.inst 538531000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 538531000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.843328 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.843328 # miss rate for overall accesses +system.cpu.l2cache.overall_misses::cpu.inst 7875 # number of overall misses +system.cpu.l2cache.overall_misses::total 7875 # number of overall misses +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 439447500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 439447500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.843328 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.843328 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7875 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7875 # number of overall MSHR misses +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 612 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4444 # Occupied blocks per task id +system.cpu.l2cache.tags.avg_refs 0.282708 # Average number of references to valid blocks. +system.cpu.l2cache.tags.data_accesses 88409 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 373.078063 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4054.561025 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011385 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123735 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.135121 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5274 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160950 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.sampled_refs 5274 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.tag_accesses 88409 # Number of tag accesses +system.cpu.l2cache.tags.tagsinuse 4427.639089 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1491 # Total number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.numCycles 441370107 # number of cpu cycles simulated +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.tickCycles 437376569 # Number of cycles that the CPU actually ticked +system.cpu.toL2Bus.data_through_bus 639488 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10346 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8984 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 19330 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 5650000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 8573250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 6973250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.throughput 2897740 # Throughput (bytes/s) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 331072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 639488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 6139 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 6139 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3199 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3199 # Transaction distribution +system.cpu.workload.num_syscalls 215 # Number of system calls +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.membus.data_through_bus 504000 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15750 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15750 # Packet count per connected master and slave (bytes) +system.membus.reqLayer0.occupancy 9402000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 73919000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.throughput 2283798 # Throughput (bytes/s) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 504000 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 504000 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 4737 # Transaction distribution +system.membus.trans_dist::ReadResp 4737 # Transaction distribution +system.membus.trans_dist::ReadExReq 3138 # Transaction distribution +system.membus.trans_dist::ReadExResp 3138 # Transaction distribution +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgGap 28023488.51 # Average gap between requests +system.physmem.avgMemAccLat 25444.19 # Average memory access latency per DRAM burst +system.physmem.avgQLat 6694.19 # Average queueing delay per DRAM burst +system.physmem.avgRdBW 2.28 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.28 # Average system read bandwidth in MiByte/s +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.bw_inst_read::cpu.inst 1130154 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1130154 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 2283798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2283798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2283798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2283798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytesPerActivate::samples 1519 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 329.859118 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 197.497740 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 333.655221 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 518 34.10% 34.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 348 22.91% 57.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 182 11.98% 68.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 96 6.32% 75.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 63 4.15% 79.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 48 3.16% 82.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 42 2.76% 85.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 38 2.50% 87.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 184 12.11% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1519 # Bytes accessed per row activation +system.physmem.bytesReadDRAM 504000 # Total number of bytes read from DRAM +system.physmem.bytesReadSys 504000 # Total read bytes from the system interface side +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.bytes_inst_read::cpu.inst 249408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 249408 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 504000 # Number of bytes read from this memory +system.physmem.bytes_read::total 504000 # Number of bytes read from this memory +system.physmem.memoryStateTime::IDLE 211586881750 # Time in different power states +system.physmem.memoryStateTime::REF 7368920000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 1722369500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.num_reads::cpu.inst 7875 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7875 # Number of read requests responded to by this memory +system.physmem.pageHitRate 80.58 # Row buffer hit rate, read and write combined +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.perBankRdBursts::0 551 # Per bank write bursts +system.physmem.perBankRdBursts::1 675 # Per bank write bursts +system.physmem.perBankRdBursts::2 471 # Per bank write bursts +system.physmem.perBankRdBursts::3 633 # Per bank write bursts +system.physmem.perBankRdBursts::4 475 # Per bank write bursts +system.physmem.perBankRdBursts::5 478 # Per bank write bursts +system.physmem.perBankRdBursts::6 564 # Per bank write bursts +system.physmem.perBankRdBursts::7 560 # Per bank write bursts +system.physmem.perBankRdBursts::8 471 # Per bank write bursts +system.physmem.perBankRdBursts::9 437 # Per bank write bursts +system.physmem.perBankRdBursts::10 354 # Per bank write bursts +system.physmem.perBankRdBursts::11 324 # Per bank write bursts +system.physmem.perBankRdBursts::12 430 # Per bank write bursts +system.physmem.perBankRdBursts::13 556 # Per bank write bursts +system.physmem.perBankRdBursts::14 473 # Per bank write bursts +system.physmem.perBankRdBursts::15 423 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.rdQLenPdf::0 6827 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 967 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 81 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.readBursts 7875 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 7875 # Read request sizes (log2) +system.physmem.readReqs 7875 # Number of read requests accepted +system.physmem.readRowHitRate 80.58 # Row buffer hit rate for reads +system.physmem.readRowHits 6346 # Number of row buffer hits during reads +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.totBusLat 39375000 # Total ticks spent in databus transfers +system.physmem.totGap 220684972000 # Total gap between requests +system.physmem.totMemAccLat 200373000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 52716750 # Total ticks spent queuing +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What 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write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.voltage_domain.voltage 1 # Voltage in Volts + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini new file mode 100644 index 000000000..396ce5f1d --- /dev/null +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini @@ -0,0 +1,816 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=262144 + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[3] + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming 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+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentBus +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook +cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/arm/projectscratch/pd/sysrandd/dist/cpu2000/binaries/arm/linux/eon +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.membus] +type=CoherentBus +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.physmem] +type=DRAMCtrl +activation_limit=4 +addr_mapping=RoRaBaChCo +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCL=13750 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=300000 +tRP=13750 +tRRD=6250 +tWTR=7500 +tXAW=40000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simerr new file mode 100644 index 000000000..956bfed52 --- /dev/null +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simerr @@ -0,0 +1,57 @@ +warn: Sockets disabled, not accepting gdb connections +getting pixel output filename pixels_out.cook +opening control file chair.control.cook +opening camera file chair.camera +opening surfaces file chair.surfaces +reading data +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +processing 8parts +Grid measure is 6 by 3.0001 by 6 +cell dimension is 0.863065 +Creating grid for list of length 21 +Grid size = 7 by 4 by 7 +Total occupancy = 236 +reading control stream +reading camera stream +Writing to chair.cook.ppm +calculating 15 by 15 image with 196 samples +warn: User mode does not have SPSR +warn: User mode does not have SPSR +col 0. . . +col 1. . . +col 2. . . +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +col 3. . . +col 4. . . +col 5. . . +col 6. . . +col 7. . . +col 8. . . +col 9. . . +col 10. . . +col 11. . . +col 12. . . +col 13. . . +col 14. . . +Writing to chair.cook.ppm +0 8 14 +1 8 14 +2 8 14 +3 8 14 +4 8 14 +5 8 14 +6 8 14 +7 8 14 +8 8 14 +9 8 14 +10 8 14 +11 8 14 +12 8 14 +13 8 14 +14 8 14 diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout new file mode 100644 index 000000000..6f527f164 --- /dev/null +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout @@ -0,0 +1,19 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 7 2014 10:57:46 +gem5 started May 7 2014 12:10:42 +gem5 executing on cz3211bhr8 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing +Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0xc928260 +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Eon, Version 1.1 +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +OO-style eon Time= 0.220000 +Exiting @ tick 227450162000 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt new file mode 100644 index 000000000..0a05ac469 --- /dev/null +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -0,0 +1,699 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 227445516000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 153700 # Simulator instruction rate (inst/s) +host_mem_usage 303376 # Number of bytes of host memory used +host_op_rate 196498 # Simulator op (including micro ops) rate (op/s) +host_seconds 1776.44 # Real time elapsed on the host +host_tick_rate 128034740 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 273037854 # Number of instructions simulated +sim_ops 349065592 # Number of ops (including micro ops) simulated +sim_seconds 0.227446 # Number of seconds simulated +sim_ticks 227445516000 # Number of ticks simulated +system.clk_domain.clock 1000 # Clock period in ticks +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 83.362247 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 16723894 # Number of BTB hits +system.cpu.branchPred.BTBLookups 20061712 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 121 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 1671536 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 21059526 # Number of conditional branches predicted +system.cpu.branchPred.lookups 35363260 # Number of BP lookups +system.cpu.branchPred.usedRAS 6617396 # Number of times the RAS was used to get a target. +system.cpu.committedInsts 273037854 # Number of instructions committed +system.cpu.committedOps 349065592 # Number of ops (including micro ops) committed +system.cpu.cpi 1.666037 # CPI: cycles per instruction +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 10895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 10895 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses::cpu.inst 95145110 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 95145110 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61749.740048 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61749.740048 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61620.734497 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61620.734497 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits::cpu.inst 95143025 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 95143025 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 128748208 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 128748208 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::cpu.inst 2085 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2085 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 424 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 102352040 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 102352040 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000017 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1661 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1661 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::cpu.inst 10895 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68469.206380 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 68469.206380 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68654.108392 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68654.108392 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits::cpu.inst 82047473 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047473 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 356313750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 356313750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000063 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000063 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::cpu.inst 5204 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5204 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2344 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2344 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 196350750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 196350750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2860 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2860 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses::cpu.inst 177197787 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 177197787 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66547.120044 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66547.120044 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66070.070781 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66070.070781 # average overall mshr miss latency +system.cpu.dcache.demand_hits::cpu.inst 177190498 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 177190498 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency::cpu.inst 485061958 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 485061958 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000041 # miss rate for demand accesses +system.cpu.dcache.demand_misses::cpu.inst 7289 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7289 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits::cpu.inst 2768 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2768 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 298702790 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 298702790 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses::cpu.inst 4521 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4521 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses::cpu.inst 177197787 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 177197787 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66547.120044 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66547.120044 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66070.070781 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66070.070781 # average overall mshr miss latency +system.cpu.dcache.overall_hits::cpu.inst 177190498 # number of overall hits +system.cpu.dcache.overall_hits::total 177190498 # number of overall hits +system.cpu.dcache.overall_miss_latency::cpu.inst 485061958 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 485061958 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000041 # miss rate for overall accesses +system.cpu.dcache.overall_misses::cpu.inst 7289 # number of overall misses +system.cpu.dcache.overall_misses::total 7289 # number of overall misses +system.cpu.dcache.overall_mshr_hits::cpu.inst 2768 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2768 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 298702790 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 298702790 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses::cpu.inst 4521 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4521 # number of overall MSHR misses +system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 674 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2436 # Occupied blocks per task id +system.cpu.dcache.tags.avg_refs 39197.586375 # Average number of references to valid blocks. +system.cpu.dcache.tags.data_accesses 354443675 # Number of data accesses +system.cpu.dcache.tags.occ_blocks::cpu.inst 3089.554835 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.754286 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.754286 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3161 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.771729 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.replacements 1360 # number of replacements +system.cpu.dcache.tags.sampled_refs 4521 # Sample count of references to valid blocks. +system.cpu.dcache.tags.tag_accesses 354443675 # Number of tag accesses +system.cpu.dcache.tags.tagsinuse 3089.554835 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 177212288 # Total number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks::writebacks 1013 # number of writebacks +system.cpu.dcache.writebacks::total 1013 # number of writebacks +system.cpu.discardedOps 6932970 # Number of ops (including micro ops) which were discarded before commit +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.icache.ReadReq_accesses::cpu.inst 77471042 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 77471042 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17858.870336 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17858.870336 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15825.006083 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15825.006083 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::cpu.inst 77429612 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 77429612 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency::cpu.inst 739892998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 739892998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000535 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000535 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::cpu.inst 41430 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 41430 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 655630002 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 655630002 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000535 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 41430 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 41430 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses::cpu.inst 77471042 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 77471042 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17858.870336 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17858.870336 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15825.006083 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15825.006083 # average overall mshr miss latency +system.cpu.icache.demand_hits::cpu.inst 77429612 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 77429612 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency::cpu.inst 739892998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 739892998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::cpu.inst 0.000535 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000535 # miss rate for demand accesses +system.cpu.icache.demand_misses::cpu.inst 41430 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 41430 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 655630002 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 655630002 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000535 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses::cpu.inst 41430 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 41430 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses::cpu.inst 77471042 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 77471042 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17858.870336 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17858.870336 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15825.006083 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15825.006083 # average overall mshr miss latency +system.cpu.icache.overall_hits::cpu.inst 77429612 # number of overall hits +system.cpu.icache.overall_hits::total 77429612 # number of overall hits +system.cpu.icache.overall_miss_latency::cpu.inst 739892998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 739892998 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::cpu.inst 0.000535 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000535 # miss rate for overall accesses +system.cpu.icache.overall_misses::cpu.inst 41430 # number of overall misses +system.cpu.icache.overall_misses::total 41430 # number of overall misses +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 655630002 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 655630002 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000535 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses::cpu.inst 41430 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 41430 # number of overall MSHR misses +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 288 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1478 # Occupied blocks per task id +system.cpu.icache.tags.avg_refs 1868.971300 # Average number of references to valid blocks. +system.cpu.icache.tags.data_accesses 154983513 # Number of data accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1927.026996 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.940931 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.940931 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1941 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.947754 # Percentage of cache occupancy per task id +system.cpu.icache.tags.replacements 39488 # number of replacements +system.cpu.icache.tags.sampled_refs 41429 # Sample count of references to valid blocks. +system.cpu.icache.tags.tag_accesses 154983513 # Number of tag accesses +system.cpu.icache.tags.tagsinuse 1927.026996 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 77429612 # Total number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.idleCycles 4029946 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.ipc 0.600227 # IPC: instructions per cycle +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2860 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2860 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67967.563291 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67967.563291 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55399.173699 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55399.173699 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.inst 16 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 193299750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 193299750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.994406 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.994406 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 2844 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2844 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 157555250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 157555250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994406 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994406 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 2844 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 2844 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses::cpu.inst 43091 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 43091 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68852.642487 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68852.642487 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56391.699770 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56391.699770 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits::cpu.inst 38266 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 38266 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 332214000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 332214000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.111972 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.111972 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses::cpu.inst 4825 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4825 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 42 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 269721500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 269721500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.110998 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.110998 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4783 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4783 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses::writebacks 1013 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1013 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits::writebacks 1013 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1013 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses::cpu.inst 45951 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 45951 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68524.416482 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68524.416482 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56021.600892 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56021.600892 # average overall mshr miss latency +system.cpu.l2cache.demand_hits::cpu.inst 38282 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 38282 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency::cpu.inst 525513750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 525513750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.166895 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.166895 # miss rate for demand accesses +system.cpu.l2cache.demand_misses::cpu.inst 7669 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7669 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits::cpu.inst 42 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 42 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 427276750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 427276750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.165981 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.165981 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7627 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7627 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses::cpu.inst 45951 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 45951 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68524.416482 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68524.416482 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56021.600892 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56021.600892 # average overall mshr miss latency +system.cpu.l2cache.overall_hits::cpu.inst 38282 # number of overall hits +system.cpu.l2cache.overall_hits::total 38282 # number of overall hits +system.cpu.l2cache.overall_miss_latency::cpu.inst 525513750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 525513750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.166895 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.166895 # miss rate for overall accesses +system.cpu.l2cache.overall_misses::cpu.inst 7669 # number of overall misses +system.cpu.l2cache.overall_misses::total 7669 # number of overall misses +system.cpu.l2cache.overall_mshr_hits::cpu.inst 42 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 42 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 427276750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 427276750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.165981 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.165981 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7627 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7627 # number of overall MSHR misses +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1262 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4305 # Occupied blocks per task id +system.cpu.l2cache.tags.avg_refs 6.727368 # Average number of references to valid blocks. +system.cpu.l2cache.tags.data_accesses 384272 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 356.812936 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3883.048925 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.010889 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.118501 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.129390 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5700 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.173950 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.sampled_refs 5700 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.tag_accesses 384272 # Number of tag accesses +system.cpu.l2cache.tags.tagsinuse 4239.861860 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 38346 # Total number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.numCycles 454891032 # number of cpu cycles simulated +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.tickCycles 450861086 # Number of cycles that the CPU actually ticked +system.cpu.toL2Bus.data_through_bus 3005632 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 82859 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10055 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 92914 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 24495000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 62845998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 7514710 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.throughput 13214734 # Throughput (bytes/s) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2651456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 354176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 3005632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 43091 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 43090 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1013 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2860 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2860 # Transaction distribution +system.cpu.workload.num_syscalls 191 # Number of system calls +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.membus.data_through_bus 488128 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15254 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15254 # Packet count per connected master and slave (bytes) +system.membus.reqLayer0.occupancy 8910000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 71341750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.throughput 2146132 # Throughput (bytes/s) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 488128 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 488128 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 4783 # Transaction distribution +system.membus.trans_dist::ReadResp 4783 # Transaction distribution +system.membus.trans_dist::ReadExReq 2844 # Transaction distribution +system.membus.trans_dist::ReadExResp 2844 # Transaction distribution +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgGap 29821084.57 # Average gap between requests +system.physmem.avgMemAccLat 25580.41 # Average memory access latency per DRAM burst +system.physmem.avgQLat 6830.41 # Average queueing delay per DRAM burst +system.physmem.avgRdBW 2.15 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.15 # Average system read bandwidth in MiByte/s +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.bw_inst_read::cpu.inst 974721 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 974721 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 2146132 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2146132 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2146132 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2146132 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytesPerActivate::samples 1544 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 315.689119 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 184.950751 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.584238 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 593 38.41% 38.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 326 21.11% 59.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 172 11.14% 70.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 76 4.92% 75.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 71 4.60% 80.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 58 3.76% 83.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 38 2.46% 86.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 28 1.81% 88.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 182 11.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1544 # Bytes accessed per row activation +system.physmem.bytesReadDRAM 488128 # Total number of bytes read from DRAM +system.physmem.bytesReadSys 488128 # Total read bytes from the system interface side +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 488128 # Number of bytes read from this memory +system.physmem.bytes_read::total 488128 # Number of bytes read from this memory +system.physmem.memoryStateTime::IDLE 217468466000 # Time in different power states +system.physmem.memoryStateTime::REF 7594860000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 2381096500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.num_reads::cpu.inst 7627 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7627 # Number of read requests responded to by this memory +system.physmem.pageHitRate 79.70 # Row buffer hit rate, read and write combined +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.perBankRdBursts::0 637 # Per bank write bursts +system.physmem.perBankRdBursts::1 850 # Per bank write bursts +system.physmem.perBankRdBursts::2 633 # Per bank write bursts +system.physmem.perBankRdBursts::3 541 # Per bank write bursts +system.physmem.perBankRdBursts::4 470 # Per bank write bursts +system.physmem.perBankRdBursts::5 350 # Per bank write bursts +system.physmem.perBankRdBursts::6 175 # Per bank write bursts +system.physmem.perBankRdBursts::7 229 # Per bank write bursts +system.physmem.perBankRdBursts::8 210 # Per bank write bursts +system.physmem.perBankRdBursts::9 309 # Per bank write bursts +system.physmem.perBankRdBursts::10 346 # Per bank write bursts +system.physmem.perBankRdBursts::11 428 # Per bank write bursts +system.physmem.perBankRdBursts::12 552 # Per bank write bursts +system.physmem.perBankRdBursts::13 714 # Per bank write bursts +system.physmem.perBankRdBursts::14 639 # Per bank write bursts +system.physmem.perBankRdBursts::15 544 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.rdQLenPdf::0 6680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 887 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.readBursts 7627 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 7627 # Read request sizes (log2) +system.physmem.readReqs 7627 # Number of read requests accepted +system.physmem.readRowHitRate 79.70 # Row buffer hit rate for reads +system.physmem.readRowHits 6079 # Number of row buffer hits during reads +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.totBusLat 38135000 # Total ticks spent in databus transfers +system.physmem.totGap 227445412000 # Total gap between requests +system.physmem.totMemAccLat 195101750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 52095500 # Total ticks spent queuing +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.voltage_domain.voltage 1 # Voltage in Volts + +---------- End Simulation Statistics ---------- |