diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
| commit | 84f138ba96201431513eb2ae5f847389ac731aa2 (patch) | |
| tree | 3aee721699295c85e4e0c2d3d4a6bb27595bfabd /tests/long/se/30.eon | |
| parent | a288c94387b110112461ff5686fa727a43ddbe9c (diff) | |
| download | gem5-84f138ba96201431513eb2ae5f847389ac731aa2.tar.xz | |
stats: update references
Diffstat (limited to 'tests/long/se/30.eon')
28 files changed, 1463 insertions, 913 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini index 00495eb93..00cf13ff8 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini @@ -14,7 +14,9 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -24,9 +26,16 @@ mem_mode=timing mem_ranges= memories=system.physmem mmap_using_noreserve=false +multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null readfile= symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -55,6 +64,7 @@ decodeCycleInput=true decodeInputBufferSize=3 decodeInputWidth=2 decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -97,12 +107,17 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false system=system +threadPolicy=RoundRobin tracer=system.cpu.tracer workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side @@ -118,11 +133,18 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 +useIndirect=true [system.cpu.dcache] type=Cache @@ -130,13 +152,18 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -146,6 +173,7 @@ system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -154,8 +182,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=262144 @@ -553,13 +586,18 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -569,6 +607,7 @@ system=system tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=true cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -577,8 +616,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=131072 @@ -602,13 +646,18 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -618,6 +667,7 @@ system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] @@ -626,19 +676,31 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentXBar +children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 -snoop_filter=Null +snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false @@ -646,6 +708,13 @@ width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + [system.cpu.tracer] type=ExeTracer eventq_index=0 @@ -660,7 +729,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon +executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin kvmInSE=false @@ -692,9 +761,15 @@ transition_latency=100000000 [system.membus] type=CoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -738,6 +813,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -749,7 +825,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=0:134217727 ranks_per_channel=2 read_buffer_size=32 diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simerr index 3b53ebc6c..9c10deefc 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simerr +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simerr @@ -1,5 +1,6 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout index d34e3637b..33c16c36c 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout @@ -3,15 +3,15 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 14 2015 20:54:01 -gem5 started Sep 14 2015 21:15:11 -gem5 executing on ribera.cs.wisc.edu -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing +gem5 compiled Jul 19 2016 12:23:51 +gem5 started Jul 21 2016 14:09:28 +gem5 executing on e108600-lin, pid 4300 +command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/alpha/tru64/minor-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. -OO-style eon Time= 0.216667 -Exiting @ tick 225710988500 because target called exit() +OO-style eon Time= 0.233333 +Exiting @ tick 233525789500 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index 1c291ca67..b65c3962a 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.223533 # Number of seconds simulated -sim_ticks 223532962500 # Number of ticks simulated -final_tick 223532962500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.233526 # Number of seconds simulated +sim_ticks 233525789500 # Number of ticks simulated +final_tick 233525789500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 488740 # Simulator instruction rate (inst/s) -host_op_rate 488740 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 274038351 # Simulator tick rate (ticks/s) -host_mem_usage 302272 # Number of bytes of host memory used -host_seconds 815.70 # Real time elapsed on the host -sim_insts 398664665 # Number of instructions simulated -sim_ops 398664665 # Number of ops (including micro ops) simulated +host_inst_rate 279317 # Simulator instruction rate (inst/s) +host_op_rate 279317 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 163615265 # Simulator tick rate (ticks/s) +host_mem_usage 255720 # Number of bytes of host memory used +host_seconds 1427.29 # Real time elapsed on the host +sim_insts 398664651 # Number of instructions simulated +sim_ops 398664651 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 249088 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 249280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory -system.physmem.bytes_read::total 503680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 249088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 249088 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3892 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 503872 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 249280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 249280 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3895 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7870 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1114323 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1138946 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2253269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1114323 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1114323 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1114323 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1138946 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2253269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7870 # Number of read requests accepted +system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1067462 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1090209 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2157672 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1067462 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1067462 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1067462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1090209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2157672 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7873 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7870 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7873 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 503680 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 503872 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 503680 # Total read bytes from the system interface side +system.physmem.bytesReadSys 503872 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -46,9 +46,9 @@ system.physmem.perBankRdBursts::0 548 # Pe system.physmem.perBankRdBursts::1 675 # Per bank write bursts system.physmem.perBankRdBursts::2 473 # Per bank write bursts system.physmem.perBankRdBursts::3 633 # Per bank write bursts -system.physmem.perBankRdBursts::4 474 # Per bank write bursts +system.physmem.perBankRdBursts::4 475 # Per bank write bursts system.physmem.perBankRdBursts::5 477 # Per bank write bursts -system.physmem.perBankRdBursts::6 562 # Per bank write bursts +system.physmem.perBankRdBursts::6 563 # Per bank write bursts system.physmem.perBankRdBursts::7 560 # Per bank write bursts system.physmem.perBankRdBursts::8 471 # Per bank write bursts system.physmem.perBankRdBursts::9 437 # Per bank write bursts @@ -57,7 +57,7 @@ system.physmem.perBankRdBursts::11 323 # Pe system.physmem.perBankRdBursts::12 430 # Per bank write bursts system.physmem.perBankRdBursts::13 556 # Per bank write bursts system.physmem.perBankRdBursts::14 473 # Per bank write bursts -system.physmem.perBankRdBursts::15 424 # Per bank write bursts +system.physmem.perBankRdBursts::15 425 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 223532875000 # Total gap between requests +system.physmem.totGap 233525688500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7870 # Read request sizes (log2) +system.physmem.readPktSize::6 7873 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6816 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 971 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6857 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 948 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 68 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -188,28 +188,28 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 1541 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 325.149903 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 194.496255 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.966466 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 538 34.91% 34.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 340 22.06% 56.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 192 12.46% 69.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 106 6.88% 76.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 56 3.63% 79.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 49 3.18% 83.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 40 2.60% 85.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 36 2.34% 88.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 184 11.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 326.852693 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 195.480715 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 331.694198 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 535 34.72% 34.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 344 22.32% 57.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 186 12.07% 69.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 104 6.75% 75.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 66 4.28% 80.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 53 3.44% 83.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 28 1.82% 85.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 39 2.53% 87.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 186 12.07% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1541 # Bytes accessed per row activation -system.physmem.totQLat 51693000 # Total ticks spent queuing -system.physmem.totMemAccLat 199255500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 39350000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6568.36 # Average queueing delay per DRAM burst +system.physmem.totQLat 52273750 # Total ticks spent queuing +system.physmem.totMemAccLat 199892500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6639.62 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25318.36 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.25 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25389.62 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.25 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage @@ -217,75 +217,75 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6320 # Number of row buffer hits during reads +system.physmem.readRowHits 6330 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.30 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.40 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28403160.74 # Average gap between requests -system.physmem.pageHitRate 80.30 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6751080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3683625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 34125000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 29661588.78 # Average gap between requests +system.physmem.pageHitRate 80.40 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6804000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3712500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 34327800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14599740480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5792542920 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 129035577000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 149472420105 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.696853 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 214662823500 # Time in different power states -system.physmem_0.memoryStateTime::REF 7464080000 # Time in different power states +system.physmem_0.refreshEnergy 15252731520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5982776145 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 134867232750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 156147584715 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.653337 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 224361889750 # Time in different power states +system.physmem_0.memoryStateTime::REF 7797920000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1403552000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1365674000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4891320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2668875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 26933400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 4845960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2644125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 27058200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14599740480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5529545775 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 129266276250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 149430056100 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.507329 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 215046035000 # Time in different power states -system.physmem_1.memoryStateTime::REF 7464080000 # Time in different power states +system.physmem_1.refreshEnergy 15252731520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5743132470 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 135077446500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 156107858775 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.483223 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 224713608000 # Time in different power states +system.physmem_1.memoryStateTime::REF 7797920000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1017823750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1013955750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 45898041 # Number of BP lookups -system.cpu.branchPred.condPredicted 26691639 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 566044 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25194489 # Number of BTB lookups -system.cpu.branchPred.BTBHits 18810772 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 45912937 # Number of BP lookups +system.cpu.branchPred.condPredicted 26702744 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 565787 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 25186730 # Number of BTB lookups +system.cpu.branchPred.BTBHits 18811780 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 74.662249 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 8282157 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 322 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2248490 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2235007 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 13483 # Number of indirect misses. +system.cpu.branchPred.BTBHitPct 74.689251 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 8285572 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 2249877 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2235903 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 13974 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 111495 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 95357145 # DTB read hits -system.cpu.dtb.read_misses 114 # DTB read misses +system.cpu.dtb.read_hits 95338457 # DTB read hits +system.cpu.dtb.read_misses 116 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 95357259 # DTB read accesses -system.cpu.dtb.write_hits 73594596 # DTB write hits -system.cpu.dtb.write_misses 852 # DTB write misses +system.cpu.dtb.read_accesses 95338573 # DTB read accesses +system.cpu.dtb.write_hits 73578378 # DTB write hits +system.cpu.dtb.write_misses 849 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73595448 # DTB write accesses -system.cpu.dtb.data_hits 168951741 # DTB hits -system.cpu.dtb.data_misses 966 # DTB misses +system.cpu.dtb.write_accesses 73579227 # DTB write accesses +system.cpu.dtb.data_hits 168916835 # DTB hits +system.cpu.dtb.data_misses 965 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168952707 # DTB accesses -system.cpu.itb.fetch_hits 96790867 # ITB hits -system.cpu.itb.fetch_misses 1237 # ITB misses +system.cpu.dtb.data_accesses 168917800 # DTB accesses +system.cpu.itb.fetch_hits 96959231 # ITB hits +system.cpu.itb.fetch_misses 1239 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 96792104 # ITB accesses +system.cpu.itb.fetch_accesses 96960470 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,18 +299,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 223532962500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 447065925 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 467051579 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 398664665 # Number of instructions committed -system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2363843 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 398664651 # Number of instructions committed +system.cpu.committedOps 398664651 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2289293 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.121408 # CPI: cycles per instruction -system.cpu.ipc 0.891736 # IPC: instructions per cycle +system.cpu.cpi 1.171540 # CPI: cycles per instruction +system.cpu.ipc 0.853577 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction -system.cpu.op_class_0::IntAlu 141652567 35.53% 41.33% # Class of committed instruction +system.cpu.op_class_0::IntAlu 141652555 35.53% 41.33% # Class of committed instruction system.cpu.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction system.cpu.op_class_0::IntDiv 0 0.00% 41.86% # Class of committed instruction system.cpu.op_class_0::FloatAdd 35620060 8.93% 50.80% # Class of committed instruction @@ -339,81 +339,81 @@ system.cpu.op_class_0::SimdFloatMisc 0 0.00% 57.79% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 57.79% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 57.79% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::MemRead 94754511 23.77% 81.56% # Class of committed instruction -system.cpu.op_class_0::MemWrite 73520765 18.44% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 94754510 23.77% 81.56% # Class of committed instruction +system.cpu.op_class_0::MemWrite 73520764 18.44% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 398664665 # Class of committed instruction -system.cpu.tickCycles 443407678 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3658247 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states +system.cpu.op_class_0::total 398664651 # Class of committed instruction +system.cpu.tickCycles 455740556 # Number of cycles that the object actually ticked +system.cpu.idleCycles 11311023 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.617120 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 167826980 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3291.966637 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 167817023 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40294.593037 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40292.202401 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3291.617120 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803617 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803617 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3291.966637 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803703 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803703 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 3113 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 335672353 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 335672353 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 94312181 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94312181 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73514799 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73514799 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 167826980 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 167826980 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 167826980 # number of overall hits -system.cpu.dcache.overall_hits::total 167826980 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1183 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1183 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5931 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5931 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 7114 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7114 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7114 # number of overall misses -system.cpu.dcache.overall_misses::total 7114 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88520000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88520000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 429316500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 429316500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 517836500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 517836500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 517836500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 517836500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 94313364 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94313364 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 167834094 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 167834094 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 167834094 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 167834094 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000013 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000013 # miss rate for ReadReq accesses +system.cpu.dcache.tags.tag_accesses 335652191 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 335652191 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 94302223 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94302223 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73514800 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73514800 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 167817023 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 167817023 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 167817023 # number of overall hits +system.cpu.dcache.overall_hits::total 167817023 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1061 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1061 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5929 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5929 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 6990 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6990 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6990 # number of overall misses +system.cpu.dcache.overall_misses::total 6990 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 77930500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 77930500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 429190000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 429190000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 507120500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 507120500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 507120500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 507120500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 94303284 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94303284 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 167824013 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 167824013 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 167824013 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 167824013 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000011 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000011 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000081 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74826.711750 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 74826.711750 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72385.179565 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72385.179565 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72791.186393 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72791.186393 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72791.186393 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72791.186393 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73450.047125 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73450.047125 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72388.261090 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 72388.261090 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72549.427754 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72549.427754 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72549.427754 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72549.427754 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,14 +422,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 654 # number of writebacks system.cpu.dcache.writebacks::total 654 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 214 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 214 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2735 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2735 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2949 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2949 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2949 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2949 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 92 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2733 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2733 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2825 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2825 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2825 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2825 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses @@ -438,14 +438,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4165 system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 71272000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 71272000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 239421000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 239421000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 310693000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 310693000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 310693000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 310693000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70280500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 70280500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 239912500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 239912500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 310193000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 310193000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 310193000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 310193000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -454,128 +454,128 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73552.115583 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73552.115583 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74912.703379 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74912.703379 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74596.158463 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74596.158463 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74596.158463 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74596.158463 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 3190 # number of replacements -system.cpu.icache.tags.tagsinuse 1919.630000 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 96785699 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5168 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18727.882933 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72528.895769 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72528.895769 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75066.489362 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75066.489362 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74476.110444 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74476.110444 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74476.110444 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74476.110444 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 3193 # number of replacements +system.cpu.icache.tags.tagsinuse 1919.750364 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 96954060 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5171 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18749.576484 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1919.630000 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.937319 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.937319 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1919.750364 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.937378 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.937378 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1287 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 193586902 # Number of tag accesses -system.cpu.icache.tags.data_accesses 193586902 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 96785699 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 96785699 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 96785699 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 96785699 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 96785699 # number of overall hits -system.cpu.icache.overall_hits::total 96785699 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5168 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5168 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5168 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5168 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5168 # number of overall misses -system.cpu.icache.overall_misses::total 5168 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 316704500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 316704500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 316704500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 316704500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 316704500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 316704500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 96790867 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 96790867 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 96790867 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 96790867 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 96790867 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 96790867 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 193923633 # Number of tag accesses +system.cpu.icache.tags.data_accesses 193923633 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 96954060 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 96954060 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 96954060 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 96954060 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 96954060 # number of overall hits +system.cpu.icache.overall_hits::total 96954060 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5171 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5171 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5171 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5171 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5171 # number of overall misses +system.cpu.icache.overall_misses::total 5171 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 318040500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 318040500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 318040500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 318040500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 318040500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 318040500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 96959231 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 96959231 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 96959231 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 96959231 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 96959231 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 96959231 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000053 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000053 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000053 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61281.830495 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61281.830495 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61281.830495 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61281.830495 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61281.830495 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61281.830495 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61504.641269 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61504.641269 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61504.641269 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61504.641269 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61504.641269 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61504.641269 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 3190 # number of writebacks -system.cpu.icache.writebacks::total 3190 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5168 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 5168 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 5168 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 5168 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 5168 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5168 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 311536500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 311536500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 311536500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 311536500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 311536500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 311536500 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 3193 # number of writebacks +system.cpu.icache.writebacks::total 3193 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5171 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 5171 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 5171 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 5171 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 5171 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 5171 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312869500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 312869500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312869500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 312869500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312869500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 312869500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60281.830495 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60281.830495 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60281.830495 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60281.830495 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60281.830495 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60281.830495 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60504.641269 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60504.641269 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60504.641269 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60504.641269 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60504.641269 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60504.641269 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4421.902302 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4798 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5270 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.910436 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 4425.384656 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4801 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5273 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.910487 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 372.081904 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3407.854115 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 641.966284 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011355 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.103999 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.019591 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.134946 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5270 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 372.164909 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.179805 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 642.039942 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011358 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104101 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.019594 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.135052 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5273 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 613 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4439 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160828 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 114820 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 114820 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4442 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160919 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 114871 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 114871 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 654 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 654 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 3190 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 3190 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::writebacks 3193 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 3193 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 61 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 61 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1276 # number of ReadCleanReq hits @@ -590,68 +590,68 @@ system.cpu.l2cache.overall_hits::cpu.data 187 # n system.cpu.l2cache.overall_hits::total 1463 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 3137 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 3137 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3892 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3892 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3895 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3895 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 841 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 841 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3892 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 3895 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 3978 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7870 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3892 # number of overall misses +system.cpu.l2cache.demand_misses::total 7873 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3895 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3978 # number of overall misses -system.cpu.l2cache.overall_misses::total 7870 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 234104000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 234104000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 290385500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 290385500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 68345000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 68345000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 290385500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 302449000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 592834500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 290385500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 302449000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 592834500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::total 7873 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 234589500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 234589500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 291713500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 291713500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 67354500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 67354500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 291713500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 301944000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 593657500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 291713500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 301944000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 593657500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 654 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 654 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 3190 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 3190 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 3193 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 3193 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 3198 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 3198 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5168 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 5168 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5171 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 5171 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 967 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 967 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 5168 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 5171 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4165 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9333 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 5168 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9336 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 5171 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4165 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9333 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9336 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.980926 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.980926 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.753096 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.753096 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.753239 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.753239 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.869700 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.869700 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.753096 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.753239 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.955102 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.843244 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.753096 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.843295 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.753239 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955102 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.843244 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74626.713420 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74626.713420 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74610.868448 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74610.868448 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81266.349584 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81266.349584 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74610.868448 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76030.417295 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75328.398983 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74610.868448 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76030.417295 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75328.398983 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.843295 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74781.479120 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74781.479120 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74894.351733 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74894.351733 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80088.585018 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80088.585018 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74894.351733 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75903.469080 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75404.229646 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74894.351733 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75903.469080 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75404.229646 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -660,114 +660,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3137 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 3137 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3892 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3892 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3895 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3895 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 841 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 841 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3892 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3895 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 3978 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7870 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3892 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7873 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3895 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3978 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7870 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 202734000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 202734000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 251465500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 251465500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59935000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59935000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 251465500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 262669000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 514134500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 251465500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 262669000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 514134500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 7873 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 203219500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 203219500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 252763500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 252763500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 58944500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 58944500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 252763500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 262164000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 514927500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 252763500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 262164000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 514927500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.753096 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.753096 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.753239 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.753239 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.869700 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.753096 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.753239 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.843244 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.753096 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.843295 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.753239 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.843244 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64626.713420 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64626.713420 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64610.868448 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64610.868448 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71266.349584 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71266.349584 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64610.868448 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66030.417295 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65328.398983 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64610.868448 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66030.417295 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.398983 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 13294 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 3961 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.843295 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64781.479120 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64781.479120 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64894.351733 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64894.351733 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70088.585018 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70088.585018 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64894.351733 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65903.469080 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65404.229646 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64894.351733 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65903.469080 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65404.229646 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 13300 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3964 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 6135 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 6138 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 654 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 3190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 3193 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 117 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 5168 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 5171 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 967 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13526 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13535 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9101 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22627 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 534912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22636 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 535296 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 843328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 843712 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 9333 # Request fanout histogram +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 9336 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 9333 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 9336 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 9333 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10491000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 9336 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10497000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7752000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7756500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6247999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4733 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 4736 # Transaction distribution system.membus.trans_dist::ReadExReq 3137 # Transaction distribution system.membus.trans_dist::ReadExResp 3137 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4733 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15740 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15740 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 503680 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 503680 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 4736 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15746 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15746 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 503872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 503872 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7870 # Request fanout histogram +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 7873 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7870 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7873 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7870 # Request fanout histogram -system.membus.reqLayer0.occupancy 9176500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7873 # Request fanout histogram +system.membus.reqLayer0.occupancy 9219000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 41781750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 41801750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini index fda724fd7..e7c466732 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -14,7 +14,9 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -24,9 +26,16 @@ mem_mode=timing mem_ranges= memories=system.physmem mmap_using_noreserve=false +multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null readfile= symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -68,6 +77,7 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 +default_p_state=UNDEFINED dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -104,6 +114,10 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -143,11 +157,18 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 +useIndirect=true [system.cpu.dcache] type=Cache @@ -155,13 +176,18 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -171,6 +197,7 @@ system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -179,8 +206,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=262144 @@ -502,13 +534,18 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -518,6 +555,7 @@ system=system tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=true cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -526,8 +564,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=131072 @@ -551,13 +594,18 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -567,6 +615,7 @@ system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] @@ -575,19 +624,31 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentXBar +children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 -snoop_filter=Null +snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false @@ -595,6 +656,13 @@ width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + [system.cpu.tracer] type=ExeTracer eventq_index=0 @@ -609,7 +677,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon +executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin kvmInSE=false @@ -641,9 +709,15 @@ transition_latency=100000000 [system.membus] type=CoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -687,6 +761,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -698,7 +773,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=0:134217727 ranks_per_channel=2 read_buffer_size=32 diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr index 3b53ebc6c..9c10deefc 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr @@ -1,5 +1,6 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout index d6aa6688c..02658fe82 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout @@ -3,15 +3,15 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 14 2015 20:54:01 -gem5 started Sep 14 2015 20:55:00 -gem5 executing on ribera.cs.wisc.edu -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing +gem5 compiled Jul 19 2016 12:23:51 +gem5 started Jul 21 2016 14:09:28 +gem5 executing on e108600-lin, pid 4299 +command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. -OO-style eon Time= 0.066667 -Exiting @ tick 67874346000 because target called exit() +OO-style eon Time= 0.050000 +Exiting @ tick 64188759000 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 68a991d52..81cd1b880 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.064189 # Nu sim_ticks 64188759000 # Number of ticks simulated final_tick 64188759000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 392159 # Simulator instruction rate (inst/s) -host_op_rate 392159 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67023124 # Simulator tick rate (ticks/s) -host_mem_usage 303292 # Number of bytes of host memory used -host_seconds 957.71 # Real time elapsed on the host +host_inst_rate 260398 # Simulator instruction rate (inst/s) +host_op_rate 260398 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44504184 # Simulator tick rate (ticks/s) +host_mem_usage 257256 # Number of bytes of host memory used +host_seconds 1442.31 # Real time elapsed on the host sim_insts 375574794 # Number of instructions simulated sim_ops 375574794 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -985,6 +985,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309184 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 705472 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) system.cpu.toL2Bus.snoop_fanout::samples 8236 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram @@ -1012,6 +1013,7 @@ system.membus.pkt_count::total 14880 # Pa system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476160 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 476160 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 7440 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini index 427c7c717..7b7341967 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -14,7 +14,9 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -24,9 +26,16 @@ mem_mode=timing mem_ranges= memories=system.physmem mmap_using_noreserve=false +multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null readfile= symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -51,6 +60,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -66,6 +76,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -83,13 +97,18 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -99,6 +118,7 @@ system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -107,8 +127,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=262144 @@ -123,13 +148,18 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -139,6 +169,7 @@ system=system tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=true cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -147,8 +178,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=131072 @@ -172,13 +208,18 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -188,6 +229,7 @@ system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] @@ -196,19 +238,31 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentXBar +children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 -snoop_filter=Null +snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false @@ -216,6 +270,13 @@ width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + [system.cpu.tracer] type=ExeTracer eventq_index=0 @@ -230,7 +291,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon +executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin kvmInSE=false @@ -262,9 +323,15 @@ transition_latency=100000000 [system.membus] type=CoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -279,11 +346,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:134217727 port=system.membus.master[0] diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr index 664365742..870cfd899 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr @@ -1,4 +1,5 @@ warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout index ab67caf1c..1c6cb75e4 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout @@ -1,14 +1,17 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 16:27:55 -gem5 started Jan 22 2014 17:48:27 -gem5 executing on u200540-lin -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing +gem5 compiled Jul 19 2016 12:23:51 +gem5 started Jul 21 2016 14:09:28 +gem5 executing on e108600-lin, pid 4302 +command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/alpha/tru64/simple-timing + Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.566667 -Exiting @ tick 567335093000 because target called exit() +Exiting @ tick 567385356500 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index d0130300a..9532c68be 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.567385 # Nu sim_ticks 567385356500 # Number of ticks simulated final_tick 567385356500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1687815 # Simulator instruction rate (inst/s) -host_op_rate 1687815 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2402123351 # Simulator tick rate (ticks/s) -host_mem_usage 300208 # Number of bytes of host memory used -host_seconds 236.20 # Real time elapsed on the host +host_inst_rate 1154582 # Simulator instruction rate (inst/s) +host_op_rate 1154582 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1643217424 # Simulator tick rate (ticks/s) +host_mem_usage 254440 # Number of bytes of host memory used +host_seconds 345.29 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -500,6 +500,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 655552 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) system.cpu.toL2Bus.snoop_fanout::samples 7825 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram @@ -527,6 +528,7 @@ system.membus.pkt_count::total 14348 # Pa system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 459136 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 7174 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini index c0afc2364..76d7daa42 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini @@ -14,7 +14,9 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -24,9 +26,16 @@ mem_mode=timing mem_ranges= memories=system.physmem mmap_using_noreserve=false +multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null readfile= symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -55,6 +64,7 @@ decodeCycleInput=true decodeInputBufferSize=3 decodeInputWidth=2 decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -99,12 +109,17 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false system=system +threadPolicy=RoundRobin tracer=system.cpu.tracer workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side @@ -120,11 +135,18 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 +useIndirect=true [system.cpu.dcache] type=Cache @@ -132,13 +154,18 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -148,6 +175,7 @@ system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -156,8 +184,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=262144 @@ -180,9 +213,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker [system.cpu.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.dtb] @@ -196,9 +234,14 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[3] @@ -591,13 +634,18 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -607,6 +655,7 @@ system=system tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=true cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -615,8 +664,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=131072 @@ -626,6 +680,7 @@ eventq_index=0 [system.cpu.isa] type=ArmISA +decoderFlavour=Generic eventq_index=0 fpsid=1090793632 id_aa64afr0_el1=0 @@ -673,9 +728,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker [system.cpu.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.itb] @@ -689,9 +749,14 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[2] @@ -701,13 +766,18 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -717,6 +787,7 @@ system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] @@ -725,19 +796,31 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentXBar +children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 -snoop_filter=Null +snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false @@ -745,6 +828,13 @@ width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + [system.cpu.tracer] type=ExeTracer eventq_index=0 @@ -759,7 +849,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon +executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/eon gid=100 input=cin kvmInSE=false @@ -791,9 +881,15 @@ transition_latency=100000000 [system.membus] type=CoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -837,6 +933,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -848,7 +945,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=0:134217727 ranks_per_channel=2 read_buffer_size=32 diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simerr index 62f25930d..497b78d8e 100755 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/simerr +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simerr @@ -1,5 +1,6 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout index 8d785cb1f..ab196f487 100755 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 14 2015 23:29:19 -gem5 started Sep 15 2015 01:25:17 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:38:22 +gem5 executing on e108600-lin, pid 23074 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -15,5 +15,5 @@ Eon, Version 1.1 info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. -OO-style eon Time= 0.210000 -Exiting @ tick 215505832500 because target called exit() +OO-style eon Time= 0.220000 +Exiting @ tick 225030243000 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 521f1135c..0b49d498f 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.211715 # Number of seconds simulated -sim_ticks 211714953000 # Number of ticks simulated -final_tick 211714953000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.225030 # Number of seconds simulated +sim_ticks 225030243000 # Number of ticks simulated +final_tick 225030243000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 271910 # Simulator instruction rate (inst/s) -host_op_rate 326458 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 210840466 # Simulator tick rate (ticks/s) -host_mem_usage 322892 # Number of bytes of host memory used -host_seconds 1004.15 # Real time elapsed on the host -sim_insts 273037857 # Number of instructions simulated -sim_ops 327812214 # Number of ops (including micro ops) simulated +host_inst_rate 131394 # Simulator instruction rate (inst/s) +host_op_rate 157754 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 108291606 # Simulator tick rate (ticks/s) +host_mem_usage 275248 # Number of bytes of host memory used +host_seconds 2078.00 # Real time elapsed on the host +sim_insts 273037855 # Number of instructions simulated +sim_ops 327812212 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 219136 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 266432 # Number of bytes read from this memory -system.physmem.bytes_read::total 485504 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3423 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 485568 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219136 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4163 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7586 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1034750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1258447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2293197 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1034750 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1034750 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1034750 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1258447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2293197 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7586 # Number of read requests accepted +system.physmem.num_reads::total 7587 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 973807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1183983 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2157790 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 973807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 973807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 973807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1183983 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2157790 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7587 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7586 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7587 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 485504 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 485568 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 485504 # Total read bytes from the system interface side +system.physmem.bytesReadSys 485568 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -51,13 +51,13 @@ system.physmem.perBankRdBursts::5 349 # Pe system.physmem.perBankRdBursts::6 171 # Per bank write bursts system.physmem.perBankRdBursts::7 228 # Per bank write bursts system.physmem.perBankRdBursts::8 208 # Per bank write bursts -system.physmem.perBankRdBursts::9 310 # Per bank write bursts +system.physmem.perBankRdBursts::9 309 # Per bank write bursts system.physmem.perBankRdBursts::10 343 # Per bank write bursts system.physmem.perBankRdBursts::11 428 # Per bank write bursts system.physmem.perBankRdBursts::12 553 # Per bank write bursts system.physmem.perBankRdBursts::13 705 # Per bank write bursts -system.physmem.perBankRdBursts::14 638 # Per bank write bursts -system.physmem.perBankRdBursts::15 542 # Per bank write bursts +system.physmem.perBankRdBursts::14 639 # Per bank write bursts +system.physmem.perBankRdBursts::15 543 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 211714708500 # Total gap between requests +system.physmem.totGap 225029996000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7586 # Read request sizes (log2) +system.physmem.readPktSize::6 7587 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6629 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6713 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -187,86 +187,86 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1530 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 316.067974 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 186.296863 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.878934 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 560 36.60% 36.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 363 23.73% 60.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 160 10.46% 70.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 74 4.84% 75.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 70 4.58% 80.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 59 3.86% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 34 2.22% 86.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 28 1.83% 88.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 182 11.90% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1530 # Bytes accessed per row activation -system.physmem.totQLat 52630500 # Total ticks spent queuing -system.physmem.totMemAccLat 194868000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37930000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6937.85 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1511 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 320.084712 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.611752 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 331.049486 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 552 36.53% 36.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 328 21.71% 58.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 178 11.78% 70.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 86 5.69% 75.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 72 4.77% 80.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 49 3.24% 83.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 32 2.12% 85.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 31 2.05% 87.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 183 12.11% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1511 # Bytes accessed per row activation +system.physmem.totQLat 51456750 # Total ticks spent queuing +system.physmem.totMemAccLat 193713000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37935000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6782.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25687.85 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25532.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6048 # Number of row buffer hits during reads +system.physmem.readRowHits 6068 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.73 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.98 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 27908609.08 # Average gap between requests -system.physmem.pageHitRate 79.73 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5080320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2772000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 29659944.11 # Average gap between requests +system.physmem.pageHitRate 79.98 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5012280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2734875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 29881800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 13827746400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5529396150 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 122174691000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 141569591070 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.700877 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 203247000500 # Time in different power states -system.physmem_0.memoryStateTime::REF 7069400000 # Time in different power states +system.physmem_0.refreshEnergy 14697384000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5831471925 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 129898404750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 150464889630 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.664832 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 216095628500 # Time in different power states +system.physmem_0.memoryStateTime::REF 7514000000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1392729000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1413270250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6463800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3526875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 28992600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 6380640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3481500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 29000400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 13827746400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5726317185 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 122001953250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 141595000110 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.820896 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 202960400000 # Time in different power states -system.physmem_1.memoryStateTime::REF 7069400000 # Time in different power states +system.physmem_1.refreshEnergy 14697384000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6004643625 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 129746499750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 150487389915 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.764823 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 215845139250 # Time in different power states +system.physmem_1.memoryStateTime::REF 7514000000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1682763000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1668675750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 32413931 # Number of BP lookups -system.cpu.branchPred.condPredicted 16919661 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 738142 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17496692 # Number of BTB lookups -system.cpu.branchPred.BTBHits 12856502 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 32430290 # Number of BP lookups +system.cpu.branchPred.condPredicted 16924100 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 738493 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17494980 # Number of BTB lookups +system.cpu.branchPred.BTBHits 12858502 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 73.479615 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6512761 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2303892 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2264485 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 39407 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 128263 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 73.498238 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6523127 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 2303930 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2264813 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 39117 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 128237 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,18 +387,18 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 211714953000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 423429906 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 450060486 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 273037857 # Number of instructions committed -system.cpu.committedOps 327812214 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2127081 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 273037855 # Number of instructions committed +system.cpu.committedOps 327812212 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2063972 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.550810 # CPI: cycles per instruction -system.cpu.ipc 0.644824 # IPC: instructions per cycle +system.cpu.cpi 1.648345 # CPI: cycles per instruction +system.cpu.ipc 0.606669 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.op_class_0::IntAlu 104312544 31.82% 31.82% # Class of committed instruction +system.cpu.op_class_0::IntAlu 104312542 31.82% 31.82% # Class of committed instruction system.cpu.op_class_0::IntMult 2145905 0.65% 32.48% # Class of committed instruction system.cpu.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction system.cpu.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction @@ -431,93 +431,93 @@ system.cpu.op_class_0::MemRead 85732248 26.15% 74.87% # Cl system.cpu.op_class_0::MemWrite 82375599 25.13% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 327812214 # Class of committed instruction -system.cpu.tickCycles 420106568 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3323338 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states +system.cpu.op_class_0::total 327812212 # Class of committed instruction +system.cpu.tickCycles 434886518 # Number of cycles that the object actually ticked +system.cpu.idleCycles 15173968 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1355 # number of replacements -system.cpu.dcache.tags.tagsinuse 3085.570959 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168654881 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3086.261687 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168654217 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4512 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37379.184619 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37379.037456 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3085.570959 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.753313 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.753313 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3086.261687 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.753482 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.753482 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 337328856 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 337328856 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 86522107 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86522107 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82047451 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047451 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 63533 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 63533 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 337326818 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337326818 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 86521433 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86521433 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82047456 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047456 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 63538 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 63538 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168569558 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168569558 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168633091 # number of overall hits -system.cpu.dcache.overall_hits::total 168633091 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2060 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2060 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5226 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5226 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 168568889 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168568889 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168632427 # number of overall hits +system.cpu.dcache.overall_hits::total 168632427 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1710 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1710 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5221 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5221 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 7286 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7286 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7291 # number of overall misses -system.cpu.dcache.overall_misses::total 7291 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 136635000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 136635000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 394688000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 394688000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 531323000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 531323000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 531323000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 531323000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86524167 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86524167 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 6931 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6931 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6936 # number of overall misses +system.cpu.dcache.overall_misses::total 6936 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 114932500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 114932500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 393586500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 393586500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 508519000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 508519000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 508519000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 508519000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86523143 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86523143 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 63538 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 63538 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 63543 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 63543 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168576844 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168576844 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168640382 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168640382 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 168575820 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168575820 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168639363 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168639363 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000079 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.000079 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66327.669903 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66327.669903 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75523.918867 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75523.918867 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72923.826517 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72923.826517 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72873.817035 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72873.817035 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.000041 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000041 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000041 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000041 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67211.988304 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67211.988304 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75385.271021 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75385.271021 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73368.777954 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73368.777954 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73315.888120 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73315.888120 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -526,14 +526,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks system.cpu.dcache.writebacks::total 1010 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 421 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 421 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2356 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2356 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2777 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2777 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2777 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2777 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 71 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2351 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2351 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2422 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2422 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2422 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2422 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1639 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1639 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses @@ -544,16 +544,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4509 system.cpu.dcache.demand_mshr_misses::total 4509 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4512 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4512 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109916500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 109916500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219842000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 219842000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 481000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 481000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329758500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 329758500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 330239500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 330239500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 110662500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 110662500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219478500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 219478500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 238000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 238000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 330141000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 330141000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 330379000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 330379000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -564,208 +564,208 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67063.148261 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67063.148261 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76600 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76600 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 160333.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 160333.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73133.399867 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73133.399867 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73191.378546 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73191.378546 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 38168 # number of replacements -system.cpu.icache.tags.tagsinuse 1923.744161 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 69641436 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 40104 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1736.520946 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67518.303844 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67518.303844 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76473.344948 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76473.344948 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73218.230206 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73218.230206 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73222.296099 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73222.296099 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 38188 # number of replacements +system.cpu.icache.tags.tagsinuse 1925.010528 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 69819783 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 40125 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1740.056897 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1923.744161 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939328 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939328 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 276 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1483 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 139403186 # Number of tag accesses -system.cpu.icache.tags.data_accesses 139403186 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 69641436 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 69641436 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 69641436 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 69641436 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 69641436 # number of overall hits -system.cpu.icache.overall_hits::total 69641436 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 40105 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 40105 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 40105 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 40105 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 40105 # number of overall misses -system.cpu.icache.overall_misses::total 40105 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 757528000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 757528000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 757528000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 757528000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 757528000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 757528000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 69681541 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 69681541 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 69681541 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 69681541 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 69681541 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 69681541 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000576 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000576 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000576 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000576 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000576 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000576 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18888.617379 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18888.617379 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18888.617379 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18888.617379 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18888.617379 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18888.617379 # average overall miss latency +system.cpu.icache.tags.occ_blocks::cpu.inst 1925.010528 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939947 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939947 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 277 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 139759943 # Number of tag accesses +system.cpu.icache.tags.data_accesses 139759943 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 69819783 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 69819783 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 69819783 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 69819783 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 69819783 # number of overall hits +system.cpu.icache.overall_hits::total 69819783 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 40126 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 40126 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 40126 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 40126 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 40126 # number of overall misses +system.cpu.icache.overall_misses::total 40126 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 756662500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 756662500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 756662500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 756662500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 756662500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 756662500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 69859909 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 69859909 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 69859909 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 69859909 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 69859909 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 69859909 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000574 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000574 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000574 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000574 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000574 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000574 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18857.162438 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18857.162438 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18857.162438 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18857.162438 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18857.162438 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18857.162438 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 38168 # number of writebacks -system.cpu.icache.writebacks::total 38168 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 40105 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 40105 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 40105 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 40105 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 40105 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 40105 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 717424000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 717424000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 717424000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 717424000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 717424000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 717424000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000576 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000576 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000576 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000576 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000576 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000576 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17888.642314 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17888.642314 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17888.642314 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17888.642314 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17888.642314 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17888.642314 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states +system.cpu.icache.writebacks::writebacks 38188 # number of writebacks +system.cpu.icache.writebacks::total 38188 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 40126 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 40126 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 40126 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 40126 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 40126 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 40126 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 716537500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 716537500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 716537500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 716537500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 716537500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 716537500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000574 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000574 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000574 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17857.187360 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17857.187360 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17857.187360 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17857.187360 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17857.187360 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17857.187360 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4199.701287 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 60529 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5648 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.716891 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 4201.230054 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 60569 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5649 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.722075 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 353.800339 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.579629 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 678.321319 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.010797 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096667 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.020701 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.128165 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5648 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1251 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 354.127692 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3168.434045 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 678.668317 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.010807 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096693 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.020711 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.128211 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5649 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1257 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4262 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172363 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 561366 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 561366 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172394 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 561687 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 561687 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 1010 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 1010 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 23251 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 23251 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::writebacks 23270 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 23270 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36680 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 36680 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 291 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 291 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 36680 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 307 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 36987 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 36680 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 307 # number of overall hits -system.cpu.l2cache.overall_hits::total 36987 # number of overall hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36700 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 36700 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 292 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 292 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 36700 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 308 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 37008 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 36700 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 308 # number of overall hits +system.cpu.l2cache.overall_hits::total 37008 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 2854 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 2854 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3425 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3425 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1351 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 1351 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3425 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 4205 # number of demand (read+write) misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3426 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3426 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1350 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 1350 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3426 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 4204 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 7630 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3425 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 4205 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 3426 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses system.cpu.l2cache.overall_misses::total 7630 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 215334500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 215334500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 257203500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 257203500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 104684500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 104684500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 257203500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 320019000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 577222500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 257203500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 320019000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 577222500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 214976500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 214976500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 256075000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 256075000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 105174500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 105174500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 256075000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 320151000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 576226000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 256075000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 320151000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 576226000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 1010 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 1010 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 23251 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 23251 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 23270 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 23270 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 2870 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 2870 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 40105 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 40105 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 40126 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 40126 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1642 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 1642 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 40105 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 40126 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4512 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 44617 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 40105 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 44638 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 40126 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4512 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 44617 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 44638 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994425 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.994425 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.085401 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.085401 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.822777 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.822777 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.085401 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.931959 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.171011 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085401 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.931959 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.171011 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75450.070077 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75450.070077 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75095.912409 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75095.912409 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77486.676536 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77486.676536 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75095.912409 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76104.399524 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75651.703801 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75095.912409 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76104.399524 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75651.703801 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.085381 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.085381 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.822168 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.822168 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.085381 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.931738 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.170931 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085381 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.931738 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.170931 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75324.632095 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75324.632095 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74744.600117 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74744.600117 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77907.037037 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77907.037037 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74744.600117 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76153.901047 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75521.100917 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74744.600117 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76153.901047 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75521.100917 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -774,124 +774,126 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 42 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 42 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 41 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 41 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 42 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 44 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 41 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 43 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 42 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 44 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 41 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 43 # number of overall MSHR hits system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2854 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 2854 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3423 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3423 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3424 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3424 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1309 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1309 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3423 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3424 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 4163 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7586 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3423 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7587 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3424 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4163 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7586 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 186794500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 186794500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 222839000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 222839000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 88850500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 88850500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 222839000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 275645000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 498484000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 222839000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 275645000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 498484000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 7587 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 186436500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 186436500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 221700500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 221700500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 89390500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 89390500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 221700500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 275827000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 497527500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 221700500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 275827000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 497527500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085351 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.085351 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.085331 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.797199 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.797199 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.085351 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.170025 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085351 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.169967 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.170025 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65450.070077 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65450.070077 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65100.496640 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65100.496640 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67876.623377 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67876.623377 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65100.496640 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66213.067499 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65711.046665 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65100.496640 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66213.067499 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65711.046665 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 84140 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 39625 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15034 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.169967 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65324.632095 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65324.632095 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64748.977804 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64748.977804 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68289.152024 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68289.152024 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64748.977804 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66256.785972 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65576.314749 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64748.977804 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66256.785972 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65576.314749 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 84181 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 39645 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15035 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 41746 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 41767 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 38168 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 38188 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 40105 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 40126 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1642 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118377 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118439 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10379 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 128756 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5009408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 128818 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5012032 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 5362816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 5365440 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 44617 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.339243 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.473458 # Request fanout histogram +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 44638 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.339106 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.473411 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 29481 66.08% 66.08% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 15136 33.92% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 29501 66.09% 66.09% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 15137 33.91% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 44617 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 81248000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 44638 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 81288500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 60156998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 60188498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6789457 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4732 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 4733 # Transaction distribution system.membus.trans_dist::ReadExReq 2854 # Transaction distribution system.membus.trans_dist::ReadExResp 2854 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4732 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15172 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15172 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 485504 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 4733 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15174 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15174 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 485568 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7586 # Request fanout histogram +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 7587 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7586 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7587 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7586 # Request fanout histogram -system.membus.reqLayer0.occupancy 8883500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7587 # Request fanout histogram +system.membus.reqLayer0.occupancy 9083500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 40266000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40284000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index a48b86389..d73a74668 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -27,6 +28,10 @@ memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null readfile= symbolfile= thermal_components= @@ -72,6 +77,7 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=2 decodeWidth=3 +default_p_state=UNDEFINED dispatchWidth=6 do_checkpoint_insts=true do_quiesce=true @@ -110,6 +116,10 @@ numPhysIntRegs=128 numROBEntries=40 numRobs=1 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -166,12 +176,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -190,8 +205,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -214,9 +234,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker [system.cpu.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.dtb] @@ -230,9 +255,14 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[3] @@ -508,12 +538,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=1 @@ -532,8 +567,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -591,9 +631,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker [system.cpu.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.itb] @@ -607,9 +652,14 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[2] @@ -620,12 +670,17 @@ addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=true prefetcher=system.cpu.l2cache.prefetcher response_latency=12 @@ -643,6 +698,7 @@ mem_side=system.membus.slave[1] type=StridePrefetcher cache_snoop=false clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED degree=8 eventq_index=0 latency=1 @@ -653,6 +709,10 @@ on_inst=true on_miss=false on_read=true on_write=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null queue_filter=true queue_size=32 queue_squash=true @@ -669,8 +729,13 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=12 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1048576 @@ -678,10 +743,15 @@ size=1048576 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -712,7 +782,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/cpu2000/binaries/arm/linux/eon +executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/eon gid=100 input=cin kvmInSE=false @@ -744,10 +814,15 @@ transition_latency=100000000 [system.membus] type=CoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -791,6 +866,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -802,7 +878,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=0:134217727 ranks_per_channel=2 read_buffer_size=32 diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr index 613c6a6b7..3415c9346 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr @@ -1,5 +1,6 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index 572268607..7e2bba88d 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2016 19:53:43 -gem5 started Mar 15 2016 21:05:26 -gem5 executing on dinar2c11, pid 11410 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 15:06:52 +gem5 executing on e108600-lin, pid 24264 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index f64410488..cc1788f11 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.111754 # Nu sim_ticks 111753553500 # Number of ticks simulated final_tick 111753553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 201687 # Simulator instruction rate (inst/s) -host_op_rate 242148 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 82550264 # Simulator tick rate (ticks/s) -host_mem_usage 334820 # Number of bytes of host memory used -host_seconds 1353.76 # Real time elapsed on the host +host_inst_rate 162111 # Simulator instruction rate (inst/s) +host_op_rate 194632 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66351635 # Simulator tick rate (ticks/s) +host_mem_usage 287668 # Number of bytes of host memory used +host_seconds 1684.26 # Real time elapsed on the host sim_insts 273037220 # Number of instructions simulated sim_ops 327811602 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1165,6 +1165,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197531008 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 290513216 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 134350 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5056 # Total snoop traffic (bytes) system.cpu.toL2Bus.snoop_fanout::samples 2404477 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.192237 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.468638 # Request fanout histogram @@ -1193,6 +1194,7 @@ system.membus.pkt_count::total 169247 # Pa system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 5415488 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 5415488 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 84630 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini index f27ac4466..1b5061343 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -27,6 +28,10 @@ memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null readfile= symbolfile= thermal_components= @@ -55,6 +60,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -73,6 +79,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -106,9 +116,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker [system.cpu.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.dtb] @@ -122,9 +137,14 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.membus.slave[4] @@ -182,9 +202,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker [system.cpu.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.itb] @@ -198,9 +223,14 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.membus.slave[3] @@ -218,7 +248,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon +executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/eon gid=100 input=cin kvmInSE=false @@ -250,10 +280,15 @@ transition_latency=100000000 [system.membus] type=CoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -268,11 +303,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:134217727 port=system.membus.master[0] diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr index a25196116..c881283f7 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr @@ -1,4 +1,5 @@ warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout index a48a8bb5c..154af3aae 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 14 2015 23:29:19 -gem5 started Sep 15 2015 00:56:31 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:54:12 +gem5 executing on e108600-lin, pid 23918 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index ddaf7206c..e42324626 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.201717 # Nu sim_ticks 201717314000 # Number of ticks simulated final_tick 201717314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1421524 # Simulator instruction rate (inst/s) -host_op_rate 1706697 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1050207028 # Simulator tick rate (ticks/s) -host_mem_usage 310740 # Number of bytes of host memory used -host_seconds 192.07 # Real time elapsed on the host +host_inst_rate 732440 # Simulator instruction rate (inst/s) +host_op_rate 879375 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 541118678 # Simulator tick rate (ticks/s) +host_mem_usage 263976 # Number of bytes of host memory used +host_seconds 372.78 # Real time elapsed on the host sim_insts 273037595 # Number of instructions simulated sim_ops 327811950 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -237,6 +237,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1394641096 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 2275398075 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 517024352 # Request fanout histogram system.membus.snoop_fanout::mean 0.674359 # Request fanout histogram system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini index 72dade1ff..0faba130d 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -27,6 +28,10 @@ memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null readfile= symbolfile= thermal_components= @@ -55,6 +60,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -72,6 +78,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -90,12 +100,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -114,8 +129,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=262144 @@ -138,9 +158,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker [system.cpu.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.dtb] @@ -154,9 +179,14 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[3] @@ -167,12 +197,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -191,8 +226,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=131072 @@ -250,9 +290,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker [system.cpu.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.itb] @@ -266,9 +311,14 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[2] @@ -279,12 +329,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -303,8 +358,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=2097152 @@ -312,10 +372,15 @@ size=2097152 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -346,7 +411,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/cpu2000/binaries/arm/linux/eon +executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/eon gid=100 input=cin kvmInSE=false @@ -378,10 +443,15 @@ transition_latency=100000000 [system.membus] type=CoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -396,11 +466,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:134217727 port=system.membus.master[0] diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr index a25196116..c881283f7 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr @@ -1,4 +1,5 @@ warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout index f8e2a4c4d..bd192fb8a 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 16 2016 23:07:21 -gem5 started Mar 16 2016 23:13:40 -gem5 executing on dinar2c11, pid 25474 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 15:00:59 +gem5 executing on e108600-lin, pid 24143 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index ea2a43ab9..fd046e3e7 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.517291 # Nu sim_ticks 517291025500 # Number of ticks simulated final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 968617 # Simulator instruction rate (inst/s) -host_op_rate 1162861 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1837127354 # Simulator tick rate (ticks/s) -host_mem_usage 320856 # Number of bytes of host memory used -host_seconds 281.58 # Real time elapsed on the host +host_inst_rate 451771 # Simulator instruction rate (inst/s) +host_op_rate 542368 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 856851233 # Simulator tick rate (ticks/s) +host_mem_usage 273716 # Number of bytes of host memory used +host_seconds 603.71 # Real time elapsed on the host sim_insts 272739286 # Number of instructions simulated sim_ops 327433744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -620,6 +620,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 2232000 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) system.cpu.toL2Bus.snoop_fanout::samples 20081 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.386335 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.486921 # Request fanout histogram @@ -647,6 +648,7 @@ system.membus.pkt_count::total 13664 # Pa system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 6833 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram |