diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
| commit | 8909843a76c723cb9d8a0b1394eeeba4d7abadb1 (patch) | |
| tree | 446fe188000e814cbc7d23075428cab7f44868d1 /tests/long/se/30.eon | |
| parent | fc315901ff4aaae0f56c4c1b1c50ffe9bd70b4d6 (diff) | |
| download | gem5-8909843a76c723cb9d8a0b1394eeeba4d7abadb1.tar.xz | |
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
Diffstat (limited to 'tests/long/se/30.eon')
7 files changed, 2352 insertions, 2360 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index 688c5f811..bccf5186d 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.226819 # Number of seconds simulated -sim_ticks 226818771000 # Number of ticks simulated -final_tick 226818771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.226866 # Number of seconds simulated +sim_ticks 226865901500 # Number of ticks simulated +final_tick 226865901500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 207340 # Simulator instruction rate (inst/s) -host_op_rate 207340 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 117965343 # Simulator tick rate (ticks/s) -host_mem_usage 287544 # Number of bytes of host memory used -host_seconds 1922.76 # Real time elapsed on the host +host_inst_rate 324605 # Simulator instruction rate (inst/s) +host_op_rate 324605 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 184721178 # Simulator tick rate (ticks/s) +host_mem_usage 301676 # Number of bytes of host memory used +host_seconds 1228.15 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 249280 # Nu system.physmem.num_reads::cpu.inst 3895 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1099027 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1122447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2221474 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1099027 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1099027 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1099027 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1122447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2221474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1098799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1122214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2221012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1098799 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1098799 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1098799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1122214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2221012 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7873 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7873 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 226818689500 # Total gap between requests +system.physmem.totGap 226865813000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6808 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 980 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6816 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1523 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 329.076822 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 197.330219 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.077184 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 516 33.88% 33.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 348 22.85% 56.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 193 12.67% 69.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 104 6.83% 76.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 58 3.81% 80.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 41 2.69% 82.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 32 2.10% 84.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 40 2.63% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 191 12.54% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1523 # Bytes accessed per row activation -system.physmem.totQLat 50610250 # Total ticks spent queuing -system.physmem.totMemAccLat 198229000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1561 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 321.065983 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 192.383190 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 328.308816 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 550 35.23% 35.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 344 22.04% 57.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 200 12.81% 70.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 103 6.60% 76.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 61 3.91% 80.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 52 3.33% 83.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 34 2.18% 86.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 30 1.92% 88.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 187 11.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1561 # Bytes accessed per row activation +system.physmem.totQLat 54380250 # Total ticks spent queuing +system.physmem.totMemAccLat 201999000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6428.33 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6907.18 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25178.33 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25657.18 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.22 # Average system read bandwidth in MiByte/s @@ -216,70 +216,70 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6341 # Number of row buffer hits during reads +system.physmem.readRowHits 6303 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.54 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.06 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28809690.02 # Average gap between requests -system.physmem.pageHitRate 80.54 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6698160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3654750 # Energy for precharge commands per rank (pJ) +system.physmem.avgGap 28815675.47 # Average gap between requests +system.physmem.pageHitRate 80.06 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6902280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3766125 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 34164000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14814352800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5823127980 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 130980226500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 151662224190 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.664235 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 217898379000 # Time in different power states -system.physmem_0.memoryStateTime::REF 7573800000 # Time in different power states +system.physmem_0.refreshEnergy 14817404160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5855918085 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 130979493750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 151697648400 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.682686 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 217896983750 # Time in different power states +system.physmem_0.memoryStateTime::REF 7575360000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1344256000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1391017250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4808160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2623500 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 4891320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2668875 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 26910000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14814352800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5572496700 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 131200078500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 151621269660 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.483670 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 218263346500 # Time in different power states -system.physmem_1.memoryStateTime::REF 7573800000 # Time in different power states +system.physmem_1.refreshEnergy 14817404160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5585732100 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 131216499000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 151654105455 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.490749 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 218290626750 # Time in different power states +system.physmem_1.memoryStateTime::REF 7575360000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 976701000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 994701750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 46273761 # Number of BP lookups +system.cpu.branchPred.lookups 46273750 # Number of BP lookups system.cpu.branchPred.condPredicted 26730646 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1017469 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25595416 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21359944 # Number of BTB hits +system.cpu.branchPred.BTBLookups 25595406 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21359943 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.452224 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 8341649 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 83.452253 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 8341648 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 95585470 # DTB read hits +system.cpu.dtb.read_hits 95585469 # DTB read hits system.cpu.dtb.read_misses 115 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 95585585 # DTB read accesses -system.cpu.dtb.write_hits 73606436 # DTB write hits +system.cpu.dtb.read_accesses 95585584 # DTB read accesses +system.cpu.dtb.write_hits 73606437 # DTB write hits system.cpu.dtb.write_misses 857 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73607293 # DTB write accesses +system.cpu.dtb.write_accesses 73607294 # DTB write accesses system.cpu.dtb.data_hits 169191906 # DTB hits system.cpu.dtb.data_misses 972 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 169192878 # DTB accesses -system.cpu.itb.fetch_hits 98781228 # ITB hits -system.cpu.itb.fetch_misses 1237 # ITB misses +system.cpu.itb.fetch_hits 98781212 # ITB hits +system.cpu.itb.fetch_misses 1236 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 98782465 # ITB accesses +system.cpu.itb.fetch_accesses 98782448 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,59 +293,59 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 453637542 # number of cpu cycles simulated +system.cpu.numCycles 453731803 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664665 # Number of instructions committed system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4467797 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 4467789 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.137893 # CPI: cycles per instruction -system.cpu.ipc 0.878818 # IPC: instructions per cycle -system.cpu.tickCycles 450174327 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3463215 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.138129 # CPI: cycles per instruction +system.cpu.ipc 0.878635 # IPC: instructions per cycle +system.cpu.tickCycles 450174138 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3557665 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.955330 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168028615 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3291.677539 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168028622 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40343.004802 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40343.006483 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3291.955330 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803700 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803700 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3291.677539 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803632 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803632 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 336075633 # Number of tag accesses system.cpu.dcache.tags.data_accesses 336075633 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 94513823 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94513823 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73514792 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73514792 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168028615 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168028615 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168028615 # number of overall hits -system.cpu.dcache.overall_hits::total 168028615 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1181 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1181 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5938 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5938 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 7119 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7119 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7119 # number of overall misses -system.cpu.dcache.overall_misses::total 7119 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 81009750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 81009750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 391587500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 391587500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 472597250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 472597250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 472597250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 472597250 # number of overall miss cycles +system.cpu.dcache.ReadReq_hits::cpu.data 94513824 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94513824 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73514798 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73514798 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168028622 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168028622 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168028622 # number of overall hits +system.cpu.dcache.overall_hits::total 168028622 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1180 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1180 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5932 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5932 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 7112 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7112 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7112 # number of overall misses +system.cpu.dcache.overall_misses::total 7112 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88706750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88706750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 435640500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 435640500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 524347250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 524347250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 524347250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 524347250 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94515004 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94515004 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) @@ -362,14 +362,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68594.199831 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68594.199831 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65946.025598 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65946.025598 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66385.342042 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66385.342042 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66385.342042 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66385.342042 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75175.211864 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75175.211864 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73439.059339 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73439.059339 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73727.116142 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73727.116142 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73727.116142 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73727.116142 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,28 +382,28 @@ system.cpu.dcache.writebacks::writebacks 654 # nu system.cpu.dcache.writebacks::total 654 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 211 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2743 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2743 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2954 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2954 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2954 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2954 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 970 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 970 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3195 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3195 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2736 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2736 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2947 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2947 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2947 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2947 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3196 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 64296000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 64296000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 214342750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 214342750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 278638750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 278638750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 278638750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 278638750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70790750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 70790750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 240139250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 240139250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 310930000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 310930000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 310930000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 310930000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -412,68 +412,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66284.536082 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66284.536082 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67086.932707 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67086.932707 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66900.060024 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66900.060024 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66900.060024 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66900.060024 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73055.469556 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73055.469556 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75137.437422 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75137.437422 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74653.061224 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74653.061224 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74653.061224 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74653.061224 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3196 # number of replacements -system.cpu.icache.tags.tagsinuse 1918.781818 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 98776054 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1918.668562 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 98776038 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 5174 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19090.849246 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 19090.846154 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1918.781818 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.936905 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.936905 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1918.668562 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.936850 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.936850 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 397 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1281 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 197567630 # Number of tag accesses -system.cpu.icache.tags.data_accesses 197567630 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 98776054 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 98776054 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 98776054 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 98776054 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 98776054 # number of overall hits -system.cpu.icache.overall_hits::total 98776054 # number of overall hits +system.cpu.icache.tags.tag_accesses 197567598 # Number of tag accesses +system.cpu.icache.tags.data_accesses 197567598 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 98776038 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 98776038 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 98776038 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 98776038 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 98776038 # number of overall hits +system.cpu.icache.overall_hits::total 98776038 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 5174 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 5174 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 5174 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 5174 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5174 # number of overall misses system.cpu.icache.overall_misses::total 5174 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 293011250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 293011250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 293011250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 293011250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 293011250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 293011250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 98781228 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 98781228 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 98781228 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 98781228 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 98781228 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 98781228 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 320697250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 320697250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 320697250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 320697250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 320697250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 320697250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 98781212 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 98781212 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 98781212 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 98781212 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 98781212 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 98781212 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56631.474681 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56631.474681 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56631.474681 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56631.474681 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56631.474681 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56631.474681 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61982.460379 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61982.460379 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61982.460379 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61982.460379 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61982.460379 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61982.460379 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -488,41 +488,41 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 5174 system.cpu.icache.demand_mshr_misses::total 5174 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 5174 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 5174 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281053750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281053750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281053750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281053750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281053750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281053750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 311289750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 311289750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 311289750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 311289750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 311289750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 311289750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54320.400077 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54320.400077 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54320.400077 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54320.400077 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54320.400077 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54320.400077 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60164.234635 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60164.234635 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60164.234635 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60164.234635 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60164.234635 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60164.234635 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4426.924727 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4426.526265 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1494 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5273 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.283330 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 373.138335 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.752394 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 642.033998 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011387 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104118 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.019593 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.135099 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 373.084024 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.466195 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 641.976046 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011386 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104110 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.019592 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.135087 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 5273 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 611 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4443 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160919 # Percentage of cache occupancy per task id @@ -552,17 +552,17 @@ system.cpu.l2cache.demand_misses::total 7873 # nu system.cpu.l2cache.overall_misses::cpu.inst 3895 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3978 # number of overall misses system.cpu.l2cache.overall_misses::total 7873 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 263088750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61866750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 324955500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 210698500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 210698500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 263088750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 272565250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 535654000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 263088750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 272565250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 535654000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 292685750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 68346250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 361032000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 236421750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 236421750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 292685750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 304768000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 597453750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 292685750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 304768000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 597453750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 5174 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 967 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 6141 # number of ReadReq accesses(hits+misses) @@ -587,17 +587,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.843024 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.752802 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955102 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.843024 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67545.250321 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73563.317479 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68613.914696 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67165.604080 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67165.604080 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67545.250321 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68518.162393 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68036.834752 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67545.250321 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68518.162393 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68036.834752 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75143.966624 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81267.835910 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76231.418919 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75365.556264 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75365.556264 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75143.966624 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76613.373555 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75886.415598 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75143.966624 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76613.373555 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75886.415598 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -617,17 +617,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7873 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3895 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3978 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7873 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 214177750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 51424250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 265602000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 171025500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 171025500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 214177750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 222449750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 436627500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 214177750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 222449750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 436627500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 243926750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 57790750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 301717500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 197209250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 197209250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 243926750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 255000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 498926750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 243926750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 255000000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 498926750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.752802 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771210 # mshr miss rate for ReadReq accesses @@ -639,17 +639,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.843024 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.752802 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.843024 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54987.869063 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61146.551724 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56081.503378 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54518.807778 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54518.807778 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54987.869063 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55919.997486 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55458.846691 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54987.869063 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55919.997486 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55458.846691 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62625.609756 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68716.706302 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63707.242399 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62865.556264 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62865.556264 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62625.609756 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64102.564103 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63371.872222 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62625.609756 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64102.564103 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63371.872222 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 6141 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 6141 # Transaction distribution @@ -676,9 +676,9 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 9993 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 5650500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8565750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 8584250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6972750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7034000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.trans_dist::ReadReq 4736 # Transaction distribution system.membus.trans_dist::ReadResp 4736 # Transaction distribution @@ -699,9 +699,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7873 # Request fanout histogram -system.membus.reqLayer0.occupancy 9387500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9289000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 73877500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 41806250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 90aeffe97..7866e7931 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.069652 # Number of seconds simulated -sim_ticks 69651704000 # Number of ticks simulated -final_tick 69651704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.069793 # Number of seconds simulated +sim_ticks 69793219500 # Number of ticks simulated +final_tick 69793219500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 253977 # Simulator instruction rate (inst/s) -host_op_rate 253977 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47101012 # Simulator tick rate (ticks/s) -host_mem_usage 302288 # Number of bytes of host memory used -host_seconds 1478.77 # Real time elapsed on the host +host_inst_rate 248568 # Simulator instruction rate (inst/s) +host_op_rate 248568 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46191499 # Simulator tick rate (ticks/s) +host_mem_usage 302704 # Number of bytes of host memory used +host_seconds 1510.95 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 221568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255744 # Number of bytes read from this memory -system.physmem.bytes_read::total 477312 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221568 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3462 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3996 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7458 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3181085 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3671755 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6852840 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3181085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3181085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3181085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3671755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6852840 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7458 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 221440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255808 # Number of bytes read from this memory +system.physmem.bytes_read::total 477248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221440 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3460 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3997 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7457 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 3172801 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3665227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6838028 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3172801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3172801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3172801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3665227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6838028 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7457 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7458 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7457 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 477312 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 477248 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 477312 # Total read bytes from the system interface side +system.physmem.bytesReadSys 477248 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 528 # Per bank write bursts -system.physmem.perBankRdBursts::1 655 # Per bank write bursts +system.physmem.perBankRdBursts::0 527 # Per bank write bursts +system.physmem.perBankRdBursts::1 657 # Per bank write bursts system.physmem.perBankRdBursts::2 455 # Per bank write bursts system.physmem.perBankRdBursts::3 602 # Per bank write bursts system.physmem.perBankRdBursts::4 446 # Per bank write bursts system.physmem.perBankRdBursts::5 454 # Per bank write bursts system.physmem.perBankRdBursts::6 515 # Per bank write bursts -system.physmem.perBankRdBursts::7 524 # Per bank write bursts -system.physmem.perBankRdBursts::8 439 # Per bank write bursts -system.physmem.perBankRdBursts::9 406 # Per bank write bursts -system.physmem.perBankRdBursts::10 340 # Per bank write bursts +system.physmem.perBankRdBursts::7 522 # Per bank write bursts +system.physmem.perBankRdBursts::8 438 # Per bank write bursts +system.physmem.perBankRdBursts::9 407 # Per bank write bursts +system.physmem.perBankRdBursts::10 339 # Per bank write bursts system.physmem.perBankRdBursts::11 305 # Per bank write bursts system.physmem.perBankRdBursts::12 414 # Per bank write bursts system.physmem.perBankRdBursts::13 542 # Per bank write bursts -system.physmem.perBankRdBursts::14 454 # Per bank write bursts +system.physmem.perBankRdBursts::14 455 # Per bank write bursts system.physmem.perBankRdBursts::15 379 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 69651614500 # Total gap between requests +system.physmem.totGap 69793123000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7458 # Read request sizes (log2) +system.physmem.readPktSize::6 7457 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4228 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 63 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4245 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -186,100 +186,100 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1353 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 350.509978 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 208.904608 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 348.764111 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 423 31.26% 31.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 330 24.39% 55.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 152 11.23% 66.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 83 6.13% 73.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 55 4.07% 77.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 43 3.18% 80.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 38 2.81% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 25 1.85% 84.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 204 15.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1353 # Bytes accessed per row activation -system.physmem.totQLat 67034750 # Total ticks spent queuing -system.physmem.totMemAccLat 206872250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37290000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8988.30 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1360 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 348.047059 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 208.039838 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 346.646558 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 428 31.47% 31.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 327 24.04% 55.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 157 11.54% 67.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 92 6.76% 73.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 56 4.12% 77.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 39 2.87% 80.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 33 2.43% 83.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 25 1.84% 85.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 203 14.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1360 # Bytes accessed per row activation +system.physmem.totQLat 67335750 # Total ticks spent queuing +system.physmem.totMemAccLat 207154500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37285000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9029.87 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27738.30 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.85 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27779.87 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.84 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.85 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.84 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6096 # Number of row buffer hits during reads +system.physmem.readRowHits 6086 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.74 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9339181.35 # Average gap between requests -system.physmem.pageHitRate 81.74 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5843880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3188625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 32385600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 9359410.35 # Average gap between requests +system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5828760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3180375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 32377800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4549069200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2090226195 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 39955428000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 46636141500 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.595153 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 66468117000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2325700000 # Time in different power states +system.physmem_0.refreshEnergy 4558223280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2111779035 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 40020613500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 46732002750 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.624038 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 66577889000 # Time in different power states +system.physmem_0.memoryStateTime::REF 2330380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 855864000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 882777000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4362120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2380125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 25373400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 4430160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2417250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 25272000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4549069200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1978191270 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 40053704250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 46613080365 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.264045 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 66630949750 # Time in different power states -system.physmem_1.memoryStateTime::REF 2325700000 # Time in different power states +system.physmem_1.refreshEnergy 4558223280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2013356565 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 40106949000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 46710648255 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.318049 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 66719394750 # Time in different power states +system.physmem_1.memoryStateTime::REF 2330380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 691630250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 738657750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 51167471 # Number of BP lookups -system.cpu.branchPred.condPredicted 29641015 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1213095 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25804996 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23600999 # Number of BTB hits +system.cpu.branchPred.lookups 51259743 # Number of BP lookups +system.cpu.branchPred.condPredicted 29683169 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1233682 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 26552604 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23664767 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 91.459030 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9351091 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 307 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.124091 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9366329 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 317 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 103696202 # DTB read hits -system.cpu.dtb.read_misses 91462 # DTB read misses -system.cpu.dtb.read_acv 49407 # DTB read access violations -system.cpu.dtb.read_accesses 103787664 # DTB read accesses -system.cpu.dtb.write_hits 79414480 # DTB write hits -system.cpu.dtb.write_misses 1579 # DTB write misses +system.cpu.dtb.read_hits 103795078 # DTB read hits +system.cpu.dtb.read_misses 91880 # DTB read misses +system.cpu.dtb.read_acv 49322 # DTB read access violations +system.cpu.dtb.read_accesses 103886958 # DTB read accesses +system.cpu.dtb.write_hits 79431295 # DTB write hits +system.cpu.dtb.write_misses 1540 # DTB write misses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 79416059 # DTB write accesses -system.cpu.dtb.data_hits 183110682 # DTB hits -system.cpu.dtb.data_misses 93041 # DTB misses -system.cpu.dtb.data_acv 49409 # DTB access violations -system.cpu.dtb.data_accesses 183203723 # DTB accesses -system.cpu.itb.fetch_hits 51277820 # ITB hits -system.cpu.itb.fetch_misses 422 # ITB misses +system.cpu.dtb.write_accesses 79432835 # DTB write accesses +system.cpu.dtb.data_hits 183226373 # DTB hits +system.cpu.dtb.data_misses 93420 # DTB misses +system.cpu.dtb.data_acv 49324 # DTB access violations +system.cpu.dtb.data_accesses 183319793 # DTB accesses +system.cpu.itb.fetch_hits 51424924 # ITB hits +system.cpu.itb.fetch_misses 367 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 51278242 # ITB accesses +system.cpu.itb.fetch_accesses 51425291 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,239 +293,239 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 139303411 # number of cpu cycles simulated +system.cpu.numCycles 139586442 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 52063926 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 457094521 # Number of instructions fetch has processed -system.cpu.fetch.Branches 51167471 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 32952090 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 85692281 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2532764 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 52218190 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 457878359 # Number of instructions fetch has processed +system.cpu.fetch.Branches 51259743 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33031096 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 85762697 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2573496 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 13783 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 51277820 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 545278 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 139036576 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.287585 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.344928 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.MiscStallCycles 172 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 13442 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 10 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 51424924 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 558112 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 139281263 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.287437 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.344389 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 58307337 41.94% 41.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4519216 3.25% 45.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 7280822 5.24% 50.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5545601 3.99% 54.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11970286 8.61% 63.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 8019991 5.77% 68.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5933032 4.27% 73.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1884761 1.36% 74.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35575530 25.59% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58400466 41.93% 41.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4519538 3.24% 45.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 7300185 5.24% 50.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5568881 4.00% 54.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11993718 8.61% 63.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 8035210 5.77% 68.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5954127 4.27% 73.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1896980 1.36% 74.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35612158 25.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 139036576 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.367310 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.281287 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45112383 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16348146 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 71787003 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4526860 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1262184 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9563244 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4245 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 451283163 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 14196 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1262184 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 47011024 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5663526 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 519113 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 74309218 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10271511 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 447721649 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 439815 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2540100 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2926498 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 3600527 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 292278306 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 589607782 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 419965282 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 169642499 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 139281263 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.367226 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.280250 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45296559 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16238717 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 71951122 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4512320 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1282545 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9579038 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4257 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 452073358 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 14179 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1282545 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 47196926 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5664651 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 519192 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 74460720 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 10157229 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 448418638 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 439172 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2532304 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2861217 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 3565763 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 292805975 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 590541853 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 420605547 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 169936305 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32745977 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 37893 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 316 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 16173797 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 106306370 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 81667386 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12470725 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9729569 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 414594685 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 306 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 406915918 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 484036 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 38878487 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 18208107 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 91 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 139036576 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.926683 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.221929 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 33273646 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 37923 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 320 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 15988914 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 106425467 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 81691000 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12462225 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9670397 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 415046688 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 308 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 407272286 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 487219 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 39326693 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 18379010 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 93 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 139281263 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.924100 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.223091 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23891494 17.18% 17.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19616678 14.11% 31.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22677483 16.31% 47.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18900240 13.59% 61.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 19609416 14.10% 75.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14153871 10.18% 85.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9626410 6.92% 92.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6209797 4.47% 96.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4351187 3.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24058662 17.27% 17.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19633951 14.10% 31.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22674806 16.28% 47.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18925755 13.59% 61.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 19544360 14.03% 75.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14234748 10.22% 85.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9653364 6.93% 92.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6204842 4.45% 96.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4350775 3.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 139036576 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 139281263 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 258477 1.29% 1.29% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1 0.00% 1.29% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 145250 0.73% 2.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 90218 0.45% 2.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 2947 0.01% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 3497968 17.50% 19.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1676632 8.39% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9338598 46.73% 75.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4976149 24.90% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 264805 1.33% 1.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 148480 0.74% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 91560 0.46% 2.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 2226 0.01% 2.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 3500111 17.53% 20.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1672568 8.38% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9323721 46.69% 75.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4965817 24.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 153207490 37.65% 37.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2128182 0.52% 38.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 37392506 9.19% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7524499 1.85% 49.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2804822 0.69% 49.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16757586 4.12% 54.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1601657 0.39% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 105367868 25.89% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 80097727 19.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 153389569 37.66% 37.67% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2128191 0.52% 38.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 37431648 9.19% 47.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7537641 1.85% 49.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2804878 0.69% 49.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16758896 4.11% 54.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1606846 0.39% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 105464958 25.90% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 80116078 19.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 406915918 # Type of FU issued -system.cpu.iq.rate 2.921076 # Inst issue rate -system.cpu.iq.fu_busy_cnt 19986240 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.049116 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 625897049 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 265989715 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237228631 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 347441639 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 187559752 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 163339265 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 246150914 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 180717663 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19936358 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 407272286 # Type of FU issued +system.cpu.iq.rate 2.917707 # Inst issue rate +system.cpu.iq.fu_busy_cnt 19969288 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.049032 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 626696170 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 266696972 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237458259 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 347586172 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 187752417 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 163387975 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 246426590 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 180781403 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19964423 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 11551883 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 163597 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 76334 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8146657 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 11670980 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 165408 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 76048 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8170271 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 381699 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4488 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 382447 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3767 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1262184 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4471526 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 139208 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 439574480 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 145285 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 106306370 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 81667386 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 306 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6690 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 131691 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 76334 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 976027 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412585 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1388612 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 403157736 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 103837102 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3758182 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1282545 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4525606 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 90420 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 440059104 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 152527 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 106425467 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 81691000 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 308 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 7009 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 82356 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 76048 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1000879 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 421168 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1422047 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 403473304 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 103936308 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3798982 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24979489 # number of nop insts executed -system.cpu.iew.exec_refs 183253198 # number of memory reference insts executed -system.cpu.iew.exec_branches 46959989 # Number of branches executed -system.cpu.iew.exec_stores 79416096 # Number of stores executed -system.cpu.iew.exec_rate 2.894098 # Inst execution rate -system.cpu.iew.wb_sent 401401507 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 400567896 # cumulative count of insts written-back -system.cpu.iew.wb_producers 198000452 # num instructions producing a value -system.cpu.iew.wb_consumers 283955606 # num instructions consuming a value +system.cpu.iew.exec_nop 25012108 # number of nop insts executed +system.cpu.iew.exec_refs 183369178 # number of memory reference insts executed +system.cpu.iew.exec_branches 46997600 # Number of branches executed +system.cpu.iew.exec_stores 79432870 # Number of stores executed +system.cpu.iew.exec_rate 2.890491 # Inst execution rate +system.cpu.iew.wb_sent 401684713 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 400846234 # cumulative count of insts written-back +system.cpu.iew.wb_producers 198095133 # num instructions producing a value +system.cpu.iew.wb_consumers 284050882 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.875507 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.697294 # average fanout of values written-back +system.cpu.iew.wb_rate 2.871670 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.697393 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 40912072 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 41395670 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1208897 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 133310723 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.990491 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.213946 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1229479 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 133482933 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.986633 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.212859 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 48555712 36.42% 36.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18055923 13.54% 49.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 9630862 7.22% 57.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8737322 6.55% 63.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6426217 4.82% 68.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4404759 3.30% 71.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4988493 3.74% 75.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2616131 1.96% 77.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29895304 22.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 48683097 36.47% 36.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18109981 13.57% 50.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 9618460 7.21% 57.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8715508 6.53% 63.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6449297 4.83% 68.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4412968 3.31% 71.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5003390 3.75% 75.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2633066 1.97% 77.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29857166 22.37% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 133310723 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 133482933 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -571,128 +571,128 @@ system.cpu.commit.op_class_0::MemWrite 73520729 18.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 398664583 # Class of committed instruction -system.cpu.commit.bw_lim_events 29895304 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29857166 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 542989097 # The number of ROB reads -system.cpu.rob.rob_writes 884890973 # The number of ROB writes -system.cpu.timesIdled 3476 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 266835 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 543683043 # The number of ROB reads +system.cpu.rob.rob_writes 885930772 # The number of ROB writes +system.cpu.timesIdled 3165 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 305179 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.370907 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.370907 # CPI: Total CPI of All Threads -system.cpu.ipc 2.696092 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.696092 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 403240146 # number of integer regfile reads -system.cpu.int_regfile_writes 171897288 # number of integer regfile writes -system.cpu.fp_regfile_reads 157938395 # number of floating regfile reads -system.cpu.fp_regfile_writes 105579710 # number of floating regfile writes +system.cpu.cpi 0.371661 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.371661 # CPI: Total CPI of All Threads +system.cpu.ipc 2.690625 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.690625 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 403591803 # number of integer regfile reads +system.cpu.int_regfile_writes 172078772 # number of integer regfile writes +system.cpu.fp_regfile_reads 157997982 # number of floating regfile reads +system.cpu.fp_regfile_writes 105636085 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 798 # number of replacements -system.cpu.dcache.tags.tagsinuse 3297.113166 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 156873476 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4201 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37341.936682 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 806 # number of replacements +system.cpu.dcache.tags.tagsinuse 3297.136243 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 156944357 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4209 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37287.801616 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3297.113166 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.804959 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.804959 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3297.136243 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.804965 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.804965 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3403 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 3119 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.830811 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 313794583 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 313794583 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 83372633 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 83372633 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73500836 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73500836 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 7 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 7 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 156873469 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 156873469 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 156873469 # number of overall hits -system.cpu.dcache.overall_hits::total 156873469 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1822 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1822 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19893 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19893 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21715 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21715 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21715 # number of overall misses -system.cpu.dcache.overall_misses::total 21715 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 114608500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 114608500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1125293584 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1125293584 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1239902084 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1239902084 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1239902084 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1239902084 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 83374455 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 83374455 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 313935887 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 313935887 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 83443297 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 83443297 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501051 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501051 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 156944348 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 156944348 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 156944348 # number of overall hits +system.cpu.dcache.overall_hits::total 156944348 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1804 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1804 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19678 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19678 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21482 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21482 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21482 # number of overall misses +system.cpu.dcache.overall_misses::total 21482 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 122640500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 122640500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1228413709 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1228413709 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1351054209 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1351054209 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1351054209 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1351054209 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 83445101 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 83445101 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 156895184 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 156895184 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 156895184 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 156895184 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 9 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 9 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 156965830 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 156965830 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 156965830 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 156965830 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000271 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000271 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000138 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000138 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000138 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000138 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62902.579583 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62902.579583 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56567.314332 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56567.314332 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 57098.875616 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 57098.875616 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 57098.875616 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 57098.875616 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 46396 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 61 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 946 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000268 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000268 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000137 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000137 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000137 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000137 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67982.538803 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67982.538803 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62425.739862 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62425.739862 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62892.384741 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62892.384741 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62892.384741 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62892.384741 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 51314 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 108 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 737 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.044397 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 61 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.625509 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 108 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 674 # number of writebacks -system.cpu.dcache.writebacks::total 674 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 824 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 824 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16690 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16690 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17514 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17514 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17514 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17514 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 998 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 998 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3203 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3203 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4201 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4201 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4201 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4201 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67693000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 67693000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 235962750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 235962750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 303655750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 303655750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 303655750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 303655750 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 682 # number of writebacks +system.cpu.dcache.writebacks::total 682 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 803 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 803 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16470 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16470 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17273 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17273 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17273 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17273 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1001 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1001 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3208 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3208 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4209 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4209 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4209 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4209 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 72824500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 72824500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 253362750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 253362750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 326187250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 326187250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 326187250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 326187250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -701,198 +701,198 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67828.657315 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67828.657315 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73669.294411 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73669.294411 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72281.778148 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72281.778148 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72281.778148 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72281.778148 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72751.748252 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72751.748252 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78978.413342 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78978.413342 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77497.564742 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77497.564742 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77497.564742 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77497.564742 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2164 # number of replacements -system.cpu.icache.tags.tagsinuse 1832.364532 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 51272141 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4091 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12532.911513 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2160 # number of replacements +system.cpu.icache.tags.tagsinuse 1831.206745 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 51419247 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4087 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12581.171275 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1832.364532 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.894709 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.894709 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1831.206745 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894144 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894144 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1927 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 294 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1343 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 289 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1348 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.940918 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 102559731 # Number of tag accesses -system.cpu.icache.tags.data_accesses 102559731 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 51272141 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 51272141 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 51272141 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 51272141 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 51272141 # number of overall hits -system.cpu.icache.overall_hits::total 51272141 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5679 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5679 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5679 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5679 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5679 # number of overall misses -system.cpu.icache.overall_misses::total 5679 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 341090499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 341090499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 341090499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 341090499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 341090499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 341090499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 51277820 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 51277820 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 51277820 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 51277820 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 51277820 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 51277820 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000111 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000111 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000111 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000111 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000111 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000111 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60061.718436 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 60061.718436 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 60061.718436 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 60061.718436 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 60061.718436 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 60061.718436 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 528 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 102853935 # Number of tag accesses +system.cpu.icache.tags.data_accesses 102853935 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 51419247 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 51419247 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 51419247 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 51419247 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 51419247 # number of overall hits +system.cpu.icache.overall_hits::total 51419247 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5677 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5677 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5677 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5677 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5677 # number of overall misses +system.cpu.icache.overall_misses::total 5677 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 373029250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 373029250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 373029250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 373029250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 373029250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 373029250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 51424924 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 51424924 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 51424924 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 51424924 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 51424924 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 51424924 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000110 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000110 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000110 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000110 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000110 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000110 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65708.869121 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 65708.869121 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 65708.869121 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 65708.869121 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 65708.869121 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65708.869121 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 290 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 58.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 58 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1588 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1588 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1588 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1588 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1588 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1588 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4091 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4091 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4091 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4091 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4091 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4091 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 250258250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 250258250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 250258250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 250258250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 250258250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 250258250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61172.879492 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61172.879492 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61172.879492 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61172.879492 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61172.879492 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61172.879492 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1590 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1590 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1590 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1590 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1590 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1590 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4087 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4087 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4087 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4087 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4087 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4087 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 274156250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 274156250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 274156250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 274156250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 274156250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 274156250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67080.070957 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67080.070957 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67080.070957 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67080.070957 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67080.070957 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67080.070957 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4021.632512 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 866 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4864 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.178043 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 4023.366871 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 875 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4863 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.179930 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 371.133834 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2983.663344 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 666.835334 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011326 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.091054 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.020350 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.122730 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 4864 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 535 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4046 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148438 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 79795 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 79795 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 629 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 132 # number of ReadReq hits +system.cpu.l2cache.tags.occ_blocks::writebacks 372.059378 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2982.142231 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 669.165262 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011354 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.091008 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.020421 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.122783 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 4863 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 148 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 529 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4051 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148407 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 79895 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 79895 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 627 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 134 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 761 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 674 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 674 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 73 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 73 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 629 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 205 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 834 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 629 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 205 # number of overall hits -system.cpu.l2cache.overall_hits::total 834 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3462 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 866 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4328 # number of ReadReq misses +system.cpu.l2cache.Writeback_hits::writebacks 682 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 682 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 78 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 78 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 627 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 212 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 839 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 627 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 212 # number of overall hits +system.cpu.l2cache.overall_hits::total 839 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3460 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 867 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4327 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 3130 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 3130 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3462 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3996 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7458 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3462 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3996 # number of overall misses -system.cpu.l2cache.overall_misses::total 7458 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 239866750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 65282000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 305148750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 231929750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 231929750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 239866750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 297211750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 537078500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 239866750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 297211750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 537078500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 4091 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 998 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5089 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 674 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 674 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 3203 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 3203 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4091 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 4201 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 8292 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4091 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4201 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 8292 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.846248 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.867735 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.850462 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.977209 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.977209 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.846248 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.951202 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.899421 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.846248 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.951202 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.899421 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69285.600809 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75383.371824 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70505.718577 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74098.961661 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74098.961661 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69285.600809 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74377.314815 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72013.743631 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69285.600809 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74377.314815 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72013.743631 # average overall miss latency +system.cpu.l2cache.demand_misses::cpu.inst 3460 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3997 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7457 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3460 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3997 # number of overall misses +system.cpu.l2cache.overall_misses::total 7457 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 263476500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70328000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 333804500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 249238250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 249238250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 263476500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 319566250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 583042750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 263476500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 319566250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 583042750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4087 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1001 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5088 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 682 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 682 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 3208 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 3208 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4087 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4209 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8296 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4087 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4209 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 8296 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.846587 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.866134 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.850432 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.975686 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.975686 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.846587 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.949632 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.898867 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.846587 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.949632 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.898867 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76149.277457 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81116.493656 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 77144.557430 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79628.833866 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79628.833866 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76149.277457 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79951.526145 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78187.307228 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76149.277457 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79951.526145 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78187.307228 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -901,102 +901,102 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3462 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 866 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4328 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3460 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 867 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4327 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3130 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 3130 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3462 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3996 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7458 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3462 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3996 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7458 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 195982250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54610500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 250592750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 193350250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 193350250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195982250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 247960750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 443943000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195982250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 247960750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 443943000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867735 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.850462 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.977209 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.977209 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.951202 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.899421 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.951202 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.899421 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56609.546505 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63060.623557 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57900.358133 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61773.242812 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61773.242812 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56609.546505 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62052.239740 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59525.744167 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56609.546505 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62052.239740 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59525.744167 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3460 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3997 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7457 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3460 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3997 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7457 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 220205500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 59518000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 279723500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 210540750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 210540750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 220205500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 270058750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 490264250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 220205500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 270058750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 490264250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.846587 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.866134 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.850432 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.975686 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.975686 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.846587 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.949632 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.898867 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.846587 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.949632 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.898867 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63643.208092 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68648.212226 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64646.059626 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67265.415335 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67265.415335 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63643.208092 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67565.361521 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65745.507577 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63643.208092 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67565.361521 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65745.507577 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 5089 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5089 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 674 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3203 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3203 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8182 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9076 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 17258 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 573824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 5088 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5088 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 682 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3208 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3208 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8174 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9100 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 17274 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 313024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 574592 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 8966 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 8978 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 8966 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 8978 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8966 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5157000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 8978 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5171000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6787250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6830250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6700250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6882750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 4328 # Transaction distribution -system.membus.trans_dist::ReadResp 4328 # Transaction distribution +system.membus.trans_dist::ReadReq 4327 # Transaction distribution +system.membus.trans_dist::ReadResp 4327 # Transaction distribution system.membus.trans_dist::ReadExReq 3130 # Transaction distribution system.membus.trans_dist::ReadExResp 3130 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14916 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14916 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 477312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14914 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14914 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 477248 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7458 # Request fanout histogram +system.membus.snoop_fanout::samples 7457 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7458 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7457 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7458 # Request fanout histogram -system.membus.reqLayer0.occupancy 9422500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7457 # Request fanout histogram +system.membus.reqLayer0.occupancy 9341500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 69712000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 39310250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 01baacd99..97440304f 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.567335 # Number of seconds simulated -sim_ticks 567335093000 # Number of ticks simulated -final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 567335093500 # Number of ticks simulated +final_tick 567335093500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1606485 # Simulator instruction rate (inst/s) -host_op_rate 1606484 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2286169690 # Simulator tick rate (ticks/s) -host_mem_usage 295576 # Number of bytes of host memory used -host_seconds 248.16 # Real time elapsed on the host +host_inst_rate 1360508 # Simulator instruction rate (inst/s) +host_op_rate 1360508 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1936123010 # Simulator tick rate (ticks/s) +host_mem_usage 299124 # Number of bytes of host memory used +host_seconds 293.03 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,29 +29,6 @@ system.physmem.bw_inst_read::total 361550 # In system.physmem.bw_total::cpu.inst 361550 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 447735 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 809285 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 4032 # Transaction distribution -system.membus.trans_dist::ReadResp 4032 # Transaction distribution -system.membus.trans_dist::ReadExReq 3142 # Transaction distribution -system.membus.trans_dist::ReadExResp 3142 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14348 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14348 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 459136 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7174 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7174 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7174 # Request fanout histogram -system.membus.reqLayer0.occupancy 7174000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 64566000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -86,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 1134670186 # number of cpu cycles simulated +system.cpu.numCycles 1134670187 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664609 # Number of instructions committed @@ -105,7 +82,7 @@ system.cpu.num_mem_refs 168275276 # nu system.cpu.num_load_insts 94754511 # Number of load instructions system.cpu.num_store_insts 73520765 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1134670186 # Number of busy cycles +system.cpu.num_busy_cycles 1134670187 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 44587535 # Number of branches fetched @@ -144,13 +121,122 @@ system.cpu.op_class::MemWrite 73520765 18.44% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 398664665 # Class of executed instruction +system.cpu.dcache.tags.replacements 764 # number of replacements +system.cpu.dcache.tags.tagsinuse 3288.930570 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3288.930570 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.802962 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 210 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 3112 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.827148 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 336554592 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336554592 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73517528 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168271068 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168271068 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168271068 # number of overall hits +system.cpu.dcache.overall_hits::total 168271068 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 950 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 950 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3202 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3202 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 4152 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses +system.cpu.dcache.overall_misses::total 4152 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 47084000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 47084000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 173590000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 173590000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 220674000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 220674000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 220674000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 220674000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 168275220 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168275220 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168275220 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168275220 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000010 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000010 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000044 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000044 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49562.105263 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49562.105263 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54212.991880 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54212.991880 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53148.843931 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53148.843931 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 649 # number of writebacks +system.cpu.dcache.writebacks::total 649 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45659000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 45659000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 168787000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 168787000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 214446000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 214446000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 214446000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 214446000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48062.105263 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48062.105263 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52712.991880 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52712.991880 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51648.843931 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51648.843931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51648.843931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51648.843931 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1769 # number of replacements -system.cpu.icache.tags.tagsinuse 1795.138964 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1795.138960 # Cycle average of tags in use system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1795.138964 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1795.138960 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.876533 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1904 # Occupied blocks per task id @@ -174,12 +260,12 @@ system.cpu.icache.demand_misses::cpu.inst 3673 # n system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses system.cpu.icache.overall_misses::total 3673 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 182359000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 182359000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 182359000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 182359000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 182359000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 182359000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 182359500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 182359500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 182359500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 182359500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 182359500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 182359500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses @@ -192,12 +278,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49648.516199 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49648.516199 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49648.516199 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49648.516199 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49648.516199 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49648.516199 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49648.652328 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49648.652328 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49648.652328 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49648.652328 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49648.652328 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49648.652328 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -212,34 +298,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3673 system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175013000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 175013000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175013000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 175013000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175013000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 175013000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 176850000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 176850000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 176850000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 176850000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 176850000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 176850000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47648.516199 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47648.516199 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48148.652328 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48148.652328 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48148.652328 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48148.652328 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48148.652328 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48148.652328 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3772.485305 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3772.485298 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 677 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4566 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.148270 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 371.540221 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.469924 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 630.475161 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 371.540220 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.469918 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 630.475159 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011339 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.019241 # Average percentage of cache occupancy @@ -277,17 +363,17 @@ system.cpu.l2cache.demand_misses::total 7174 # nu system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7174 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 166660000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43004000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 209664000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163384000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 163384000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 166660000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 206388000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 373048000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 166660000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 206388000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 373048000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 168263000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43417500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 211680500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 164955000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 164955000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 168263000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 208372500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 376635500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 168263000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 208372500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 376635500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3673 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 950 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4623 # number of ReadReq accesses(hits+misses) @@ -312,17 +398,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.916805 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916805 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.156006 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.124008 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.156006 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.069696 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.156006 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.069696 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -342,17 +428,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7174 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7174 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 128200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33080000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 161280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 125680000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 125680000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 128200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158760000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 286960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 128200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158760000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 286960000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 129802500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33493500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 163296000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 127251000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 127251000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129802500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160744500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 290547000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129802500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160744500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 290547000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870526 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.872161 # mshr miss rate for ReadReq accesses @@ -364,127 +450,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.916805 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.916805 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 764 # number of replacements -system.cpu.dcache.tags.tagsinuse 3288.930576 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3288.930576 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.802962 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 210 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 3112 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.827148 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336554592 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336554592 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73517528 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168271068 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168271068 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168271068 # number of overall hits -system.cpu.dcache.overall_hits::total 168271068 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 950 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 950 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3202 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3202 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 4152 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses -system.cpu.dcache.overall_misses::total 4152 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 47084000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 47084000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 173590000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 173590000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 220674000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 220674000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 220674000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 220674000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168275220 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168275220 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168275220 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168275220 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000010 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000010 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000044 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000044 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49562.105263 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49562.105263 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54212.991880 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54212.991880 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53148.843931 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53148.843931 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 649 # number of writebacks -system.cpu.dcache.writebacks::total 649 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45184000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 45184000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167186000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 167186000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212370000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 212370000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212370000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 212370000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47562.105263 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47562.105263 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52212.991880 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52212.991880 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 4623 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution @@ -514,5 +491,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 5509500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6228000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 4032 # Transaction distribution +system.membus.trans_dist::ReadResp 4032 # Transaction distribution +system.membus.trans_dist::ReadExReq 3142 # Transaction distribution +system.membus.trans_dist::ReadExResp 3142 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14348 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14348 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 459136 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7174 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 7174 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 7174 # Request fanout histogram +system.membus.reqLayer0.occupancy 7174500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 35870500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index dd174365b..32197bf04 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.216828 # Number of seconds simulated -sim_ticks 216828260500 # Number of ticks simulated -final_tick 216828260500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.216865 # Number of seconds simulated +sim_ticks 216864820000 # Number of ticks simulated +final_tick 216864820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113548 # Simulator instruction rate (inst/s) -host_op_rate 136327 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90171945 # Simulator tick rate (ticks/s) -host_mem_usage 309844 # Number of bytes of host memory used -host_seconds 2404.61 # Real time elapsed on the host +host_inst_rate 175540 # Simulator instruction rate (inst/s) +host_op_rate 210755 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 139425507 # Simulator tick rate (ticks/s) +host_mem_usage 321524 # Number of bytes of host memory used +host_seconds 1555.42 # Real time elapsed on the host sim_insts 273037856 # Number of instructions simulated sim_ops 327812213 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 219008 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 266368 # Number of bytes read from this memory -system.physmem.bytes_read::total 485440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3423 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 485376 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219008 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3422 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7585 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1010348 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1228475 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2238823 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1010348 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1010348 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1010348 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1228475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2238823 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7585 # Number of read requests accepted +system.physmem.num_reads::total 7584 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1009883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1228267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2238150 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1009883 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1009883 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1009883 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1228267 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2238150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7584 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7585 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7584 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 485440 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 485376 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 485440 # Total read bytes from the system interface side +system.physmem.bytesReadSys 485376 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -53,7 +53,7 @@ system.physmem.perBankRdBursts::8 209 # Pe system.physmem.perBankRdBursts::9 311 # Per bank write bursts system.physmem.perBankRdBursts::10 342 # Per bank write bursts system.physmem.perBankRdBursts::11 428 # Per bank write bursts -system.physmem.perBankRdBursts::12 554 # Per bank write bursts +system.physmem.perBankRdBursts::12 553 # Per bank write bursts system.physmem.perBankRdBursts::13 706 # Per bank write bursts system.physmem.perBankRdBursts::14 637 # Per bank write bursts system.physmem.perBankRdBursts::15 541 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 216828031000 # Total gap between requests +system.physmem.totGap 216864583500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7585 # Read request sizes (log2) +system.physmem.readPktSize::6 7584 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6628 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 896 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6626 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1505 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 321.360797 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 189.304771 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.736324 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 549 36.48% 36.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 346 22.99% 59.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 165 10.96% 70.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 68 4.52% 74.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 70 4.65% 79.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 58 3.85% 83.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 34 2.26% 85.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 33 2.19% 87.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 182 12.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1505 # Bytes accessed per row activation -system.physmem.totQLat 50845500 # Total ticks spent queuing -system.physmem.totMemAccLat 193064250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37925000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6703.43 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1523 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 317.772817 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.476979 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.358112 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 549 36.05% 36.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 352 23.11% 59.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 179 11.75% 70.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 73 4.79% 75.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 70 4.60% 80.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 53 3.48% 83.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 37 2.43% 86.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 29 1.90% 88.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 181 11.88% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1523 # Bytes accessed per row activation +system.physmem.totQLat 53728750 # Total ticks spent queuing +system.physmem.totMemAccLat 195928750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37920000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7084.49 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25453.43 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25834.49 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.24 # Average system read bandwidth in MiByte/s @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6073 # Number of row buffer hits during reads +system.physmem.readRowHits 6056 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.07 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.85 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28586424.65 # Average gap between requests -system.physmem.pageHitRate 80.07 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5012280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2734875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 28595013.65 # Average gap between requests +system.physmem.pageHitRate 79.85 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5027400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2743125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 29952000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14161870320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5652564030 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 125135988750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 144988075455 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.690273 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 208174326250 # Time in different power states -system.physmem_0.memoryStateTime::REF 7240220000 # Time in different power states +system.physmem_0.refreshEnergy 14164413120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5668320825 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 125145525750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 145015982220 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.698913 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 208188918000 # Time in different power states +system.physmem_0.memoryStateTime::REF 7241520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1410814750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1432738500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6342840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3460875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 29000400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 6486480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3539250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 29031600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14161870320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5745534165 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 125054436000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 145000644600 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.748242 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 208036674250 # Time in different power states -system.physmem_1.memoryStateTime::REF 7240220000 # Time in different power states +system.physmem_1.refreshEnergy 14164413120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5831746380 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 125002170000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 145037386830 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.797614 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 207947266000 # Time in different power states +system.physmem_1.memoryStateTime::REF 7241520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1549163250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1674122750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 33221230 # Number of BP lookups -system.cpu.branchPred.condPredicted 17174007 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1583983 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17995686 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15666979 # Number of BTB hits +system.cpu.branchPred.lookups 33219592 # Number of BP lookups +system.cpu.branchPred.condPredicted 17177082 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1581285 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17974979 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15661112 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.059638 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6611215 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 87.127290 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6612085 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,75 +377,75 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 433656521 # number of cpu cycles simulated +system.cpu.numCycles 433729640 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 273037856 # Number of instructions committed system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4064410 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 4054235 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.588265 # CPI: cycles per instruction -system.cpu.ipc 0.629618 # IPC: instructions per cycle -system.cpu.tickCycles 430211127 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3445394 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.588533 # CPI: cycles per instruction +system.cpu.ipc 0.629512 # IPC: instructions per cycle +system.cpu.tickCycles 430193160 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3536480 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 1354 # number of replacements -system.cpu.dcache.tags.tagsinuse 3086.009488 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168783807 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3085.768991 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168782225 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37416.051208 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37415.700510 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3086.009488 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.753420 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.753420 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768991 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.753362 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.753362 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 337586705 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 337586705 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 86714567 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86714567 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82047450 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047450 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 337583521 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337583521 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86712977 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86712977 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82047458 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047458 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168762017 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168762017 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168762017 # number of overall hits -system.cpu.dcache.overall_hits::total 168762017 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2063 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2063 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5227 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5227 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 7290 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7290 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7290 # number of overall misses -system.cpu.dcache.overall_misses::total 7290 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 126489706 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 126489706 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 360451750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 360451750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 486941456 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 486941456 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 486941456 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 486941456 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86716630 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86716630 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 168760435 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168760435 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168760435 # number of overall hits +system.cpu.dcache.overall_hits::total 168760435 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2061 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2061 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5219 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5219 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 7280 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7280 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7280 # number of overall misses +system.cpu.dcache.overall_misses::total 7280 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 137684956 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 137684956 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 400150250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 400150250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 537835206 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 537835206 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 537835206 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 537835206 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86715038 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86715038 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168769307 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168769307 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168769307 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168769307 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168767715 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168767715 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168767715 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168767715 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses @@ -454,14 +454,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61313.478429 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61313.478429 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68959.584848 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 68959.584848 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66795.810151 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66795.810151 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66795.810151 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66795.810151 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66804.927705 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66804.927705 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76671.824104 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76671.824104 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73878.462363 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73878.462363 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73878.462363 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73878.462363 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,14 +472,14 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks system.cpu.dcache.writebacks::total 1010 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2357 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2357 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2779 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2779 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2779 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2779 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 420 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 420 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2349 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2349 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2769 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2769 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2769 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2769 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1641 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1641 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses @@ -488,14 +488,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4511 system.cpu.dcache.demand_mshr_misses::total 4511 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 100259792 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 100259792 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 197855250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 197855250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298115042 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 298115042 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298115042 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 298115042 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109745542 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 109745542 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219964750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 219964750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329710292 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 329710292 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329710292 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 329710292 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -504,69 +504,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61096.765387 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61096.765387 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68939.111498 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68939.111498 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66086.242962 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66086.242962 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66086.242962 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66086.242962 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66877.234613 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66877.234613 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76642.770035 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76642.770035 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73090.288628 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73090.288628 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73090.288628 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73090.288628 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 36927 # number of replacements -system.cpu.icache.tags.tagsinuse 1924.993634 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 73270394 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 38864 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1885.302439 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 36897 # number of replacements +system.cpu.icache.tags.tagsinuse 1924.852609 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 73252005 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 38834 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1886.285343 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1924.993634 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939938 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939938 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.852609 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939869 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939869 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1487 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146657382 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146657382 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 73270394 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 73270394 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 73270394 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 73270394 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 73270394 # number of overall hits -system.cpu.icache.overall_hits::total 73270394 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 38865 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 38865 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 38865 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 38865 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 38865 # number of overall misses -system.cpu.icache.overall_misses::total 38865 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 703218247 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 703218247 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 703218247 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 703218247 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 703218247 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 703218247 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 73309259 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 73309259 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 73309259 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 73309259 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 73309259 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 73309259 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 146620514 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146620514 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 73252005 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 73252005 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 73252005 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 73252005 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 73252005 # number of overall hits +system.cpu.icache.overall_hits::total 73252005 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 38835 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 38835 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 38835 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 38835 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 38835 # number of overall misses +system.cpu.icache.overall_misses::total 38835 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 728456748 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 728456748 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 728456748 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 728456748 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 728456748 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 728456748 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 73290840 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 73290840 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 73290840 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 73290840 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 73290840 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 73290840 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000530 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000530 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000530 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000530 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000530 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000530 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18093.869729 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18093.869729 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18093.869729 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18093.869729 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18093.869729 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18093.869729 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18757.737814 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18757.737814 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18757.737814 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18757.737814 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18757.737814 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18757.737814 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -575,123 +575,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38865 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 38865 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 38865 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 38865 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 38865 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 38865 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 624088753 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 624088753 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 624088753 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 624088753 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 624088753 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 624088753 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38835 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 38835 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 38835 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 38835 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 38835 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 38835 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 668757252 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 668757252 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 668757252 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 668757252 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 668757252 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 668757252 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000530 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000530 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000530 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16057.860620 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16057.860620 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16057.860620 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16057.860620 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16057.860620 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16057.860620 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17220.477713 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17220.477713 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17220.477713 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17220.477713 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17220.477713 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17220.477713 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4198.559801 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 35809 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5647 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.341243 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 4197.194159 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 35781 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5646 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.337407 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 353.760842 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3166.451697 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 678.347263 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.010796 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096632 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.020702 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.128130 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5647 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 353.722028 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.177467 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 678.294664 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.010795 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096594 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.020700 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.128088 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5646 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1252 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4260 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172333 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 363605 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 363605 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 35439 # number of ReadReq hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4259 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172302 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 363364 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 363364 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 35411 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 291 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 35730 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 35702 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 1010 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 1010 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 35439 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 35411 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 307 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 35746 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 35439 # number of overall hits +system.cpu.l2cache.demand_hits::total 35718 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 35411 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 307 # number of overall hits -system.cpu.l2cache.overall_hits::total 35746 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3426 # number of ReadReq misses +system.cpu.l2cache.overall_hits::total 35718 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3424 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 1350 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4776 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4774 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 2854 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 2854 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3426 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 3424 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 4204 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7630 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3426 # number of overall misses +system.cpu.l2cache.demand_misses::total 7628 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3424 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses -system.cpu.l2cache.overall_misses::total 7630 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 230834250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 95696250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 326530500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 194789750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 194789750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 230834250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 290486000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 521320250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 230834250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 290486000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 521320250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 38865 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 7628 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 258115750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 105039500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 363155250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 216891750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 216891750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 258115750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 321931250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 580047000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 258115750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 321931250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 580047000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 38835 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1641 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 40506 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 40476 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 1010 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 1010 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 2870 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 2870 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 38865 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 38835 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4511 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 43376 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 38865 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 43346 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 38835 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4511 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 43376 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.088151 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 43346 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.088168 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.822669 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.117908 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.117946 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994425 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.994425 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088151 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088168 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.931944 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.175904 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088151 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.175979 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088168 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.931944 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.175904 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67377.189142 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70886.111111 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68369.032663 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68251.489138 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68251.489138 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67377.189142 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69097.526166 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68325.065531 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67377.189142 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69097.526166 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68325.065531 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.175979 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75384.272780 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77807.037037 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76069.386259 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75995.707779 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75995.707779 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75384.272780 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76577.366794 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76041.819612 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75384.272780 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76577.366794 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76041.819612 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -700,115 +700,113 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 44 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 42 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 44 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 42 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 45 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3423 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::total 44 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3422 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1308 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4731 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4730 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2854 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 2854 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3423 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3422 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 4162 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7585 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3423 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7584 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3422 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4162 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7585 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 187452250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 77027000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 264479250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 158825750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158825750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 187452250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 235852750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 423305000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 187452250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 235852750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 423305000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088074 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 7584 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 215130250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 85732250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 300862500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 181193250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 181193250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 215130250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 266925500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 482055750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 215130250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 266925500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 482055750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.797075 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116798 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116859 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088074 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.174866 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088074 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.174964 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.174866 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54762.562080 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58889.143731 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55903.455929 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55650.227751 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55650.227751 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54762.562080 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56668.128304 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55808.174028 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54762.562080 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56668.128304 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55808.174028 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.174964 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62866.817650 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65544.533639 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63607.293869 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63487.473721 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63487.473721 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62866.817650 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64133.950024 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63562.203323 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62866.817650 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64133.950024 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63562.203323 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 40506 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 40505 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 40476 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 40475 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77729 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77669 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10032 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 87761 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2487296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 87701 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2485376 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2840640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2838720 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 44386 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 44356 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 44386 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 44356 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 44386 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 23203000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 44356 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 23188000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 58996747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 58975248 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7500458 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7577708 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 4731 # Transaction distribution -system.membus.trans_dist::ReadResp 4731 # Transaction distribution +system.membus.trans_dist::ReadReq 4730 # Transaction distribution +system.membus.trans_dist::ReadResp 4730 # Transaction distribution system.membus.trans_dist::ReadExReq 2854 # Transaction distribution system.membus.trans_dist::ReadExResp 2854 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15170 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15170 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485440 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 485440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15168 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15168 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485376 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 485376 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7585 # Request fanout histogram +system.membus.snoop_fanout::samples 7584 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7585 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7584 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7585 # Request fanout histogram -system.membus.reqLayer0.occupancy 8964000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7584 # Request fanout histogram +system.membus.reqLayer0.occupancy 8969500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 71030500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40264250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 2e0077bb1..869d3326a 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.112624 # Number of seconds simulated -sim_ticks 112623767500 # Number of ticks simulated -final_tick 112623767500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.112554 # Number of seconds simulated +sim_ticks 112553814500 # Number of ticks simulated +final_tick 112553814500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123996 # Simulator instruction rate (inst/s) -host_op_rate 148871 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51146556 # Simulator tick rate (ticks/s) -host_mem_usage 325020 # Number of bytes of host memory used -host_seconds 2201.98 # Real time elapsed on the host +host_inst_rate 125235 # Simulator instruction rate (inst/s) +host_op_rate 150358 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51625290 # Simulator tick rate (ticks/s) +host_mem_usage 326264 # Number of bytes of host memory used +host_seconds 2180.21 # Real time elapsed on the host sim_insts 273037219 # Number of instructions simulated sim_ops 327811601 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 187072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 169856 # Number of bytes read from this memory -system.physmem.bytes_read::total 469120 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 187072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 187072 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2923 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 2654 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7330 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1661035 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 996166 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 1508172 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4165373 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1661035 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1661035 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1661035 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 996166 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 1508172 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4165373 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7330 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 187136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 114176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 167616 # Number of bytes read from this memory +system.physmem.bytes_read::total 468928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 187136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 187136 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2924 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1784 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2619 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7327 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1662636 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1014413 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1489208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4166256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1662636 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1662636 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1662636 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1014413 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1489208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4166256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7327 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7330 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7327 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 469120 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 468928 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 469120 # Total read bytes from the system interface side +system.physmem.bytesReadSys 468928 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -48,14 +48,14 @@ system.physmem.neitherReadNorWriteReqs 1 # Nu system.physmem.perBankRdBursts::0 589 # Per bank write bursts system.physmem.perBankRdBursts::1 789 # Per bank write bursts system.physmem.perBankRdBursts::2 601 # Per bank write bursts -system.physmem.perBankRdBursts::3 519 # Per bank write bursts +system.physmem.perBankRdBursts::3 520 # Per bank write bursts system.physmem.perBankRdBursts::4 444 # Per bank write bursts system.physmem.perBankRdBursts::5 346 # Per bank write bursts system.physmem.perBankRdBursts::6 153 # Per bank write bursts -system.physmem.perBankRdBursts::7 257 # Per bank write bursts +system.physmem.perBankRdBursts::7 255 # Per bank write bursts system.physmem.perBankRdBursts::8 219 # Per bank write bursts -system.physmem.perBankRdBursts::9 291 # Per bank write bursts -system.physmem.perBankRdBursts::10 316 # Per bank write bursts +system.physmem.perBankRdBursts::9 290 # Per bank write bursts +system.physmem.perBankRdBursts::10 315 # Per bank write bursts system.physmem.perBankRdBursts::11 411 # Per bank write bursts system.physmem.perBankRdBursts::12 547 # Per bank write bursts system.physmem.perBankRdBursts::13 678 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 112623613500 # Total gap between requests +system.physmem.totGap 112553656000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7330 # Read request sizes (log2) +system.physmem.readPktSize::6 7327 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,19 +94,19 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 176 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3994 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 473 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 246 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 203 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 178 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 150 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 184 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see @@ -190,26 +190,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1371 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 340.446389 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 197.878789 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 348.729899 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 488 35.59% 35.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 298 21.74% 57.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 137 9.99% 67.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 90 6.56% 73.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 49 3.57% 77.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 55 4.01% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 23 1.68% 83.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 26 1.90% 85.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 205 14.95% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1371 # Bytes accessed per row activation -system.physmem.totQLat 100359280 # Total ticks spent queuing -system.physmem.totMemAccLat 237796780 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 36650000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13691.58 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1397 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 334.064424 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 193.482672 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 348.087808 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 504 36.08% 36.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 315 22.55% 58.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 145 10.38% 69.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 78 5.58% 74.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 51 3.65% 78.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 45 3.22% 81.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 28 2.00% 83.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 21 1.50% 84.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 210 15.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1397 # Bytes accessed per row activation +system.physmem.totQLat 96387273 # Total ticks spent queuing +system.physmem.totMemAccLat 233768523 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36635000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13155.08 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32441.58 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31905.08 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.17 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.17 # Average system read bandwidth in MiByte/s @@ -218,51 +218,51 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.38 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5950 # Number of row buffer hits during reads +system.physmem.readRowHits 5921 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.17 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.81 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 15364749.45 # Average gap between requests -system.physmem.pageHitRate 81.17 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4906440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2677125 # Energy for precharge commands per rank (pJ) +system.physmem.avgGap 15361492.56 # Average gap between requests +system.physmem.pageHitRate 80.81 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4883760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2664750 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 28688400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 7355811840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3232257390 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 64737034500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 75361375695 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.161673 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 107692958200 # Time in different power states -system.physmem_0.memoryStateTime::REF 3760640000 # Time in different power states +system.physmem_0.refreshEnergy 7351234800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3253381020 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 64676459250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 75317311980 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.186805 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 107592163396 # Time in different power states +system.physmem_0.memoryStateTime::REF 3758300000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1167342300 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1200480604 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5435640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2965875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 28165800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 5654880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3085500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 28158000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 7355811840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3291484950 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 64685080500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 75368944605 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.228880 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 107605030400 # Time in different power states -system.physmem_1.memoryStateTime::REF 3760640000 # Time in different power states +system.physmem_1.refreshEnergy 7351234800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3298234320 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 64637123250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 75323490750 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.241613 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 107525247142 # Time in different power states +system.physmem_1.memoryStateTime::REF 3758300000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1254923350 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1266984612 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 37762202 # Number of BP lookups -system.cpu.branchPred.condPredicted 20178978 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1746186 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18669843 # Number of BTB lookups -system.cpu.branchPred.BTBHits 17301885 # Number of BTB hits +system.cpu.branchPred.lookups 37745757 # Number of BP lookups +system.cpu.branchPred.condPredicted 20165080 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1746215 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18666199 # Number of BTB lookups +system.cpu.branchPred.BTBHits 17299874 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.672900 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7228775 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3814 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.680218 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7225607 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,234 +381,234 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 225247536 # number of cpu cycles simulated +system.cpu.numCycles 225107630 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12260997 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 334142837 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37762202 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24530660 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 210950106 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3511423 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1112 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 2317 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 89109626 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 21670 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 224970243 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.801560 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.228501 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12251626 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 334050460 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37745757 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24525481 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 210773788 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3510701 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1259 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 2425 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 89095014 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 21830 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 224784448 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.802641 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.228554 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 51235855 22.77% 22.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42807602 19.03% 41.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 30290628 13.46% 55.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 100636158 44.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 51100209 22.73% 22.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42897495 19.08% 41.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 30052167 13.37% 55.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 100734577 44.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 224970243 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.167648 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.483447 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 27756041 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64007493 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108311444 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 23274289 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1620976 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6880269 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 135184 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 363488172 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 6272061 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1620976 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 45214868 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13194135 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 339970 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 113472539 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51127755 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 355731319 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 2913591 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 6682784 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 150888 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7653578 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 21157029 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 7934488 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 403383639 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2533813915 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 350195205 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 194873173 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 224784448 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.167679 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.483959 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 27670459 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63847459 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108576617 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 23069322 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1620591 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6880031 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 135198 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 363530052 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6167703 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1620591 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44985233 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 17899875 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 341878 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 113387886 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 46548985 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 355747640 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 2899285 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 6598470 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 195112 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7751940 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 21223571 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 2892429 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 403401871 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2533892950 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 350207607 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 194891234 # Number of floating rename lookups system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31153588 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 17016 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 17052 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 55396743 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 92428788 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 88464605 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1673696 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1845347 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 353205084 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28025 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 346266425 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 2344670 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24805703 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 73566871 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 5905 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 224970243 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.539165 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.101848 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 31171820 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 17015 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 17024 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 55320329 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 92416671 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 88482299 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1659115 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1844729 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 353235129 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 28024 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 346404668 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 2300304 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24831082 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 73599170 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 5904 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 224784448 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.541053 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.099675 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 40745402 18.11% 18.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 78348887 34.83% 52.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 60751762 27.00% 79.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34737500 15.44% 95.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9740629 4.33% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 637380 0.28% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8683 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 40431348 17.99% 17.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 78272117 34.82% 52.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 61035980 27.15% 79.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34788778 15.48% 95.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9595638 4.27% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 651817 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8770 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 224970243 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 224784448 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9315798 7.51% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7337 0.01% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 233455 0.19% 7.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 152510 0.12% 7.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 103371 0.08% 7.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 37180 0.03% 7.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 820015 0.66% 8.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 318375 0.26% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 687813 0.55% 9.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 53407928 43.05% 52.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 58972553 47.54% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9471276 7.62% 7.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7330 0.01% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 257049 0.21% 7.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 126990 0.10% 7.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 92940 0.07% 8.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 68000 0.05% 8.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 719474 0.58% 8.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 316340 0.25% 8.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 682824 0.55% 9.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 53604156 43.13% 52.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 58946138 47.43% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 110648263 31.95% 31.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148166 0.62% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6796965 1.96% 34.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8667386 2.50% 37.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3331882 0.96% 38.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1592439 0.46% 38.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20937021 6.05% 44.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7180792 2.07% 46.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147105 2.06% 48.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 91783076 26.51% 75.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 85858044 24.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 110656025 31.94% 31.94% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148357 0.62% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6798490 1.96% 34.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8668315 2.50% 37.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3332477 0.96% 37.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592461 0.46% 38.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20930112 6.04% 44.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7182294 2.07% 46.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7148952 2.06% 48.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 91886799 26.53% 75.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 85885100 24.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 346266425 # Type of FU issued -system.cpu.iq.rate 1.537271 # Inst issue rate -system.cpu.iq.fu_busy_cnt 124056335 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.358268 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 756639732 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 251256110 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 223226406 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 287264366 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 126793395 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 117417412 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 302952760 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 167370000 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5033832 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 346404668 # Type of FU issued +system.cpu.iq.rate 1.538840 # Inst issue rate +system.cpu.iq.fu_busy_cnt 124292517 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.358807 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 756686876 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 251306416 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 223263085 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 287499729 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 126798006 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 117424806 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 303164482 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 167532703 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5066223 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6696513 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13646 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 10697 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6088988 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6684396 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13685 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 10191 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6106682 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 151171 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 488903 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 154303 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 567640 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1620976 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2121777 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 321028 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 353233977 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 1620591 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2121620 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 330440 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 353264020 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 92428788 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 88464605 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 16992 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 8078 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 328775 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 10697 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1220281 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 438299 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1658580 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 342303629 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 90585110 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3962796 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 92416671 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 88482299 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 16991 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 8046 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 336925 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 10191 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1220622 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 439103 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1659725 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 342414286 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 90666955 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3990382 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 868 # number of nop insts executed -system.cpu.iew.exec_refs 175167602 # number of memory reference insts executed -system.cpu.iew.exec_branches 31752029 # Number of branches executed -system.cpu.iew.exec_stores 84582492 # Number of stores executed -system.cpu.iew.exec_rate 1.519678 # Inst execution rate -system.cpu.iew.wb_sent 340903564 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 340643818 # cumulative count of insts written-back -system.cpu.iew.wb_producers 153542130 # num instructions producing a value -system.cpu.iew.wb_consumers 265815285 # num instructions consuming a value +system.cpu.iew.exec_nop 867 # number of nop insts executed +system.cpu.iew.exec_refs 175255989 # number of memory reference insts executed +system.cpu.iew.exec_branches 31752931 # Number of branches executed +system.cpu.iew.exec_stores 84589034 # Number of stores executed +system.cpu.iew.exec_rate 1.521114 # Inst execution rate +system.cpu.iew.wb_sent 340946352 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 340687891 # cumulative count of insts written-back +system.cpu.iew.wb_producers 153731206 # num instructions producing a value +system.cpu.iew.wb_consumers 266896125 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.512309 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.577627 # average fanout of values written-back +system.cpu.iew.wb_rate 1.513444 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.575996 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 22999072 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23077118 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1611451 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 221242338 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.481688 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.053337 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1611456 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 221059297 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.482915 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.052167 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 87860442 39.71% 39.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 69868164 31.58% 71.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 20927833 9.46% 80.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13474111 6.09% 86.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8800250 3.98% 90.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4584845 2.07% 92.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2913190 1.32% 94.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2446339 1.11% 95.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10367164 4.69% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 87356112 39.52% 39.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 70369552 31.83% 71.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 20804455 9.41% 80.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13442204 6.08% 86.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8808979 3.98% 90.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4514912 2.04% 92.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2991653 1.35% 94.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2424695 1.10% 95.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10346735 4.68% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 221242338 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 221059297 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037831 # Number of instructions committed system.cpu.commit.committedOps 327812213 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -654,387 +654,387 @@ system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 327812213 # Class of committed instruction -system.cpu.commit.bw_lim_events 10367164 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 10346735 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 561683936 # The number of ROB reads -system.cpu.rob.rob_writes 705354391 # The number of ROB writes -system.cpu.timesIdled 50923 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 277293 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 561599370 # The number of ROB reads +system.cpu.rob.rob_writes 705507733 # The number of ROB writes +system.cpu.timesIdled 50679 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 323182 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273037219 # Number of Instructions Simulated system.cpu.committedOps 327811601 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.824970 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.824970 # CPI: Total CPI of All Threads -system.cpu.ipc 1.212165 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.212165 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 331186150 # number of integer regfile reads -system.cpu.int_regfile_writes 136908474 # number of integer regfile writes -system.cpu.fp_regfile_reads 187099872 # number of floating regfile reads -system.cpu.fp_regfile_writes 132166295 # number of floating regfile writes -system.cpu.cc_regfile_reads 1296656595 # number of cc regfile reads -system.cpu.cc_regfile_writes 80246016 # number of cc regfile writes -system.cpu.misc_regfile_reads 1182266137 # number of misc regfile reads +system.cpu.cpi 0.824458 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.824458 # CPI: Total CPI of All Threads +system.cpu.ipc 1.212919 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.212919 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 331300708 # number of integer regfile reads +system.cpu.int_regfile_writes 136940215 # number of integer regfile writes +system.cpu.fp_regfile_reads 187107289 # number of floating regfile reads +system.cpu.fp_regfile_writes 132177847 # number of floating regfile writes +system.cpu.cc_regfile_reads 1297030245 # number of cc regfile reads +system.cpu.cc_regfile_writes 80242169 # number of cc regfile writes +system.cpu.misc_regfile_reads 1182847920 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1533739 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.852624 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 163803903 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1534251 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 106.764736 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 77087500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.852624 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999712 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999712 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1533856 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.843197 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 163689216 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1534368 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 106.681849 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 83394000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.843197 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999694 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999694 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336684823 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336684823 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 82726313 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 82726313 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80985354 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80985354 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 70429 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 70429 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10910 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10910 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 336633502 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336633502 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 82631348 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 82631348 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80965582 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80965582 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 70480 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 70480 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 163711667 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 163711667 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 163782096 # number of overall hits -system.cpu.dcache.overall_hits::total 163782096 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2704016 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2704016 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1067345 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1067345 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 19 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 19 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 163596930 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 163596930 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 163667410 # number of overall hits +system.cpu.dcache.overall_hits::total 163667410 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2773213 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2773213 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1087117 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1087117 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3771361 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3771361 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3771380 # number of overall misses -system.cpu.dcache.overall_misses::total 3771380 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 21429430210 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 21429430210 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8382362067 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8382362067 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 174750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 174750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29811792277 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29811792277 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29811792277 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29811792277 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 85430329 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 85430329 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3860330 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3860330 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3860348 # number of overall misses +system.cpu.dcache.overall_misses::total 3860348 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 22349106216 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 22349106216 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8902471046 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8902471046 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 189750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31251577262 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31251577262 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31251577262 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31251577262 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 85404561 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 85404561 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 70448 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 70448 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10915 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10915 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 70498 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 70498 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 167483028 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 167483028 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 167553476 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 167553476 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.031652 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.031652 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013008 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013008 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000270 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.000270 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 167457260 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 167457260 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 167527758 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 167527758 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032471 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032471 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013249 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013249 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000255 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000255 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.022518 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.022518 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.022509 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.022509 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7925.038243 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 7925.038243 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7853.470122 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7853.470122 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 34950 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 34950 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 7904.783519 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 7904.783519 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 7904.743695 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 7904.743695 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.023053 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023053 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023043 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023043 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8058.921625 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 8058.921625 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8189.064329 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8189.064329 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37950 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37950 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 8095.571431 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 8095.571431 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 8095.533683 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 8095.533683 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 768686 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 918314 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 111802 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 117385 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 6.875423 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7.823095 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 966281 # number of writebacks -system.cpu.dcache.writebacks::total 966281 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1390263 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1390263 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 846856 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 846856 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 966341 # number of writebacks +system.cpu.dcache.writebacks::total 966341 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1459499 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1459499 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 866472 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 866472 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2237119 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2237119 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2237119 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2237119 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313753 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1313753 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220489 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 220489 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 2325971 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2325971 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2325971 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2325971 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313714 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1313714 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220645 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 220645 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1534242 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1534242 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1534253 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1534253 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9313835285 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9313835285 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1599508327 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1599508327 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 613250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 613250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10913343612 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10913343612 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10913956862 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10913956862 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015378 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015378 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002687 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002687 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1534359 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1534359 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1534370 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1534370 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9969290033 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9969290033 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1717345064 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1717345064 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1161750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1161750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11686635097 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11686635097 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11687796847 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11687796847 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015382 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015382 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002689 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002689 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000156 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000156 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009161 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.009161 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009157 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.009157 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7089.487358 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7089.487358 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7254.367914 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7254.367914 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 55750 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 55750 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7113.182674 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 7113.182674 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7113.531381 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 7113.531381 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009163 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.009163 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009159 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.009159 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7588.630427 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7588.630427 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7783.294722 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7783.294722 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 105613.636364 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 105613.636364 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7616.623683 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 7616.623683 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7617.326230 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 7617.326230 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 715275 # number of replacements -system.cpu.icache.tags.tagsinuse 511.840362 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 88389408 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 715787 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 123.485629 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 315060000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.840362 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999688 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999688 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 715719 # number of replacements +system.cpu.icache.tags.tagsinuse 511.828705 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 88373879 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 716231 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 123.387397 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 326261250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.828705 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999665 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999665 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 245 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 68 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 244 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 178935006 # Number of tag accesses -system.cpu.icache.tags.data_accesses 178935006 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 88389408 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 88389408 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 88389408 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 88389408 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 88389408 # number of overall hits -system.cpu.icache.overall_hits::total 88389408 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 720201 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 720201 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 720201 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 720201 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 720201 # number of overall misses -system.cpu.icache.overall_misses::total 720201 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 5943843584 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 5943843584 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 5943843584 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 5943843584 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 5943843584 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 5943843584 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 89109609 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 89109609 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 89109609 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 89109609 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 89109609 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 89109609 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008082 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008082 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008082 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008082 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008082 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008082 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8253.034339 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8253.034339 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8253.034339 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8253.034339 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8253.034339 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8253.034339 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 51882 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 52 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1935 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 178906226 # Number of tag accesses +system.cpu.icache.tags.data_accesses 178906226 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 88373879 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 88373879 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 88373879 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 88373879 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 88373879 # number of overall hits +system.cpu.icache.overall_hits::total 88373879 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 721118 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 721118 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 721118 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 721118 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 721118 # number of overall misses +system.cpu.icache.overall_misses::total 721118 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 5972962690 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 5972962690 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 5972962690 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 5972962690 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 5972962690 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 5972962690 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 89094997 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 89094997 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 89094997 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 89094997 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 89094997 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 89094997 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008094 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008094 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008094 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008094 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008094 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008094 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8282.919980 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8282.919980 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8282.919980 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8282.919980 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8282.919980 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8282.919980 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 60262 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 95 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2026 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 26.812403 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 17.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 29.744324 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 31.666667 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4413 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4413 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4413 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4413 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4413 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4413 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 715788 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 715788 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 715788 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 715788 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 715788 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 715788 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 4812391061 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 4812391061 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 4812391061 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 4812391061 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 4812391061 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 4812391061 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008033 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008033 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008033 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.008033 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008033 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.008033 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6723.207236 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6723.207236 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6723.207236 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 6723.207236 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6723.207236 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 6723.207236 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4886 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4886 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4886 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4886 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4886 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4886 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 716232 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 716232 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 716232 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 716232 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 716232 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 716232 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5192936459 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 5192936459 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5192936459 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 5192936459 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5192936459 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 5192936459 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008039 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.008039 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.008039 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7250.355275 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7250.355275 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7250.355275 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7250.355275 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7250.355275 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7250.355275 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 406270 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 406521 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 191 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 404550 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 404804 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 188 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 28111 # number of prefetches not generated due to page crossing +system.cpu.l2cache.prefetcher.pfSpanPage 28140 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 5993.755359 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2805980 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 7304 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 384.170318 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 5993.813794 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2806615 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 7301 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 384.415149 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2575.357550 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2680.182450 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 614.569855 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 123.645504 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.157187 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.163585 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.037510 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.007547 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.365830 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 515 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 6789 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 2575.149913 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2681.614006 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 610.589138 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 126.460737 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.157175 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.163673 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.037267 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.007719 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.365833 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 517 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 6784 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::2 344 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 133 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 135 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 775 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5746 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.031433 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.414368 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 51674481 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 51674481 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 711950 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1312705 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2024655 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 966281 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 966281 # number of Writeback hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 126 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5743 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.031555 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.414062 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 51684538 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 51684538 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 712391 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1312672 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2025063 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 966341 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 966341 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 219662 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 219662 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 711950 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1532367 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2244317 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 711950 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1532367 # number of overall hits -system.cpu.l2cache.overall_hits::total 2244317 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2934 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1059 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 3993 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 219831 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 219831 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 712391 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1532503 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2244894 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 712391 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1532503 # number of overall hits +system.cpu.l2cache.overall_hits::total 2244894 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2935 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1053 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3988 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 825 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 825 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2934 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1884 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 4818 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2934 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1884 # number of overall misses -system.cpu.l2cache.overall_misses::total 4818 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 179619250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70145000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 249764250 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 15499 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 15499 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 50824468 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 50824468 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 179619250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 120969468 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 300588718 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 179619250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 120969468 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 300588718 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 714884 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1313764 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2028648 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 966281 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 966281 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 812 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 812 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2935 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1865 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 4800 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2935 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1865 # number of overall misses +system.cpu.l2cache.overall_misses::total 4800 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 200800474 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 76846248 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 277646722 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23499 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 23499 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 57691250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 57691250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 200800474 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 134537498 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 335337972 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 200800474 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 134537498 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 335337972 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 715326 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1313725 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2029051 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 966341 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 966341 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 220487 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 220487 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 714884 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1534251 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2249135 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 714884 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1534251 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2249135 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.004104 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000806 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001968 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 220643 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 220643 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 715326 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1534368 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2249694 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 715326 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1534368 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2249694 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.004103 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000802 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001965 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003742 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.003742 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004104 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.001228 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.002142 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004104 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.001228 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.002142 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61219.921609 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 66237.016053 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 62550.525920 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15499 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15499 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 61605.415758 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 61605.415758 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61219.921609 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64208.847134 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 62388.691988 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61219.921609 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64208.847134 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 62388.691988 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003680 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.003680 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004103 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.001215 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.002134 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004103 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.001215 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.002134 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68415.834412 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72978.393162 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69620.542126 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 23499 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 23499 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71048.337438 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71048.337438 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68415.834412 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72138.068633 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69862.077500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68415.834412 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72138.068633 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69862.077500 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1044,141 +1044,139 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 33 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 44 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 98 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 98 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 34 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 47 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 47 # number of ReadExReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 131 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 142 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 81 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 131 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 142 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2923 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1026 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3949 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 30530 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 30530 # number of HardPFReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::cpu.data 81 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 92 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2924 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1019 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3943 # number of ReadReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 30395 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 30395 # number of HardPFReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 727 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 727 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2923 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1753 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 4676 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2923 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1753 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 30530 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 35206 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 153898250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 59960500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 213858750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 204942291 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 204942291 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6001 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6001 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 41351500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 41351500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 153898250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101312000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 255210250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 153898250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101312000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 204942291 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 460152541 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004089 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000781 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001947 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 765 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 765 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2924 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1784 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 4708 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2924 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1784 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 30395 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 35103 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 175338026 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 66096002 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 241434028 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 176500042 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 176500042 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14001 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14001 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49863251 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49863251 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 175338026 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115959253 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 291297279 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 175338026 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115959253 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 176500042 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 467797321 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004088 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000776 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001943 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003297 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003297 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004089 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001143 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.002079 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004089 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001143 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003467 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003467 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004088 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001163 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.002093 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004088 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001163 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.015653 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52650.786863 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58441.033138 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54155.165865 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6712.816607 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 6712.816607 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56879.642366 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56879.642366 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52650.786863 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57793.496863 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54578.753208 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52650.786863 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57793.496863 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6712.816607 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13070.287479 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.015603 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59965.125171 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64863.593719 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61231.049455 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5806.877513 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 5806.877513 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65180.720261 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65180.720261 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59965.125171 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64999.581278 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61872.829014 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59965.125171 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64999.581278 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5806.877513 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13326.419993 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2029552 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2029552 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 966281 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 32098 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2029957 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2029957 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 966341 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 31800 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 220487 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 220487 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1430672 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4034787 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5465459 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45752576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160034048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205786624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 33002 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3248420 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.009881 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.098911 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 220643 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 220643 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1431558 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4035081 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5466639 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45780864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160045376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205826240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 32706 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3248743 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.009788 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.098451 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3216322 99.01% 99.01% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 32098 0.99% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3216943 99.02% 99.02% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 31800 0.98% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3248420 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2574443497 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3248743 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2574812500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1074521893 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1075185997 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2301598998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2301792968 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 6603 # Transaction distribution -system.membus.trans_dist::ReadResp 6603 # Transaction distribution +system.membus.trans_dist::ReadReq 6562 # Transaction distribution +system.membus.trans_dist::ReadResp 6562 # Transaction distribution system.membus.trans_dist::UpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 727 # Transaction distribution -system.membus.trans_dist::ReadExResp 727 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14662 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14662 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 469120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 469120 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 765 # Transaction distribution +system.membus.trans_dist::ReadExResp 765 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14656 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14656 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 468928 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 468928 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7331 # Request fanout histogram +system.membus.snoop_fanout::samples 7328 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7331 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7328 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7331 # Request fanout histogram -system.membus.reqLayer0.occupancy 9338317 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7328 # Request fanout histogram +system.membus.reqLayer0.occupancy 9247379 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 68128868 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 38369962 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index 8e74d72ee..833e406c9 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.201717 # Nu sim_ticks 201717313500 # Number of ticks simulated final_tick 201717313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1117455 # Simulator instruction rate (inst/s) -host_op_rate 1341629 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 825564009 # Simulator tick rate (ticks/s) -host_mem_usage 308812 # Number of bytes of host memory used -host_seconds 244.34 # Real time elapsed on the host +host_inst_rate 1235958 # Simulator instruction rate (inst/s) +host_op_rate 1483905 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 913112758 # Simulator tick rate (ticks/s) +host_mem_usage 308700 # Number of bytes of host memory used +host_seconds 220.91 # Real time elapsed on the host sim_insts 273037594 # Number of instructions simulated sim_ops 327811949 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979 system.membus.pkt_size::total 2275398071 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 517024351 # Request fanout histogram -system.membus.snoop_fanout::mean 4.674359 # Request fanout histogram +system.membus.snoop_fanout::mean 2.674359 # Request fanout histogram system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 168364078 32.56% 32.56% # Request fanout histogram -system.membus.snoop_fanout::5 348660273 67.44% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 168364078 32.56% 32.56% # Request fanout histogram +system.membus.snoop_fanout::3 348660273 67.44% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 517024351 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index c39fe9424..426aa68c6 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.517235 # Number of seconds simulated -sim_ticks 517235411000 # Number of ticks simulated -final_tick 517235411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 517235404500 # Number of ticks simulated +final_tick 517235404500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 761441 # Simulator instruction rate (inst/s) -host_op_rate 914138 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1444030997 # Simulator tick rate (ticks/s) -host_mem_usage 318052 # Number of bytes of host memory used -host_seconds 358.19 # Real time elapsed on the host +host_inst_rate 693666 # Simulator instruction rate (inst/s) +host_op_rate 832772 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1315500911 # Simulator tick rate (ticks/s) +host_mem_usage 318184 # Number of bytes of host memory used +host_seconds 393.19 # Real time elapsed on the host sim_insts 272739285 # Number of instructions simulated sim_ops 327433743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 1034470822 # number of cpu cycles simulated +system.cpu.numCycles 1034470809 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 272739285 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 168107847 # nu system.cpu.num_load_insts 85732248 # Number of load instructions system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1034470821.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1034470808.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 30563502 # Number of branches fetched @@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812213 # Class of executed instruction system.cpu.dcache.tags.replacements 1332 # number of replacements -system.cpu.dcache.tags.tagsinuse 3078.445016 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3078.445039 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445016 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445039 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id @@ -251,12 +251,12 @@ system.cpu.dcache.overall_misses::cpu.data 4479 # system.cpu.dcache.overall_misses::total 4479 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 78354000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 78354000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 157425500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 157425500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 235779500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 235779500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 235779500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 235779500 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 157422500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 157422500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 235776500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 235776500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 235776500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 235776500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) @@ -283,12 +283,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52676.385165 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52641.102925 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54812.848189 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54812.848189 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52675.714924 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52675.714924 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52640.433132 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52640.433132 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -315,16 +315,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4475 system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75108000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75108000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151681500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 151681500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 159000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 159000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226789500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 226789500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226948500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 226948500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75909500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75909500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 153114500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 153114500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 160500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 160500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 229024000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 229024000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 229184500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 229184500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -335,24 +335,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47354.647536 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47354.647536 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53312.848189 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53312.848189 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51178.547486 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51178.547486 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51180.102724 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51180.102724 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13796 # number of replacements -system.cpu.icache.tags.tagsinuse 1766.007645 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1766.007658 # Cycle average of tags in use system.cpu.icache.tags.total_refs 348644749 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 22344.725309 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007645 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007658 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id @@ -376,12 +376,12 @@ system.cpu.icache.demand_misses::cpu.inst 15603 # n system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses system.cpu.icache.overall_misses::total 15603 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 312527500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 312527500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 312527500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 312527500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 312527500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 312527500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 312524000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 312524000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 312524000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 312524000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 312524000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 312524000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 348660352 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 348660352 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 348660352 # number of demand (read+write) accesses @@ -394,12 +394,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.962187 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20029.962187 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20029.962187 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20029.962187 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.737871 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20029.737871 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.737871 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20029.737871 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.737871 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20029.737871 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -414,34 +414,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603 system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281321500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281321500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281321500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281321500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281321500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281321500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 289119500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 289119500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 289119500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 289119500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 289119500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 289119500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18029.962187 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18029.962187 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18529.737871 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18529.737871 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18529.737871 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18529.737871 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18529.737871 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18529.737871 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3487.764987 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3487.765017 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 341.623056 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.427143 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 737.714788 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 341.623060 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.427163 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 737.714793 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010426 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy @@ -479,17 +479,17 @@ system.cpu.l2cache.demand_misses::total 6832 # nu system.cpu.l2cache.overall_misses::cpu.inst 2609 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4223 # number of overall misses system.cpu.l2cache.overall_misses::total 6832 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135778500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71271000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 207049500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148649500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 148649500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 135778500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 219920500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 355699000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 135778500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 219920500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 355699000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 137079500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71954500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 209034000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 150074500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 150074500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 137079500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 222029000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 359108500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 137079500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 222029000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 359108500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses) @@ -514,17 +514,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.340222 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167211 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52042.353392 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52136.795903 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52074.823944 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52048.144258 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52048.144258 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52063.670960 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52063.670960 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52541.011882 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52636.795903 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52573.943662 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52547.093838 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52547.093838 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52541.011882 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52576.130713 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52562.719555 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52541.011882 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52576.130713 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52562.719555 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -544,17 +544,17 @@ system.cpu.l2cache.demand_mshr_misses::total 6832 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104365000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159045000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114243000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114243000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104365000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168923000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 273288000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104365000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168923000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 273288000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 105665500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55363500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 161029000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115668000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115668000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 105665500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 171031500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 276697000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 105665500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 171031500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 276697000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231042 # mshr miss rate for ReadReq accesses @@ -566,17 +566,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.916443 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.257545 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.050420 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.050420 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500.383289 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.251509 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500.383289 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.146370 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500.383289 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.146370 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution @@ -591,19 +591,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 21079 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 21079 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 21079 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 21079 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) @@ -630,9 +628,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 6833 # Request fanout histogram -system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 7260500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 34587500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |