all: Update stats for memory per master and total fix.

22 files changed, 418 insertions, 145 deletions

diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
index ad08e6373..673c743ff 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
@@ -176,9 +176,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -209,9 +208,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
index 56d057ebd..051061431 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:36:31
-gem5 started May  8 2012 15:36:55
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:50:11
+gem5 started Jun  4 2012 13:42:58
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
index 28e031d9f..06e2fa444 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
@@ -4,22 +4,29 @@ sim_seconds                                  0.141175                       # Nu
 sim_ticks                                141175129500                       # Number of ticks simulated
 final_tick                               141175129500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  60144                       # Simulator instruction rate (inst/s)
-host_op_rate                                    60144                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               21298240                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 221000                       # Number of bytes of host memory used
-host_seconds                                  6628.49                       # Real time elapsed on the host
+host_inst_rate                                 110841                       # Simulator instruction rate (inst/s)
+host_op_rate                                   110841                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               39251086                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 221340                       # Number of bytes of host memory used
+host_seconds                                  3596.72                       # Real time elapsed on the host
 sim_insts                                   398664595                       # Number of instructions simulated
 sim_ops                                     398664595                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                      468992                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                 214592                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                         7328                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                        3322058                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                   1520041                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                       3322058                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst            214592                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            254400                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               468992                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       214592                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          214592                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3353                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               3975                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7328                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1520041                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1802017                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3322058                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1520041                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1520041                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1520041                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1802017                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3322058                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -155,11 +162,17 @@ system.cpu.icache.demand_accesses::total     49111849                       # nu
 system.cpu.icache.overall_accesses::cpu.inst     49111849                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total     49111849                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000089                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000089                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000089                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000089                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000089                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000089                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48928.995434                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 48928.995434                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 48928.995434                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 48928.995434                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 48928.995434                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 48928.995434                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets        45000                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -187,11 +200,17 @@ system.cpu.icache.demand_mshr_miss_latency::total    185222000
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst    185222000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total    185222000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000079                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000079                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000079                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000079                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000079                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000079                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47480.645988                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47480.645988                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47480.645988                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 47480.645988                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47480.645988                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 47480.645988                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                    764                       # number of replacements
 system.cpu.dcache.tagsinuse               3284.843893                       # Cycle average of tags in use
@@ -235,13 +254,21 @@ system.cpu.dcache.demand_accesses::total    168275218                       # nu
 system.cpu.dcache.overall_accesses::cpu.data    168275218                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total    168275218                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000013                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000013                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000164                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000164                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.000079                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000079                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000079                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000079                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52139.705882                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 52139.705882                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52061.154965                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 52061.154965                       # average WriteReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 52068.406365                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 52068.406365                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 52068.406365                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 52068.406365                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets     82410500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -277,13 +304,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total    215717000
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data    215717000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total    215717000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000010                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000044                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48610.526316                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48610.526316                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52947.220487                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52947.220487                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51954.961464                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 51954.961464                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51954.961464                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 51954.961464                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                    13                       # number of replacements
 system.cpu.l2cache.tagsinuse              3896.685167                       # Cycle average of tags in use
@@ -348,18 +383,26 @@ system.cpu.l2cache.overall_accesses::cpu.data         4152
 system.cpu.l2cache.overall_accesses::total         8053                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.859523                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.876452                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.862830                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.981279                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.981279                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.859523                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.957370                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.909971                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.859523                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.957370                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.909971                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52322.696093                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52557.228916                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52369.232608                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52454.848967                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52454.848967                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52322.696093                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52476.226415                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52405.977074                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52322.696093                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52476.226415                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52405.977074                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -392,18 +435,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    160275000
 system.cpu.l2cache.overall_mshr_miss_latency::total    294866000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.859523                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.876452                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.862830                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.981279                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.981279                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.859523                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.957370                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.909971                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.859523                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.957370                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.909971                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.471220                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40382.530120                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40188.501076                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40304.451510                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40304.451510                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.471220                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40320.754717                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40238.264192                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.471220                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40320.754717                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40238.264192                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
index bf1407a6b..7162e6c66 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -507,9 +506,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
index 54524760f..0c5d1935a 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:36:31
-gem5 started May  8 2012 15:37:12
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:50:11
+gem5 started Jun  4 2012 13:46:44
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index 891e3f52e..55fb5b70f 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,22 +4,29 @@ sim_seconds                                  0.080257                       # Nu
 sim_ticks                                 80257421500                       # Number of ticks simulated
 final_tick                                80257421500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  93963                       # Simulator instruction rate (inst/s)
-host_op_rate                                    93963                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               20079187                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 221872                       # Number of bytes of host memory used
-host_seconds                                  3997.05                       # Real time elapsed on the host
+host_inst_rate                                 183656                       # Simulator instruction rate (inst/s)
+host_op_rate                                   183656                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               39245952                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222148                       # Number of bytes of host memory used
+host_seconds                                  2044.99                       # Real time elapsed on the host
 sim_insts                                   375574808                       # Number of instructions simulated
 sim_ops                                     375574808                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                      478528                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                 222720                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                         7477                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                        5962414                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                   2775070                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                       5962414                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst            222720                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            255808                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               478528                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       222720                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          222720                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3480                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               3997                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7477                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              2775070                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3187344                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 5962414                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         2775070                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            2775070                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2775070                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3187344                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                5962414                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -357,11 +364,17 @@ system.cpu.icache.demand_accesses::total     52487109                       # nu
 system.cpu.icache.overall_accesses::cpu.inst     52487109                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total     52487109                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000108                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000108                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000108                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000108                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000108                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000108                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31012.199434                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 31012.199434                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 31012.199434                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 31012.199434                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 31012.199434                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 31012.199434                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -389,11 +402,17 @@ system.cpu.icache.demand_mshr_miss_latency::total    125153000
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst    125153000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total    125153000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000079                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000079                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000079                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000079                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000079                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000079                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30055.955812                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 30055.955812                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30055.955812                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 30055.955812                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30055.955812                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 30055.955812                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                    804                       # number of replacements
 system.cpu.dcache.tagsinuse               3297.800145                       # Cycle average of tags in use
@@ -441,13 +460,21 @@ system.cpu.dcache.demand_accesses::total    161830750                       # nu
 system.cpu.dcache.overall_accesses::cpu.data    161830750                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total    161830750                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000019                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000019                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000265                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000265                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.000131                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000131                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000131                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000131                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33167.850799                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 33167.850799                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29072.241300                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 29072.241300                       # average WriteReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 29398.537736                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 29398.537736                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 29398.537736                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 29398.537736                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs         2500                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 1                       # number of cycles access was blocked
@@ -483,13 +510,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total    144878500
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data    144878500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total    144878500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000011                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000011                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000044                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000026                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000026                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000026                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000026                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31659.521436                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31659.521436                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35329.169269                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35329.169269                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34453.864447                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 34453.864447                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34453.864447                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 34453.864447                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                    11                       # number of replacements
 system.cpu.l2cache.tagsinuse              4039.301940                       # Cycle average of tags in use
@@ -554,18 +589,26 @@ system.cpu.l2cache.overall_accesses::cpu.data         4205
 system.cpu.l2cache.overall_accesses::total         8369                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.835735                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.867398                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.841881                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.976577                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.976577                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.835735                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.950535                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.893416                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.835735                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.950535                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.893416                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34383.045977                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34584.482759                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34423.333333                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34647.105852                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34647.105852                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34383.045977                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34633.475106                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34516.918550                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34383.045977                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34633.475106                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34516.918550                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -598,18 +641,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    125810000
 system.cpu.l2cache.overall_mshr_miss_latency::total    234231000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.835735                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.867398                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.841881                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.976577                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.976577                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.835735                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.950535                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.893416                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.835735                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.950535                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.893416                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31155.459770                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31425.287356                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31209.425287                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31490.246242                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31490.246242                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31155.459770                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31476.107080                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31326.869065                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31155.459770                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31476.107080                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31326.869065                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
index dc447cd7b..4442b5ed2 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
@@ -94,9 +94,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr
index 860580eeb..28eb1122e 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr
@@ -1,3 +1,4 @@
+warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout
index 57f8a5318..ba8d40ed9 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:36:31
-gem5 started May  8 2012 15:37:06
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:50:11
+gem5 started Jun  4 2012 14:23:04
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
index 290084525..695830448 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,23 +4,35 @@ sim_seconds                                  0.199332                       # Nu
 sim_ticks                                199332411500                       # Number of ticks simulated
 final_tick                               199332411500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1838180                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1838179                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              919090070                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 211568                       # Number of bytes of host memory used
-host_seconds                                   216.88                       # Real time elapsed on the host
+host_inst_rate                                3372014                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3372014                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1686007461                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 211928                       # Number of bytes of host memory used
+host_seconds                                   118.23                       # Real time elapsed on the host
 sim_insts                                   398664595                       # Number of instructions simulated
 sim_ops                                     398664595                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                  2257107875                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read             1594658604                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                492356798                       # Number of bytes written to this memory
-system.physmem.num_reads                    493419140                       # Number of read requests responded to by this memory
-system.physmem.num_writes                    73520729                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                    11323336020                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                7999996548                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                    2470028804                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                   13793364824                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst        1594658604                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         662449271                       # Number of bytes read from this memory
+system.physmem.bytes_read::total           2257107875                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst   1594658604                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total      1594658604                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data      492356798                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         492356798                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst          398664651                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data           94754489                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             493419140                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data          73520729                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total             73520729                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst           7999996548                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           3323339471                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total             11323336020                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      7999996548                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         7999996548                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          2470028804                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             2470028804                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          7999996548                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          5793368275                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            13793364824                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
index 998e07c81..b05b7d5ce 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
@@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -176,9 +175,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
index 8e7f3829a..39e268f04 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:36:31
-gem5 started May  8 2012 15:37:07
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:50:11
+gem5 started Jun  4 2012 13:47:31
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
index 852f5134d..f16fecb77 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,22 +4,29 @@ sim_seconds                                  0.567343                       # Nu
 sim_ticks                                567343170000                       # Number of ticks simulated
 final_tick                               567343170000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 766770                       # Simulator instruction rate (inst/s)
-host_op_rate                                   766770                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1091197730                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 220456                       # Number of bytes of host memory used
-host_seconds                                   519.93                       # Real time elapsed on the host
+host_inst_rate                                1377504                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1377504                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1960338494                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220796                       # Number of bytes of host memory used
+host_seconds                                   289.41                       # Real time elapsed on the host
 sim_insts                                   398664609                       # Number of instructions simulated
 sim_ops                                     398664609                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                      459520                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                 205120                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                         7180                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                         809951                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                    361545                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                        809951                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst            205120                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            254400                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               459520                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       205120                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          205120                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3205                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               3975                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7180                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst               361545                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               448406                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                  809951                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          361545                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             361545                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              361545                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              448406                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                 809951                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -109,11 +116,17 @@ system.cpu.icache.demand_accesses::total    398664666                       # nu
 system.cpu.icache.overall_accesses::cpu.inst    398664666                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total    398664666                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000009                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000009                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000009                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000009                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000009                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000009                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50648.516199                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 50648.516199                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 50648.516199                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 50648.516199                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 50648.516199                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 50648.516199                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -135,11 +148,17 @@ system.cpu.icache.demand_mshr_miss_latency::total    175013000
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst    175013000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total    175013000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000009                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000009                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000009                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000009                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000009                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000009                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47648.516199                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47648.516199                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47648.516199                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 47648.516199                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 47648.516199                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                    764                       # number of replacements
 system.cpu.dcache.tagsinuse               3288.912598                       # Cycle average of tags in use
@@ -183,13 +202,21 @@ system.cpu.dcache.demand_accesses::total    168275220                       # nu
 system.cpu.dcache.overall_accesses::cpu.data    168275220                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total    168275220                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000010                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000010                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000044                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000044                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.000025                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000025                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000025                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000025                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50827.368421                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 50827.368421                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55212.991880                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55212.991880                       # average WriteReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 54209.537572                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 54209.537572                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 54209.537572                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 54209.537572                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -217,13 +244,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total    212622000
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data    212622000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total    212622000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000010                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000044                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47827.368421                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47827.368421                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52212.991880                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52212.991880                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51209.537572                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 51209.537572                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51209.537572                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 51209.537572                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                    13                       # number of replacements
 system.cpu.l2cache.tagsinuse              3768.712262                       # Cycle average of tags in use
@@ -288,18 +323,26 @@ system.cpu.l2cache.overall_accesses::cpu.data         4152
 system.cpu.l2cache.overall_accesses::total         7825                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.872584                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.876842                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.873459                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.981262                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.981262                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.872584                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.957370                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.917572                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.872584                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.957370                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.917572                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -332,18 +375,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    159000000
 system.cpu.l2cache.overall_mshr_miss_latency::total    287200000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.872584                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.876842                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.873459                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.981262                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.981262                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.872584                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.957370                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.917572                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.872584                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.957370                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.917572                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
index 1cf41a172..b166901dc 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
@@ -492,9 +492,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -525,9 +524,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
index f0a5e284e..fd4ba336e 100755
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:17:37
-gem5 started May  8 2012 16:35:18
-gem5 executing on piton
+gem5 compiled Jun  4 2012 12:14:06
+gem5 started Jun  4 2012 17:54:41
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
index 969b86901..154ddb0a7 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -4,22 +4,29 @@ sim_seconds                                  0.071775                       # Nu
 sim_ticks                                 71774859500                       # Number of ticks simulated
 final_tick                                71774859500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  69606                       # Simulator instruction rate (inst/s)
-host_op_rate                                    88987                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               18296996                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 240272                       # Number of bytes of host memory used
-host_seconds                                  3922.77                       # Real time elapsed on the host
+host_inst_rate                                 120484                       # Simulator instruction rate (inst/s)
+host_op_rate                                   154032                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               31671128                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 240520                       # Number of bytes of host memory used
+host_seconds                                  2266.26                       # Real time elapsed on the host
 sim_insts                                   273048474                       # Number of instructions simulated
 sim_ops                                     349076199                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                      472896                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                 199168                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                         7389                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                        6588602                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                   2774899                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                       6588602                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst            199168                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            273728                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               472896                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       199168                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          199168                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3112                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               4277                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7389                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              2774899                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3813703                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 6588602                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         2774899                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            2774899                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2774899                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3813703                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6588602                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -368,11 +375,17 @@ system.cpu.icache.demand_accesses::total     39951299                       # nu
 system.cpu.icache.overall_accesses::cpu.inst     39951299                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total     39951299                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000426                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000426                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000426                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000426                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000426                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000426                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12404.519807                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 12404.519807                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 12404.519807                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 12404.519807                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 12404.519807                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 12404.519807                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -400,11 +413,17 @@ system.cpu.icache.demand_mshr_miss_latency::total    139714000
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst    139714000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total    139714000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000403                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000403                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000403                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000403                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000403                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000403                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  8670.348765                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  8670.348765                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  8670.348765                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  8670.348765                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  8670.348765                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  8670.348765                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                   1427                       # number of replacements
 system.cpu.dcache.tagsinuse               3127.647604                       # Cycle average of tags in use
@@ -460,15 +479,25 @@ system.cpu.dcache.demand_accesses::total    172497310                       # nu
 system.cpu.dcache.overall_accesses::cpu.data    172497310                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total    172497310                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000040                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000040                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000238                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000238                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000143                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000143                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.000134                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000134                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000134                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000134                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32138.410228                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 32138.410228                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33299.569848                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 33299.569848                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        38000                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        38000                       # average LoadLockedReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 33118.913777                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 33118.913777                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 33118.913777                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 33118.913777                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets       315000                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -506,13 +535,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total    156453500
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data    156453500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total    156453500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000020                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000020                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000035                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30396.733112                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30396.733112                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35546.727336                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35546.727336                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33552.112374                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 33552.112374                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33552.112374                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 33552.112374                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                    69                       # number of replacements
 system.cpu.l2cache.tagsinuse              4034.301662                       # Cycle average of tags in use
@@ -581,19 +618,28 @@ system.cpu.l2cache.overall_accesses::cpu.data         4641
 system.cpu.l2cache.overall_accesses::total        20733                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.194009                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.834903                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.258647                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.994006                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.994006                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.194009                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.932127                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.359234                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.194009                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.932127                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.359234                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34267.136451                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34345.388188                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34292.611795                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34476.055339                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34476.055339                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34267.136451                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34430.536292                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34362.043502                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.136451                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34430.536292                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34362.043502                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -639,20 +685,30 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    133876000
 system.cpu.l2cache.overall_mshr_miss_latency::total    230619500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.193388                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.807756                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.255350                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994006                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994006                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.193388                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.921569                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.356388                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.193388                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.921569                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.356388                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.242931                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31322.359396                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31162.253829                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        31000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        31000                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31290.528556                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31290.528556                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.242931                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31301.379472                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31211.192313                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.242931                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31301.379472                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31211.192313                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
index 72280076c..796e4e4fa 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
@@ -112,9 +112,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
index 51d5089a3..80d4c141d 100755
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:17:37
-gem5 started May  8 2012 16:37:41
-gem5 executing on piton
+gem5 compiled Jun  4 2012 12:14:06
+gem5 started Jun  4 2012 18:01:26
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
index 30e59a4c3..1239fc01a 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
@@ -4,23 +4,35 @@ sim_seconds                                  0.212344                       # Nu
 sim_ticks                                212344048000                       # Number of ticks simulated
 final_tick                               212344048000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 841557                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1075889                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              654486612                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228648                       # Number of bytes of host memory used
-host_seconds                                   324.44                       # Real time elapsed on the host
+host_inst_rate                                1586428                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2028172                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1233780581                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 229108                       # Number of bytes of host memory used
+host_seconds                                   172.11                       # Real time elapsed on the host
 sim_insts                                   273037671                       # Number of instructions simulated
 sim_ops                                     349065408                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                  1875350709                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read             1394641440                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                400047783                       # Number of bytes written to this memory
-system.physmem.num_reads                    443242866                       # Number of read requests responded to by this memory
-system.physmem.num_writes                    82063572                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                     8831661291                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                6567838624                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                    1883960425                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                   10715621716                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst        1394641440                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         480709269                       # Number of bytes read from this memory
+system.physmem.bytes_read::total           1875350709                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst   1394641440                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total      1394641440                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data      400047783                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         400047783                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst          348660360                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data           94582506                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             443242866                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data          82063572                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total             82063572                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst           6567838624                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           2263822667                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              8831661291                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      6567838624                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         6567838624                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1883960425                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1883960425                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          6567838624                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          4147783092                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            10715621716                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
index 28132d5a1..f88d3c19b 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
@@ -161,9 +161,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -194,9 +193,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
index 85721b4bd..02e894db6 100755
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:17:37
-gem5 started May  8 2012 16:38:02
-gem5 executing on piton
+gem5 compiled Jun  4 2012 12:14:06
+gem5 started Jun  4 2012 18:04:29
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
index 1725766a3..ce6e736cb 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
@@ -4,22 +4,29 @@ sim_seconds                                  0.525854                       # Nu
 sim_ticks                                525854475000                       # Number of ticks simulated
 final_tick                               525854475000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 425859                       # Simulator instruction rate (inst/s)
-host_op_rate                                   544445                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              821076045                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 237820                       # Number of bytes of host memory used
-host_seconds                                   640.45                       # Real time elapsed on the host
+host_inst_rate                                 697015                       # Simulator instruction rate (inst/s)
+host_op_rate                                   891108                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1343878935                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 238268                       # Number of bytes of host memory used
+host_seconds                                   391.30                       # Real time elapsed on the host
 sim_insts                                   272739291                       # Number of instructions simulated
 sim_ops                                     348687131                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                      437312                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                 167040                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                         6833                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                         831622                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                    317654                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                        831622                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst            167040                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            270272                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               437312                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       167040                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          167040                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               2610                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               4223                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  6833                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst               317654                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               513967                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                  831622                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          317654                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             317654                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              317654                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              513967                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                 831622                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -119,11 +126,17 @@ system.cpu.icache.demand_accesses::total    348660359                       # nu
 system.cpu.icache.overall_accesses::cpu.inst    348660359                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total    348660359                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000045                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000045                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000045                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000045                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000045                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000045                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21025.572005                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 21025.572005                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 21025.572005                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 21025.572005                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 21025.572005                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 21025.572005                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -145,11 +158,17 @@ system.cpu.icache.demand_mshr_miss_latency::total    281253000
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst    281253000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total    281253000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000045                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000045                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000045                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000045                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000045                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000045                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18025.572005                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18025.572005                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18025.572005                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 18025.572005                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18025.572005                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 18025.572005                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                   1332                       # number of replacements
 system.cpu.dcache.tagsinuse               3078.396238                       # Cycle average of tags in use
@@ -201,13 +220,21 @@ system.cpu.dcache.demand_accesses::total    176624288                       # nu
 system.cpu.dcache.overall_accesses::cpu.data    176624288                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total    176624288                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000017                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000017                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000035                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000035                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.000025                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000025                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000025                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000025                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49749.688667                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 49749.688667                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55766.016713                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55766.016713                       # average WriteReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 53608.307280                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 53608.307280                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 53608.307280                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 53608.307280                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -235,13 +262,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total    226624000
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data    226624000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total    226624000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000017                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000017                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000035                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46749.688667                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52766.016713                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                    48                       # number of replacements
 system.cpu.l2cache.tagsinuse              3475.672922                       # Cycle average of tags in use
@@ -306,18 +341,26 @@ system.cpu.l2cache.overall_accesses::cpu.data         4478
 system.cpu.l2cache.overall_accesses::total        20081                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.167276                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.851183                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.231100                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.994429                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.994429                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.167276                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.943055                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.340272                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.167276                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.943055                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.340272                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -350,18 +393,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    168920000
 system.cpu.l2cache.overall_mshr_miss_latency::total    273320000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.167276                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.851183                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.231100                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994429                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994429                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.167276                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.943055                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.340272                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.167276                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.943055                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.340272                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------