diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-10-13 23:21:40 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-10-13 23:21:40 +0100 |
| commit | c87b717dbdf36f4b0ebef1df4592f1ebabad15a5 (patch) | |
| tree | e8dab9b58aef6394538af96fd1c7f1f2ffaf5775 /tests/long/se/30.eon | |
| parent | 78dd152a0d5e55e26cd6c501dbc4f73e316937d9 (diff) | |
| download | gem5-c87b717dbdf36f4b0ebef1df4592f1ebabad15a5.tar.xz | |
stats: update references
Diffstat (limited to 'tests/long/se/30.eon')
12 files changed, 2075 insertions, 1998 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini index 00cf13ff8..63271ea71 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini @@ -149,7 +149,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -583,7 +583,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -643,7 +643,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -760,6 +760,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -771,7 +772,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -779,29 +780,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -821,6 +829,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -852,9 +861,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout index 33c16c36c..6a622d0db 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:28 -gem5 executing on e108600-lin, pid 4300 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:45 +gem5 executing on e108600-lin, pid 28070 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/alpha/tru64/minor-timing Global frequency set at 1000000000000 ticks per second @@ -14,4 +14,4 @@ info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.233333 -Exiting @ tick 233525789500 because target called exit() +Exiting @ tick 233641094500 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index 6b30c3cf1..e0c918d80 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.233534 # Number of seconds simulated -sim_ticks 233533887500 # Number of ticks simulated -final_tick 233533887500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.233641 # Number of seconds simulated +sim_ticks 233641094500 # Number of ticks simulated +final_tick 233641094500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 225573 # Simulator instruction rate (inst/s) -host_op_rate 225573 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 132138421 # Simulator tick rate (ticks/s) -host_mem_usage 260868 # Number of bytes of host memory used -host_seconds 1767.34 # Real time elapsed on the host +host_inst_rate 295188 # Simulator instruction rate (inst/s) +host_op_rate 295188 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 172997788 # Simulator tick rate (ticks/s) +host_mem_usage 258004 # Number of bytes of host memory used +host_seconds 1350.54 # Real time elapsed on the host sim_insts 398664651 # Number of instructions simulated sim_ops 398664651 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 249280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory system.physmem.bytes_read::total 503872 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 249280 # Nu system.physmem.num_reads::cpu.inst 3895 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1067425 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1090172 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2157597 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1067425 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1067425 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1067425 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1090172 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2157597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1066936 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1089671 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2156607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1066936 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1066936 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1066936 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1089671 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2156607 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7873 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7873 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 233533785500 # Total gap between requests +system.physmem.totGap 233641000500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6853 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 951 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 69 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6664 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 79 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1544 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 326.051813 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 195.846863 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.937998 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 532 34.46% 34.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 344 22.28% 56.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 193 12.50% 69.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 103 6.67% 75.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 73 4.73% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 45 2.91% 83.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 32 2.07% 85.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 36 2.33% 87.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 186 12.05% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1544 # Bytes accessed per row activation -system.physmem.totQLat 53440000 # Total ticks spent queuing -system.physmem.totMemAccLat 201058750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1527 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 328.298625 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 196.524272 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.958390 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 522 34.18% 34.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 350 22.92% 57.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 181 11.85% 68.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 105 6.88% 75.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 64 4.19% 80.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 46 3.01% 83.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 30 1.96% 85.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 42 2.75% 87.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 187 12.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1527 # Bytes accessed per row activation +system.physmem.totQLat 179319500 # Total ticks spent queuing +system.physmem.totMemAccLat 326938250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6787.76 # Average queueing delay per DRAM burst +system.physmem.avgQLat 22776.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25537.76 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 41526.51 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s @@ -217,53 +217,63 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6327 # Number of row buffer hits during reads +system.physmem.readRowHits 6337 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.36 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.49 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 29662617.24 # Average gap between requests -system.physmem.pageHitRate 80.36 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6758640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3687750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 34296600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 29676235.30 # Average gap between requests +system.physmem.pageHitRate 80.49 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6326040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3347190 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 31444560 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15253240080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6038642700 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 134822908500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 156159534270 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.682165 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 224288059000 # Time in different power states -system.physmem_0.memoryStateTime::REF 7798180000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1447046250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4914000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2681250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 27058200 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 242168160.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 105016230 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 11391840 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 673376340 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 320465280 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 55494876360 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 56888412000 # Total energy per rank (pJ) +system.physmem_0.averagePower 243.486327 # Core power per rank (mW) +system.physmem_0.totalIdleTime 233381065000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 19761500 # Time in different power states +system.physmem_0.memoryStateTime::REF 102860000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 231069881000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 834517500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 137354250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 1476720250 # Time in different power states +system.physmem_1.actEnergy 4641000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2447775 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 24768660 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15253240080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5739994620 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 135084870750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 156112758900 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.481917 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 224725904750 # Time in different power states -system.physmem_1.memoryStateTime::REF 7798180000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1009185250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 45912940 # Number of BP lookups -system.cpu.branchPred.condPredicted 26702743 # Number of conditional branches predicted +system.physmem_1.refreshEnergy 215124000.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 84187860 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12227040 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 535263060 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 280836480 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 55611059460 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 56770555335 # Total energy per rank (pJ) +system.physmem_1.averagePower 242.981892 # Core power per rank (mW) +system.physmem_1.totalIdleTime 233423818750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 23567500 # Time in different power states +system.physmem_1.memoryStateTime::REF 91510000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 231519465750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 731339000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 101377500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1173834750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 45912950 # Number of BP lookups +system.cpu.branchPred.condPredicted 26702746 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 565787 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25186733 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 25186743 # Number of BTB lookups system.cpu.branchPred.BTBHits 18811780 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 74.689242 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 74.689212 # BTB Hit Percentage system.cpu.branchPred.usedRAS 8285572 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2249880 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 2249876 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 2235903 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 13977 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 13973 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 111495 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -275,17 +285,17 @@ system.cpu.dtb.read_misses 116 # DT system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 95338572 # DTB read accesses system.cpu.dtb.write_hits 73578378 # DTB write hits -system.cpu.dtb.write_misses 849 # DTB write misses +system.cpu.dtb.write_misses 847 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73579227 # DTB write accesses +system.cpu.dtb.write_accesses 73579225 # DTB write accesses system.cpu.dtb.data_hits 168916834 # DTB hits -system.cpu.dtb.data_misses 965 # DTB misses +system.cpu.dtb.data_misses 963 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168917799 # DTB accesses -system.cpu.itb.fetch_hits 96959232 # ITB hits +system.cpu.dtb.data_accesses 168917797 # DTB accesses +system.cpu.itb.fetch_hits 96959253 # ITB hits system.cpu.itb.fetch_misses 1239 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 96960471 # ITB accesses +system.cpu.itb.fetch_accesses 96960492 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,16 +309,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 233533887500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 467067775 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 233641094500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 467282189 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664651 # Number of instructions committed system.cpu.committedOps 398664651 # Number of ops (including micro ops) committed system.cpu.discardedOps 2289293 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.171581 # CPI: cycles per instruction -system.cpu.ipc 0.853548 # IPC: instructions per cycle +system.cpu.cpi 1.172118 # CPI: cycles per instruction +system.cpu.ipc 0.853156 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction system.cpu.op_class_0::IntAlu 141652555 35.53% 41.33% # Class of committed instruction system.cpu.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction @@ -344,18 +354,18 @@ system.cpu.op_class_0::MemWrite 73520764 18.44% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 398664651 # Class of committed instruction -system.cpu.tickCycles 455740572 # Number of cycles that the object actually ticked -system.cpu.idleCycles 11327203 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 455741730 # Number of cycles that the object actually ticked +system.cpu.idleCycles 11540459 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.924590 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 167817024 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3291.586193 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 167817015 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40292.202641 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40292.200480 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3291.924590 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803693 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803693 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3291.586193 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803610 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803610 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id @@ -363,41 +373,41 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 3113 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 335652191 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 335652191 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 94302223 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94302223 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73514801 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73514801 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 167817024 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 167817024 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 167817024 # number of overall hits -system.cpu.dcache.overall_hits::total 167817024 # number of overall hits +system.cpu.dcache.tags.tag_accesses 335652183 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 335652183 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 94302219 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94302219 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73514796 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73514796 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 167817015 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 167817015 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 167817015 # number of overall hits +system.cpu.dcache.overall_hits::total 167817015 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1061 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1061 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5928 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5928 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 6989 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6989 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 6989 # number of overall misses -system.cpu.dcache.overall_misses::total 6989 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 80682500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 80682500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 434084500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 434084500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 514767000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 514767000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 514767000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 514767000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 94303284 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94303284 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 5933 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5933 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 6994 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6994 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6994 # number of overall misses +system.cpu.dcache.overall_misses::total 6994 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 94695000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 94695000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 540363000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 540363000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 635058000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 635058000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 635058000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 635058000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 94303280 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94303280 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 167824013 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 167824013 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 167824013 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 167824013 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 167824009 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 167824009 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 167824009 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 167824009 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000011 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000011 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses @@ -406,14 +416,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76043.826579 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 76043.826579 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73226.130229 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73226.130229 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73653.884676 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73653.884676 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73653.884676 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73653.884676 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 89250.706880 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 89250.706880 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 91077.532446 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 91077.532446 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 90800.400343 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 90800.400343 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 90800.400343 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 90800.400343 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -424,12 +434,12 @@ system.cpu.dcache.writebacks::writebacks 654 # nu system.cpu.dcache.writebacks::total 654 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 92 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2732 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2732 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2824 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2824 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2824 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2824 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2737 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2737 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2829 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2829 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2829 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2829 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses @@ -438,14 +448,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4165 system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 72936500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 72936500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 242391000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 242391000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 315327500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 315327500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 315327500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 315327500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86354000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 86354000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 303749000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 303749000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 390103000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 390103000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 390103000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 390103000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -454,139 +464,139 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75269.865841 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75269.865841 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75841.989987 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75841.989987 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75708.883553 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75708.883553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75708.883553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75708.883553 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 3193 # number of replacements -system.cpu.icache.tags.tagsinuse 1919.733373 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 96954061 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5171 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18749.576678 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89116.615067 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89116.615067 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95040.362954 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95040.362954 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 93662.184874 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 93662.184874 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 93662.184874 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 93662.184874 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 3194 # number of replacements +system.cpu.icache.tags.tagsinuse 1919.615846 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 96954081 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5172 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18745.955336 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1919.733373 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.937370 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.937370 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1919.615846 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.937312 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.937312 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1287 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 193923635 # Number of tag accesses -system.cpu.icache.tags.data_accesses 193923635 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 96954061 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 96954061 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 96954061 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 96954061 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 96954061 # number of overall hits -system.cpu.icache.overall_hits::total 96954061 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5171 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5171 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5171 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5171 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5171 # number of overall misses -system.cpu.icache.overall_misses::total 5171 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 321948500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 321948500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 321948500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 321948500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 321948500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 321948500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 96959232 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 96959232 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 96959232 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 96959232 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 96959232 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 96959232 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 193923678 # Number of tag accesses +system.cpu.icache.tags.data_accesses 193923678 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 96954081 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 96954081 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 96954081 # 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Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 503 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 502 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7185 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7186 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.240265 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 114273 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 114273 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.tag_accesses 114289 # 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miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.843295 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.753239 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.843204 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.753094 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955102 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.843295 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75572.521517 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75572.521517 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75897.689345 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75897.689345 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83243.757432 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83243.757432 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75897.689345 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77194.318753 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76552.838816 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75897.689345 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77194.318753 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76552.838816 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.843204 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95135.798534 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95135.798534 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89018.613607 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89018.613607 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99184.304400 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 99184.304400 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89018.613607 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95991.704374 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 92541.915407 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89018.613607 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95991.704374 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 92541.915407 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -669,79 +679,79 @@ system.cpu.l2cache.demand_mshr_misses::total 7873 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3895 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3978 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7873 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 205701000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 205701000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 256671500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 256671500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 61598000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 61598000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 256671500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 267299000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 523970500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 256671500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 267299000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 523970500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 267071000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 267071000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 307777500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 307777500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 75004000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 75004000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 307777500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 342075000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 649852500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 307777500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 342075000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 649852500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.753239 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.753239 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.753094 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.753094 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.869700 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.753239 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.753094 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.843295 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.753239 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.843204 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.753094 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.843295 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65572.521517 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65572.521517 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65897.689345 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65897.689345 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73243.757432 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73243.757432 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65897.689345 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67194.318753 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66552.838816 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65897.689345 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67194.318753 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66552.838816 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 13300 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 3964 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.843204 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85135.798534 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85135.798534 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79018.613607 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79018.613607 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89184.304400 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 89184.304400 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79018.613607 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85991.704374 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 82541.915407 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79018.613607 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85991.704374 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82541.915407 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 13302 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3965 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 6138 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 6139 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 654 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 3193 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 3194 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 117 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 5171 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 5172 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 967 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13535 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13538 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9101 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22636 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 535296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22639 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 535424 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 843712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 843840 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 9336 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 9337 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 9336 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 9337 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 9336 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10497000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 9337 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10499000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7756500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7758000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6247500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) @@ -751,7 +761,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4736 # Transaction distribution system.membus.trans_dist::ReadExReq 3137 # Transaction distribution system.membus.trans_dist::ReadExResp 3137 # Transaction distribution @@ -772,9 +782,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7873 # Request fanout histogram -system.membus.reqLayer0.occupancy 9223000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9215000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 41799750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 41791500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini index e7c466732..c2a5884c8 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -173,7 +173,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -531,7 +531,7 @@ pipelined=false [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -591,7 +591,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -708,6 +708,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -719,7 +720,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -727,29 +728,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -769,6 +777,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -800,9 +809,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout index 02658fe82..ee5bfc401 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:28 -gem5 executing on e108600-lin, pid 4299 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:44 +gem5 executing on e108600-lin, pid 28057 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second @@ -14,4 +14,4 @@ info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.050000 -Exiting @ tick 64188759000 because target called exit() +Exiting @ tick 64255452000 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 71e9e3432..1a8043b05 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,35 +1,35 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.064159 # Number of seconds simulated -sim_ticks 64159445000 # Number of ticks simulated -final_tick 64159445000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.064255 # Number of seconds simulated +sim_ticks 64255452000 # Number of ticks simulated +final_tick 64255452000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 223776 # Simulator instruction rate (inst/s) -host_op_rate 223776 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38227708 # Simulator tick rate (ticks/s) -host_mem_usage 261380 # Number of bytes of host memory used -host_seconds 1678.35 # Real time elapsed on the host +host_inst_rate 260947 # Simulator instruction rate (inst/s) +host_op_rate 260947 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44644346 # Simulator tick rate (ticks/s) +host_mem_usage 259540 # Number of bytes of host memory used +host_seconds 1439.27 # Real time elapsed on the host sim_insts 375574794 # Number of instructions simulated sim_ops 375574794 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 220736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255360 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255296 # Number of bytes read from this memory system.physmem.bytes_read::total 476096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 220736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 220736 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3449 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3990 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 220800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220800 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3450 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3989 # Number of read requests responded to by this memory system.physmem.num_reads::total 7439 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3440429 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3980084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7420513 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3440429 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3440429 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3440429 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3980084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7420513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3436284 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3973141 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7409426 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3436284 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3436284 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3436284 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3973141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7409426 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7439 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7439 # Number of DRAM read bursts, including those serviced by the write queue @@ -43,20 +43,20 @@ system.physmem.servicedByWrQ 0 # Nu system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 524 # Per bank write bursts -system.physmem.perBankRdBursts::1 652 # Per bank write bursts +system.physmem.perBankRdBursts::1 651 # Per bank write bursts system.physmem.perBankRdBursts::2 450 # Per bank write bursts system.physmem.perBankRdBursts::3 600 # Per bank write bursts system.physmem.perBankRdBursts::4 446 # Per bank write bursts system.physmem.perBankRdBursts::5 454 # Per bank write bursts system.physmem.perBankRdBursts::6 513 # Per bank write bursts -system.physmem.perBankRdBursts::7 523 # Per bank write bursts +system.physmem.perBankRdBursts::7 524 # Per bank write bursts system.physmem.perBankRdBursts::8 438 # Per bank write bursts system.physmem.perBankRdBursts::9 408 # Per bank write bursts system.physmem.perBankRdBursts::10 339 # Per bank write bursts -system.physmem.perBankRdBursts::11 305 # Per bank write bursts +system.physmem.perBankRdBursts::11 306 # Per bank write bursts system.physmem.perBankRdBursts::12 414 # Per bank write bursts system.physmem.perBankRdBursts::13 540 # Per bank write bursts -system.physmem.perBankRdBursts::14 453 # Per bank write bursts +system.physmem.perBankRdBursts::14 452 # Per bank write bursts system.physmem.perBankRdBursts::15 380 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 64159334500 # Total gap between requests +system.physmem.totGap 64255349500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,11 +91,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1861 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 920 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 327 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3982 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 111 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -188,28 +188,28 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 1349 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 352.640474 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 209.024877 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 349.175025 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 440 32.62% 32.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 302 22.39% 55.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 154 11.42% 66.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 83 6.15% 72.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 53 3.93% 76.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 50 3.71% 80.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 36 2.67% 82.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 35 2.59% 85.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 351.644181 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 209.715239 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 347.080632 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 429 31.80% 31.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 311 23.05% 54.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 151 11.19% 66.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 87 6.45% 72.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 68 5.04% 77.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 39 2.89% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 38 2.82% 83.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 30 2.22% 85.47% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 196 14.53% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1349 # Bytes accessed per row activation -system.physmem.totQLat 63577500 # Total ticks spent queuing -system.physmem.totMemAccLat 203058750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 165053250 # Total ticks spent queuing +system.physmem.totMemAccLat 304534500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37195000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8546.51 # Average queueing delay per DRAM burst +system.physmem.avgQLat 22187.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27296.51 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 7.42 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 40937.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 7.41 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 7.42 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 7.41 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage @@ -217,75 +217,85 @@ system.physmem.busUtilRead 0.06 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6088 # Number of row buffer hits during reads +system.physmem.readRowHits 6085 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.84 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.80 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8624725.70 # Average gap between requests -system.physmem.pageHitRate 81.84 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5821200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3176250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 32416800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 8637632.68 # Average gap between requests +system.physmem.pageHitRate 81.80 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5454960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2880405 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 29716680 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4190534400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1995176700 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 36745221000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 42972346350 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.779347 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 61126318750 # Time in different power states -system.physmem_0.memoryStateTime::REF 2142400000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 890255000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4377240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2388375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 25560600 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 128459760.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 63558420 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 5463840 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 397888500 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 152192640 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 15095921460 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 15881536665 # Total energy per rank (pJ) +system.physmem_0.averagePower 247.162475 # Core power per rank (mW) +system.physmem_0.totalIdleTime 64101767750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 8572500 # Time in different power states +system.physmem_0.memoryStateTime::REF 54520000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 62832935750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 396328750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 90536500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 872558500 # Time in different power states +system.physmem_1.actEnergy 4212600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2239050 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 23397780 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4190534400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1859740425 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 36864024750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 42946625790 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.378459 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 61324552000 # Time in different power states -system.physmem_1.memoryStateTime::REF 2142400000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 692021750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 47856205 # Number of BP lookups -system.cpu.branchPred.condPredicted 27886274 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 572784 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 23348714 # Number of BTB lookups -system.cpu.branchPred.BTBHits 19574502 # Number of BTB hits +system.physmem_1.refreshEnergy 172713840.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 67790100 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 10409760 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 394655460 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 234464640 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 15065735460 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 15975618690 # Total energy per rank (pJ) +system.physmem_1.averagePower 248.626662 # Core power per rank (mW) +system.physmem_1.totalIdleTime 64079571000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 20607500 # Time in different power states +system.physmem_1.memoryStateTime::REF 73504000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 62603628000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 610590500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 81643000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 865479000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 47858833 # Number of BP lookups +system.cpu.branchPred.condPredicted 27887840 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 573531 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 23350857 # Number of BTB lookups +system.cpu.branchPred.BTBHits 19575248 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.835461 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 8687459 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1418 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2338624 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2308001 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 30623 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 111239 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 83.830962 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 8687752 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1405 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 2338807 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2307668 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 31139 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 111329 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 98829712 # DTB read hits -system.cpu.dtb.read_misses 28367 # DTB read misses -system.cpu.dtb.read_acv 845 # DTB read access violations -system.cpu.dtb.read_accesses 98858079 # DTB read accesses -system.cpu.dtb.write_hits 75499203 # DTB write hits -system.cpu.dtb.write_misses 1454 # DTB write misses +system.cpu.dtb.read_hits 98831063 # DTB read hits +system.cpu.dtb.read_misses 28342 # DTB read misses +system.cpu.dtb.read_acv 849 # DTB read access violations +system.cpu.dtb.read_accesses 98859405 # DTB read accesses +system.cpu.dtb.write_hits 75501441 # DTB write hits +system.cpu.dtb.write_misses 1449 # DTB write misses system.cpu.dtb.write_acv 3 # DTB write access violations -system.cpu.dtb.write_accesses 75500657 # DTB write accesses -system.cpu.dtb.data_hits 174328915 # DTB hits -system.cpu.dtb.data_misses 29821 # DTB misses -system.cpu.dtb.data_acv 848 # DTB access violations -system.cpu.dtb.data_accesses 174358736 # DTB accesses -system.cpu.itb.fetch_hits 46955913 # ITB hits -system.cpu.itb.fetch_misses 420 # ITB misses -system.cpu.itb.fetch_acv 7 # ITB acv -system.cpu.itb.fetch_accesses 46956333 # ITB accesses +system.cpu.dtb.write_accesses 75502890 # DTB write accesses +system.cpu.dtb.data_hits 174332504 # DTB hits +system.cpu.dtb.data_misses 29791 # DTB misses +system.cpu.dtb.data_acv 852 # DTB access violations +system.cpu.dtb.data_accesses 174362295 # DTB accesses +system.cpu.itb.fetch_hits 46958874 # ITB hits +system.cpu.itb.fetch_misses 432 # ITB misses +system.cpu.itb.fetch_acv 5 # ITB acv +system.cpu.itb.fetch_accesses 46959306 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,141 +309,141 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 64159445000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 128318893 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 64255452000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 128510907 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 47425719 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 424811206 # Number of instructions fetch has processed -system.cpu.fetch.Branches 47856205 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 30569962 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 79950349 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1246202 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 47429437 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 424837073 # Number of instructions fetch has processed +system.cpu.fetch.Branches 47858833 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 30570668 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80085665 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1247776 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 13 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 270 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 13187 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 60 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 46955913 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 225768 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 128012699 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.318508 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.349839 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.MiscStallCycles 297 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 13295 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 79 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 46958874 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 226146 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 128152674 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.315086 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.349633 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 53041219 41.43% 41.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4325218 3.38% 44.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6711253 5.24% 50.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5104898 3.99% 54.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 10968142 8.57% 62.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 7524114 5.88% 68.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5300788 4.14% 72.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1845614 1.44% 74.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 33191453 25.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 53168247 41.49% 41.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4330315 3.38% 44.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6713619 5.24% 50.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5107106 3.99% 54.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 10970093 8.56% 62.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 7524949 5.87% 68.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5303300 4.14% 72.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1847075 1.44% 74.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 33187970 25.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 128012699 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.372947 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.310590 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 42125446 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 13481218 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 67948873 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3838220 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 618942 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 8882912 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4201 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 421902807 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 13825 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 618942 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 43678343 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3058028 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 517106 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70134710 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10005570 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 419884966 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 437260 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2526892 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2765017 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 3520699 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 273968908 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 552151473 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 393698766 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 158452706 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 128152674 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.372411 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.305844 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 42097840 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 13659925 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 67904561 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3870622 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 619726 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 8883416 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4205 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 421920314 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 13831 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 619726 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 43662514 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3075430 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 529984 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70109441 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 10155579 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 419899923 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 443686 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2538434 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2849903 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 3565226 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 273976095 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 552171720 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 393714640 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 158457079 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532319 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14436589 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 37562 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 14443776 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 37564 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 298 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 15635470 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 99735139 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 76519296 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 11859955 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9294086 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 392181792 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 15805009 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 99734698 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 76520876 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 11857010 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9264279 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 392184083 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 290 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 389203558 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 195886 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 16607287 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7664931 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 389210637 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 196187 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 16609578 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7664570 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 75 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 128012699 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.040351 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.180919 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 128152674 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.037086 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.181467 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17224377 13.46% 13.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19358192 15.12% 28.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22001472 17.19% 45.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17955910 14.03% 59.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 19066405 14.89% 74.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 13282652 10.38% 85.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8794829 6.87% 91.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6104058 4.77% 96.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4224804 3.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17313559 13.51% 13.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19411245 15.15% 28.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22012922 17.18% 45.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17948678 14.01% 59.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 19074074 14.88% 74.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 13271943 10.36% 85.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8797733 6.87% 91.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6095055 4.76% 96.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4227465 3.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 128012699 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 128152674 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 256922 1.42% 1.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2 0.00% 1.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 138470 0.76% 2.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 78848 0.44% 2.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 3339 0.02% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 3443164 19.01% 21.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1648895 9.10% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 30.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8039924 44.38% 75.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4505956 24.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 253970 1.40% 1.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 1.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 138834 0.77% 2.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 79013 0.44% 2.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 3594 0.02% 2.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 3443745 19.00% 21.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1647907 9.09% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 30.72% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8047413 44.40% 75.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4509145 24.88% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 146986421 37.77% 37.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2128250 0.55% 38.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 146989472 37.77% 37.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2128309 0.55% 38.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 36418938 9.36% 47.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7355017 1.89% 49.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2800646 0.72% 50.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16556809 4.25% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1584153 0.41% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 36418443 9.36% 47.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7355119 1.89% 49.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2800065 0.72% 50.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16556449 4.25% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1584163 0.41% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.95% # Type of FU issued @@ -455,82 +465,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.95% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 99502900 25.57% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 75836843 19.49% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 99502948 25.57% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 75842088 19.49% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 389203558 # Type of FU issued -system.cpu.iq.rate 3.033096 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18115520 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.046545 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 592493180 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 242176639 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 227925873 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 332238041 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 166682962 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 158291544 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 234723560 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 172561937 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19352464 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 389210637 # Type of FU issued +system.cpu.iq.rate 3.028619 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18123623 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.046565 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 592644502 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 242185048 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 227933309 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 332249256 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 166679024 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 158288157 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 234729597 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172571082 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19364531 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4980653 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 92349 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 70589 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2998568 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4980212 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 92962 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 70485 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3000148 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 383293 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3853 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 382479 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3666 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 618942 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1854909 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 149633 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 415904338 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 108226 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 99735139 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 76519296 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 619726 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1854972 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 162334 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 415907776 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 109026 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 99734698 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 76520876 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 290 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7462 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 141873 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 70589 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 411438 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 230495 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 641933 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 387616397 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 98858950 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1587161 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 8920 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 152322 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 70485 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 412161 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 230865 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 643026 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 387624331 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 98860283 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1586306 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 23722256 # number of nop insts executed -system.cpu.iew.exec_refs 174359643 # number of memory reference insts executed -system.cpu.iew.exec_branches 45862472 # Number of branches executed -system.cpu.iew.exec_stores 75500693 # Number of stores executed -system.cpu.iew.exec_rate 3.020727 # Inst execution rate -system.cpu.iew.wb_sent 386480663 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 386217417 # cumulative count of insts written-back -system.cpu.iew.wb_producers 192328787 # num instructions producing a value -system.cpu.iew.wb_consumers 273868663 # num instructions consuming a value -system.cpu.iew.wb_rate 3.009825 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.702266 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 17240745 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 23723403 # number of nop insts executed +system.cpu.iew.exec_refs 174363211 # number of memory reference insts executed +system.cpu.iew.exec_branches 45864022 # Number of branches executed +system.cpu.iew.exec_stores 75502928 # Number of stores executed +system.cpu.iew.exec_rate 3.016276 # Inst execution rate +system.cpu.iew.wb_sent 386484413 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 386221466 # cumulative count of insts written-back +system.cpu.iew.wb_producers 192314001 # num instructions producing a value +system.cpu.iew.wb_consumers 273852153 # num instructions consuming a value +system.cpu.iew.wb_rate 3.005359 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.702255 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 17244606 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 568625 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 125549188 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.175366 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.248155 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 569369 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 125687681 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.171867 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.248348 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 42020703 33.47% 33.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 17522364 13.96% 47.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 8729636 6.95% 54.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9062074 7.22% 61.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6240745 4.97% 66.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4112376 3.28% 69.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4753795 3.79% 73.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2410879 1.92% 75.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 30696616 24.45% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 42136978 33.53% 33.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 17569311 13.98% 47.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 8725420 6.94% 54.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9050963 7.20% 61.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6228783 4.96% 66.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4113989 3.27% 69.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 4743327 3.77% 73.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2404790 1.91% 75.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 30714120 24.44% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 125549188 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 125687681 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664569 # Number of instructions committed system.cpu.commit.committedOps 398664569 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -576,33 +586,33 @@ system.cpu.commit.op_class_0::MemWrite 73520728 18.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 398664569 # Class of committed instruction -system.cpu.commit.bw_lim_events 30696616 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 510754909 # The number of ROB reads -system.cpu.rob.rob_writes 834280363 # The number of ROB writes -system.cpu.timesIdled 3150 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 306194 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 30714120 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 510879759 # The number of ROB reads +system.cpu.rob.rob_writes 834289662 # The number of ROB writes +system.cpu.timesIdled 3136 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 358233 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574794 # Number of Instructions Simulated system.cpu.committedOps 375574794 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.341660 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.341660 # CPI: Total CPI of All Threads -system.cpu.ipc 2.926886 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.926886 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 385442521 # number of integer regfile reads -system.cpu.int_regfile_writes 165246956 # number of integer regfile writes -system.cpu.fp_regfile_reads 154535424 # number of floating regfile reads -system.cpu.fp_regfile_writes 102076666 # number of floating regfile writes +system.cpu.cpi 0.342171 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.342171 # CPI: Total CPI of All Threads +system.cpu.ipc 2.922513 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.922513 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 385452576 # number of integer regfile reads +system.cpu.int_regfile_writes 165252743 # number of integer regfile writes +system.cpu.fp_regfile_reads 154537274 # number of floating regfile reads +system.cpu.fp_regfile_writes 102070951 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 779 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.925722 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 152589979 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4179 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 36513.514956 # Average number of references to valid blocks. +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 774 # number of replacements +system.cpu.dcache.tags.tagsinuse 3291.451205 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 152580730 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4174 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 36555.038333 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3291.925722 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803693 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803693 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3291.451205 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803577 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803577 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3400 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id @@ -610,304 +620,304 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 211 system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.830078 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 305227185 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 305227185 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 79088959 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 79088959 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501014 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501014 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 305207642 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 305207642 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 79079190 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 79079190 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501534 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501534 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 152589973 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 152589973 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 152589973 # number of overall hits -system.cpu.dcache.overall_hits::total 152589973 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 152580724 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 152580724 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 152580724 # number of overall hits +system.cpu.dcache.overall_hits::total 152580724 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1810 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1810 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19714 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19714 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21524 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21524 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21524 # number of overall misses -system.cpu.dcache.overall_misses::total 21524 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 128203000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 128203000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1194602455 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1194602455 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1322805455 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1322805455 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1322805455 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1322805455 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 79090769 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 79090769 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 19194 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19194 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21004 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21004 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21004 # number of overall misses +system.cpu.dcache.overall_misses::total 21004 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 137671000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 137671000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1331646003 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1331646003 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1469317003 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1469317003 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1469317003 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1469317003 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 79081000 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 79081000 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520728 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520728 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 152611497 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 152611497 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 152611497 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 152611497 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 152601728 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 152601728 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 152601728 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 152601728 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000268 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000268 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000141 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000141 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000141 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000141 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70830.386740 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70830.386740 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60596.654915 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60596.654915 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61457.231695 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61457.231695 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61457.231695 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61457.231695 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 49869 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 82 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 741 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000261 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000261 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000138 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000138 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000138 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000138 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76061.325967 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 76061.325967 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69378.243357 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69378.243357 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69954.151733 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69954.151733 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69954.151733 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69954.151733 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 57813 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 94 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 689 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 67.299595 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 82 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 658 # number of writebacks -system.cpu.dcache.writebacks::total 658 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 821 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 821 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16524 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16524 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17345 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17345 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17345 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17345 # 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Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 297 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1343 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1342 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.940918 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 93915884 # Number of tag accesses -system.cpu.icache.tags.data_accesses 93915884 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 46950265 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76969.790206 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76969.790206 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76969.790206 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76969.790206 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 896 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 63.888889 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 59.733333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.871587 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.849926 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.954774 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.903120 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.849926 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.954774 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.903120 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68525.575448 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68525.575448 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66940.852421 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66940.852421 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74840.487239 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74840.487239 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66940.852421 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69889.849624 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68522.583681 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66940.852421 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69889.849624 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68522.583681 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 11147 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2910 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 263192000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 263192000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 276069500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 276069500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 72017500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 72017500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 276069500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 335209500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 611279000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 276069500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 335209500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 611279000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981179 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981179 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.849963 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.849963 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.873225 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.873225 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.849963 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955678 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.903559 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.849963 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955678 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.903559 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84140.664962 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84140.664962 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 80020.144928 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 80020.144928 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83644.018583 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 83644.018583 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 80020.144928 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84033.467034 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 82172.200565 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 80020.144928 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84033.467034 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82172.200565 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 11139 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2906 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 5047 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 658 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2131 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 121 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3190 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3190 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 4058 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 989 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10247 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9137 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 19384 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 396096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 705664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 5045 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 655 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2132 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 119 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3188 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3188 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4059 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 986 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10250 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9122 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 19372 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 396224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 705280 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 8237 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 8233 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 8237 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 8233 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8237 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 8362500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 8233 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 8356500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6087499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6088500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6268500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6261000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.snoop_filter.tot_requests 7439 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -1008,7 +1018,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4311 # Transaction distribution system.membus.trans_dist::ReadExReq 3128 # Transaction distribution system.membus.trans_dist::ReadExResp 3128 # Transaction distribution @@ -1029,9 +1039,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7439 # Request fanout histogram -system.membus.reqLayer0.occupancy 9245500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9229500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 39234750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 39165500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini index 76d7daa42..3e9f2ae1c 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini @@ -151,7 +151,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -631,7 +631,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -691,7 +691,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -763,7 +763,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -880,6 +880,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -891,7 +892,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -899,29 +900,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -941,6 +949,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -950,7 +959,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -972,9 +981,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout index ab196f487..feeb32deb 100755 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:38:22 -gem5 executing on e108600-lin, pid 23074 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:47:28 +gem5 executing on e108600-lin, pid 17426 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second @@ -16,4 +16,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.220000 -Exiting @ tick 225030243000 because target called exit() +Exiting @ tick 225206521000 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index a1a985a56..c3dd06017 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.225041 # Number of seconds simulated -sim_ticks 225040911000 # Number of ticks simulated -final_tick 225040911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.225207 # Number of seconds simulated +sim_ticks 225206521000 # Number of ticks simulated +final_tick 225206521000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 161529 # Simulator instruction rate (inst/s) -host_op_rate 193933 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 133133968 # Simulator tick rate (ticks/s) -host_mem_usage 280148 # Number of bytes of host memory used -host_seconds 1690.33 # Real time elapsed on the host +host_inst_rate 132189 # Simulator instruction rate (inst/s) +host_op_rate 158707 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 109031633 # Simulator tick rate (ticks/s) +host_mem_usage 278744 # Number of bytes of host memory used +host_seconds 2065.52 # Real time elapsed on the host sim_insts 273037855 # Number of instructions simulated sim_ops 327812212 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 219136 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 266432 # Number of bytes read from this memory system.physmem.bytes_read::total 485568 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 219136 # Nu system.physmem.num_reads::cpu.inst 3424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4163 # Number of read requests responded to by this memory system.physmem.num_reads::total 7587 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 973761 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1183927 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2157688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 973761 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 973761 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 973761 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1183927 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2157688 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 973045 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1183056 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2156101 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 973045 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 973045 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 973045 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1183056 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2156101 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7587 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7587 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 225040663000 # Total gap between requests +system.physmem.totGap 225206267000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,8 +91,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6713 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6691 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 845 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1537 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 314.836695 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 187.294672 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.034747 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 563 36.63% 36.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 357 23.23% 59.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 158 10.28% 70.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 85 5.53% 75.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 84 5.47% 81.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 48 3.12% 84.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 39 2.54% 86.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 28 1.82% 88.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 175 11.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1537 # Bytes accessed per row activation -system.physmem.totQLat 55497500 # Total ticks spent queuing -system.physmem.totMemAccLat 197753750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1511 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 320.635341 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 191.281375 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 328.659938 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 540 35.74% 35.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 351 23.23% 58.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 165 10.92% 69.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 80 5.29% 75.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 78 5.16% 80.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 55 3.64% 83.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 33 2.18% 86.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 36 2.38% 88.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 173 11.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1511 # Bytes accessed per row activation +system.physmem.totQLat 232482000 # Total ticks spent queuing +system.physmem.totMemAccLat 374738250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37935000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7314.81 # Average queueing delay per DRAM burst +system.physmem.avgQLat 30642.15 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26064.81 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 49392.15 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s @@ -217,56 +217,66 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6044 # Number of row buffer hits during reads +system.physmem.readRowHits 6073 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.66 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.04 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 29661350.07 # Average gap between requests -system.physmem.pageHitRate 79.66 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5110560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2788500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 29967600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 29683177.41 # Average gap between requests +system.physmem.pageHitRate 80.04 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4726680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2504700 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 27553260 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14698401120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5878157490 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 129866796000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 150481221270 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.691134 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 216043617250 # Time in different power states -system.physmem_0.memoryStateTime::REF 7514520000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1481090250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6501600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3547500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 29000400 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 284578320.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 100450530 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 15488640 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 721250640 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 385416480 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 53424510300 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 54966479550 # Total energy per rank (pJ) +system.physmem_0.averagePower 244.071438 # Core power per rank (mW) +system.physmem_0.totalIdleTime 224945701750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 29370000 # Time in different power states +system.physmem_0.memoryStateTime::REF 121010000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 222360521000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 1003697750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 110222000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 1581700250 # Time in different power states +system.physmem_1.actEnergy 6083280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3229545 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 26617920 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14698401120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 6069721950 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 129698757000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 150505929570 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.800930 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 215760799500 # Time in different power states -system.physmem_1.memoryStateTime::REF 7514520000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1763151750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 32430292 # Number of BP lookups -system.cpu.branchPred.condPredicted 16924100 # Number of conditional branches predicted +system.physmem_1.refreshEnergy 394598880.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 121239570 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 22348800 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 914379180 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 605052000 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 53195794545 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 55289408190 # Total energy per rank (pJ) +system.physmem_1.averagePower 245.505361 # Core power per rank (mW) +system.physmem_1.totalIdleTime 224881567000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 42133000 # Time in different power states +system.physmem_1.memoryStateTime::REF 167838000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 221301429000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 1575669750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 114195250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 2005256000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 32430299 # Number of BP lookups +system.cpu.branchPred.condPredicted 16924101 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 738493 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17494982 # Number of BTB lookups -system.cpu.branchPred.BTBHits 12858504 # Number of BTB hits +system.cpu.branchPred.BTBLookups 17494977 # Number of BTB lookups +system.cpu.branchPred.BTBHits 12858505 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 73.498241 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6523127 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 73.498268 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6523139 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 2303930 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 2264813 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 39117 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 128237 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +336,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,16 +397,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 225040911000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 450081822 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 225206521000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 450413042 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 273037855 # Number of instructions committed system.cpu.committedOps 327812212 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2063975 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2063976 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.648423 # CPI: cycles per instruction -system.cpu.ipc 0.606640 # IPC: instructions per cycle +system.cpu.cpi 1.649636 # CPI: cycles per instruction +system.cpu.ipc 0.606194 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 104312542 31.82% 31.82% # Class of committed instruction system.cpu.op_class_0::IntMult 2145905 0.65% 32.48% # Class of committed instruction @@ -432,62 +442,62 @@ system.cpu.op_class_0::MemWrite 82375599 25.13% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 327812212 # Class of committed instruction -system.cpu.tickCycles 434887274 # Number of cycles that the object actually ticked -system.cpu.idleCycles 15194548 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 434950533 # Number of cycles that the object actually ticked +system.cpu.idleCycles 15462509 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1355 # number of replacements -system.cpu.dcache.tags.tagsinuse 3086.207714 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168654219 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3085.768112 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168654205 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4512 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37379.037899 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37379.034796 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3086.207714 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.753469 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.753469 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768112 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.753361 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.753361 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 337326820 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 337326820 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 86521434 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86521434 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82047457 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047457 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 337326812 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337326812 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 86521430 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86521430 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82047447 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047447 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 63538 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 63538 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168568891 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168568891 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168632429 # number of overall hits -system.cpu.dcache.overall_hits::total 168632429 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 168568877 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168568877 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168632415 # number of overall hits +system.cpu.dcache.overall_hits::total 168632415 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1710 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1710 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5220 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5220 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5230 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5230 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 6930 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6930 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 6935 # number of overall misses -system.cpu.dcache.overall_misses::total 6935 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 116252000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 116252000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 401349000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 401349000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 517601000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 517601000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 517601000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 517601000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86523144 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86523144 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 6940 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6940 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6945 # number of overall misses +system.cpu.dcache.overall_misses::total 6945 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 177324000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 177324000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 487891500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 487891500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 665215500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 665215500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 665215500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 665215500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86523140 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86523140 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 63543 # number of SoftPFReq accesses(hits+misses) @@ -496,10 +506,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168575821 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168575821 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168639364 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168639364 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168575817 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168575817 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168639360 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168639360 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses @@ -510,14 +520,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000041 system.cpu.dcache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000041 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67983.625731 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67983.625731 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76886.781609 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76886.781609 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 74689.898990 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 74689.898990 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 74636.049027 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 74636.049027 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103698.245614 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 103698.245614 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93287.093690 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 93287.093690 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 95852.377522 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 95852.377522 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 95783.369330 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 95783.369330 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -528,12 +538,12 @@ system.cpu.dcache.writebacks::writebacks 1010 # nu system.cpu.dcache.writebacks::total 1010 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 71 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2350 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2350 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2421 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2421 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2421 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2421 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2360 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2360 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2431 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2431 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2431 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2431 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1639 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1639 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses @@ -544,16 +554,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4509 system.cpu.dcache.demand_mshr_misses::total 4509 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4512 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4512 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 111802000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 111802000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 223602000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 223602000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 241000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 241000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 335404000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 335404000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 335645000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 335645000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 172098000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 172098000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 285707500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 285707500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 259000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 259000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 457805500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 457805500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 458064500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 458064500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -564,72 +574,72 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68213.544844 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68213.544844 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77910.104530 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77910.104530 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80333.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80333.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74385.451320 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74385.451320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74389.406028 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74389.406028 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 105001.830384 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 105001.830384 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99549.651568 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99549.651568 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 86333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 86333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101531.492570 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 101531.492570 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101521.387411 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 101521.387411 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 38188 # number of replacements -system.cpu.icache.tags.tagsinuse 1924.983594 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 69819782 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1924.800725 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 69819801 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 40125 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1740.056872 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1740.057346 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1924.983594 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939933 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939933 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.800725 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939844 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939844 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 277 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 139759941 # Number of tag accesses -system.cpu.icache.tags.data_accesses 139759941 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 69819782 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 69819782 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 69819782 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 69819782 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 69819782 # number of overall hits -system.cpu.icache.overall_hits::total 69819782 # number of overall hits +system.cpu.icache.tags.tag_accesses 139759979 # Number of tag accesses +system.cpu.icache.tags.data_accesses 139759979 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 69819801 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 69819801 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 69819801 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 69819801 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 69819801 # number of overall hits +system.cpu.icache.overall_hits::total 69819801 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 40126 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 40126 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 40126 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 40126 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 40126 # number of overall misses system.cpu.icache.overall_misses::total 40126 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 763080000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 763080000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 763080000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 763080000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 763080000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 763080000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 69859908 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 69859908 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 69859908 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 69859908 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 69859908 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 69859908 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 817901000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 817901000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 817901000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 817901000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 817901000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 817901000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 69859927 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 69859927 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 69859927 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 69859927 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 69859927 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 69859927 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000574 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000574 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000574 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000574 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000574 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000574 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19017.096147 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19017.096147 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19017.096147 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19017.096147 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19017.096147 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19017.096147 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20383.317550 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20383.317550 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20383.317550 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20383.317550 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20383.317550 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20383.317550 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -644,46 +654,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 40126 system.cpu.icache.demand_mshr_misses::total 40126 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 40126 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 40126 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 722955000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 722955000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 722955000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 722955000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 722955000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 722955000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 777776000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 777776000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 777776000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 777776000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 777776000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 777776000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000574 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000574 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000574 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18017.121069 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18017.121069 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18017.121069 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18017.121069 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18017.121069 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18017.121069 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19383.342471 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19383.342471 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19383.342471 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19383.342471 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19383.342471 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19383.342471 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 6597.313111 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 6596.216026 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 61516 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 7587 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 8.108080 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3168.373403 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.939708 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096691 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.104643 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.201334 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.840745 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.375281 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096675 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.104626 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.201301 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 7587 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 789 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6671 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.231537 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 560755 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 560755 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 1010 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 1010 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 23270 # number of WritebackClean hits @@ -712,18 +722,18 @@ system.cpu.l2cache.demand_misses::total 7630 # nu system.cpu.l2cache.overall_misses::cpu.inst 3426 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses system.cpu.l2cache.overall_misses::total 7630 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 219100000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 219100000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 262492500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 262492500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 106317000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 106317000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 262492500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 325417000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 587909500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 262492500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 325417000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 587909500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 281205000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 281205000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 317313000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 317313000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 166631000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 166631000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 317313000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 447836000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 765149000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 317313000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 447836000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 765149000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 1010 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 1010 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 23270 # number of WritebackClean accesses(hits+misses) @@ -752,18 +762,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.170931 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085381 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.931738 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.170931 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76769.446391 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76769.446391 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76617.775832 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76617.775832 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78753.333333 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78753.333333 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76617.775832 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77406.517602 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77052.359109 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76617.775832 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77406.517602 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77052.359109 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98530.133146 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98530.133146 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92619.089317 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92619.089317 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123430.370370 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123430.370370 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92619.089317 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106526.165557 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 100281.651376 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92619.089317 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106526.165557 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 100281.651376 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -792,18 +802,18 @@ system.cpu.l2cache.demand_mshr_misses::total 7587 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3424 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4163 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7587 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 190560000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 190560000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 228116000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 228116000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 90492000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 90492000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 228116000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 281052000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 509168000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 228116000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 281052000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 509168000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 252665000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 252665000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 282924500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 282924500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 150580000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 150580000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 282924500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 403245000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 686169500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 282924500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 403245000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 686169500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for ReadCleanReq accesses @@ -816,25 +826,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.169967 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.169967 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66769.446391 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66769.446391 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66622.663551 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66622.663551 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69130.634072 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69130.634072 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66622.663551 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67511.890464 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67110.583894 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66622.663551 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67511.890464 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67110.583894 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88530.133146 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88530.133146 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82629.818925 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82629.818925 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115034.377387 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115034.377387 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82629.818925 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96864.040356 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90440.160801 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82629.818925 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96864.040356 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90440.160801 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 84181 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 39645 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15035 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 41767 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 38188 # Transaction distribution @@ -874,7 +884,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4733 # Transaction distribution system.membus.trans_dist::ReadExReq 2854 # Transaction distribution system.membus.trans_dist::ReadExResp 2854 # Transaction distribution @@ -895,9 +905,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7587 # Request fanout histogram -system.membus.reqLayer0.occupancy 9083000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9082000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 40294250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40299000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index 7f3ecc8dc..3870e90de 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -172,7 +172,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -534,7 +534,7 @@ pipelined=true [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -666,7 +666,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -813,6 +813,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -824,7 +825,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -832,29 +833,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -874,6 +882,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -883,7 +892,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -905,9 +914,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index c5508bf05..5ac8e5d82 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:10:34 -gem5 executing on e108600-lin, pid 12223 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:51:10 +gem5 executing on e108600-lin, pid 17461 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -15,5 +15,5 @@ Eon, Version 1.1 info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. -OO-style eon Time= 0.110000 -Exiting @ tick 111753553500 because target called exit() +OO-style eon Time= 0.120000 +Exiting @ tick 122177531500 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 3bab29953..9802024db 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.120480 # Number of seconds simulated -sim_ticks 120480458500 # Number of ticks simulated -final_tick 120480458500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.122178 # Number of seconds simulated +sim_ticks 122177531500 # Number of ticks simulated +final_tick 122177531500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 129515 # Simulator instruction rate (inst/s) -host_op_rate 155497 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57149813 # Simulator tick rate (ticks/s) -host_mem_usage 293332 # Number of bytes of host memory used -host_seconds 2108.15 # Real time elapsed on the host +host_inst_rate 120262 # Simulator instruction rate (inst/s) +host_op_rate 144388 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53814187 # Simulator tick rate (ticks/s) +host_mem_usage 292180 # Number of bytes of host memory used +host_seconds 2270.36 # Real time elapsed on the host sim_insts 273037218 # Number of instructions simulated sim_ops 327811600 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1888064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 14651392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 167808 # Number of bytes read from this memory -system.physmem.bytes_read::total 16707264 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1888064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1888064 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 29501 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 228928 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 2622 # Number of read requests responded to by this memory -system.physmem.num_reads::total 261051 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 15671122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 121608037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 1392823 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 138671982 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 15671122 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 15671122 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 15671122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 121608037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 1392823 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 138671982 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 261052 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1888192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 14650048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 169280 # Number of bytes read from this memory +system.physmem.bytes_read::total 16707520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1888192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1888192 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 29503 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 228907 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2645 # Number of read requests responded to by this memory +system.physmem.num_reads::total 261055 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 15454495 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 119907874 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1385525 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 136747893 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 15454495 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 15454495 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 15454495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 119907874 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1385525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 136747893 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 261056 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 261052 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 261056 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 16707328 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 16707584 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 16707328 # Total read bytes from the system interface side +system.physmem.bytesReadSys 16707584 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1258 # Per bank write bursts +system.physmem.perBankRdBursts::0 1259 # Per bank write bursts system.physmem.perBankRdBursts::1 69992 # Per bank write bursts system.physmem.perBankRdBursts::2 1296 # Per bank write bursts -system.physmem.perBankRdBursts::3 10757 # Per bank write bursts +system.physmem.perBankRdBursts::3 10759 # Per bank write bursts system.physmem.perBankRdBursts::4 42908 # Per bank write bursts -system.physmem.perBankRdBursts::5 121820 # Per bank write bursts +system.physmem.perBankRdBursts::5 121819 # Per bank write bursts system.physmem.perBankRdBursts::6 160 # Per bank write bursts -system.physmem.perBankRdBursts::7 266 # Per bank write bursts -system.physmem.perBankRdBursts::8 224 # Per bank write bursts +system.physmem.perBankRdBursts::7 257 # Per bank write bursts +system.physmem.perBankRdBursts::8 228 # Per bank write bursts system.physmem.perBankRdBursts::9 562 # Per bank write bursts system.physmem.perBankRdBursts::10 7776 # Per bank write bursts system.physmem.perBankRdBursts::11 812 # Per bank write bursts system.physmem.perBankRdBursts::12 1213 # Per bank write bursts system.physmem.perBankRdBursts::13 743 # Per bank write bursts -system.physmem.perBankRdBursts::14 656 # Per bank write bursts -system.physmem.perBankRdBursts::15 609 # Per bank write bursts +system.physmem.perBankRdBursts::14 662 # Per bank write bursts +system.physmem.perBankRdBursts::15 610 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 120480449000 # Total gap between requests +system.physmem.totGap 122177522000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 261052 # Read request sizes (log2) +system.physmem.readPktSize::6 261056 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,20 +95,20 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 204297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 43283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12075 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 208 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 216 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 21 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 204133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 43349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 235 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 176 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -191,86 +191,96 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67045 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 249.160415 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 181.717328 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 205.520754 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18369 27.40% 27.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 21159 31.56% 58.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11457 17.09% 76.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6629 9.89% 85.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4618 6.89% 92.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2220 3.31% 96.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1372 2.05% 98.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 491 0.73% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 730 1.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67045 # Bytes accessed per row activation -system.physmem.totQLat 2500931533 # Total ticks spent queuing -system.physmem.totMemAccLat 7395656533 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1305260000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9580.20 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 67229 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 248.480388 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 181.727737 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 204.056429 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18253 27.15% 27.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 21438 31.89% 59.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11486 17.08% 76.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6691 9.95% 86.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4636 6.90% 92.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2199 3.27% 96.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1378 2.05% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 426 0.63% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 722 1.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67229 # Bytes accessed per row activation +system.physmem.totQLat 4621160381 # Total ticks spent queuing +system.physmem.totMemAccLat 9515960381 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1305280000 # Total ticks spent in databus transfers +system.physmem.avgQLat 17701.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28330.20 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 138.67 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 36451.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 136.75 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 138.67 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 136.75 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.08 # Data bus utilization in percentage -system.physmem.busUtilRead 1.08 # Data bus utilization in percentage for reads +system.physmem.busUtil 1.07 # Data bus utilization in percentage +system.physmem.busUtilRead 1.07 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.60 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 193998 # Number of row buffer hits during reads +system.physmem.readRowHits 193817 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.31 # Row buffer hit rate for reads +system.physmem.readRowHitRate 74.24 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 461518.97 # Average gap between requests -system.physmem.pageHitRate 74.31 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 469687680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 256278000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1937777400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 468012.69 # Average gap between requests +system.physmem.pageHitRate 74.24 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 445443180 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 236747280 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1773933000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 7868948880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 73664414550 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 7668236250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 91865342760 # Total energy per rank (pJ) -system.physmem_0.averagePower 762.514125 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 12350213739 # Time in different power states -system.physmem_0.memoryStateTime::REF 4022980000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 104104852261 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 37134720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 20262000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 98069400 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 9531222480.000002 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4632019500 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 224464800 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 45099806190 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 3562907040 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 919525950 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 66426265230 # Total energy per rank (pJ) +system.physmem_0.averagePower 543.686420 # Core power per rank (mW) +system.physmem_0.totalIdleTime 111434381144 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 154081000 # Time in different power states +system.physmem_0.memoryStateTime::REF 4033332000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 3253133750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 9278182481 # Time in different power states +system.physmem_0.memoryStateTime::ACT 6555604606 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 98903197663 # Time in different power states +system.physmem_1.actEnergy 34636140 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 18382980 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 89999700 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 7868948880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 16939770435 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 57426696000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 82390881435 # Total energy per rank (pJ) -system.physmem_1.averagePower 683.872818 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 95444315624 # Time in different power states -system.physmem_1.memoryStateTime::REF 4022980000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 21009739880 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 35971487 # Number of BP lookups -system.cpu.branchPred.condPredicted 19266966 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 984300 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17894295 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13923321 # Number of BTB hits +system.physmem_1.refreshEnergy 3038165520.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 716380560 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 121415040 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 10108537890 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 3723173760 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 21583783695 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 39434924925 # Total energy per rank (pJ) +system.physmem_1.averagePower 322.767403 # Core power per rank (mW) +system.physmem_1.totalIdleTime 120289757500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 194586000 # Time in different power states +system.physmem_1.memoryStateTime::REF 1289158000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 88425719250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 9695988513 # Time in different power states +system.physmem_1.memoryStateTime::ACT 404030000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 22168049737 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 35971486 # Number of BP lookups +system.cpu.branchPred.condPredicted 19267078 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 984296 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17894197 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13923261 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 77.808715 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6951891 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 77.808806 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6951889 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4417 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2517210 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 2517219 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 2473355 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 43855 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 128902 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectMisses 43864 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 128904 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -300,7 +310,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -330,7 +340,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -360,7 +370,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -391,97 +401,97 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 120480458500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 240960918 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 122177531500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 244355064 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12852393 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 309387545 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35971487 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23348567 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 224289895 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1990323 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1871 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 12854090 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 309386185 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35971486 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23348505 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 227028352 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1990311 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1601 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 93 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3026 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 82204082 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 34266 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 238142439 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.562665 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.293284 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3162 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 82203694 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 34298 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 240882453 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.544883 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.296552 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 77933727 32.73% 32.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 40203358 16.88% 49.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 28082672 11.79% 61.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 91922682 38.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 80675861 33.49% 33.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 40201773 16.69% 50.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 28081031 11.66% 61.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 91923788 38.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 238142439 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.149283 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.283974 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 26809492 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 87975457 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 98235303 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 24260898 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 861289 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6686645 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 134215 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 348536073 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3411178 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 861289 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 43087679 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 34729777 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 287359 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 105264108 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 53912227 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 344595535 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1451317 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 7117459 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 85486 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7456793 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 27429966 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 3277218 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 394867605 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2218081796 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 335910446 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 192911530 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 240882453 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.147210 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.266134 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 26812973 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 90710528 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 98252382 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 24245286 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 861284 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6686689 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 134210 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 348538542 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3411137 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 861284 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 43083632 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37000044 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 289266 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 105269732 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 54378495 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 344597413 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1451618 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7112089 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 85489 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7460814 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 27903739 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 3277402 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 394869828 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2218091968 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 335911643 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 192912802 # Number of floating rename lookups system.cpu.rename.CommittedMaps 372230048 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22637557 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 22639780 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 11606 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11573 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 57394706 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89984018 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 84392471 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1976841 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1898355 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 343274386 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22623 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 339465004 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 967637 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 15485409 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 37250778 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 503 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 238142439 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.425470 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.136916 # Number of insts issued each cycle +system.cpu.rename.tempSerializingInsts 11574 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 57375410 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89984183 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 84392474 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1977179 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1898949 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343275804 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22622 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 339466020 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 967573 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 15486826 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 37253539 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 502 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 240882453 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.409260 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.140571 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 57979720 24.35% 24.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 76155774 31.98% 56.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 59457503 24.97% 81.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34550396 14.51% 95.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9286722 3.90% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 677796 0.28% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34528 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 60724616 25.21% 25.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 76160793 31.62% 56.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 59430978 24.67% 81.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34569007 14.35% 95.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9283720 3.85% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 678664 0.28% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34675 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 238142439 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 240882453 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9217758 7.75% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7319 0.01% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9218221 7.75% 7.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7322 0.01% 7.76% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 7.76% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.76% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.76% # attempts to use FU when none available @@ -500,22 +510,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.76% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 7.76% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.76% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 238781 0.20% 7.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 238834 0.20% 7.96% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 138932 0.12% 8.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 70694 0.06% 8.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 68373 0.06% 8.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 637081 0.54% 8.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 296736 0.25% 8.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 541785 0.46% 9.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 51510154 43.32% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 56187310 47.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 138891 0.12% 8.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 70679 0.06% 8.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 68365 0.06% 8.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 640804 0.54% 8.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 296732 0.25% 8.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 541759 0.46% 9.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 51504063 43.31% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 56187426 47.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 108183295 31.87% 31.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148337 0.63% 32.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 108184064 31.87% 31.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148340 0.63% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.50% # Type of FU issued @@ -534,91 +544,91 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.50% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6792696 2.00% 34.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6792701 2.00% 34.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8634939 2.54% 37.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3210556 0.95% 37.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8634973 2.54% 37.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3210554 0.95% 37.99% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1592986 0.47% 38.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20863290 6.15% 44.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7179112 2.11% 46.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7141893 2.10% 48.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20863316 6.15% 44.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7179113 2.11% 46.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7141894 2.10% 48.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 175297 0.05% 48.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 90024001 26.52% 75.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 83518602 24.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 90024187 26.52% 75.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 83518595 24.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 339465004 # Type of FU issued -system.cpu.iq.rate 1.408797 # Inst issue rate -system.cpu.iq.fu_busy_cnt 118914923 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.350301 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 753593457 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 235149136 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 219170609 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 283361550 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 123645361 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 116917491 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 293630516 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 164749411 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5409371 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 339466020 # Type of FU issued +system.cpu.iq.rate 1.389233 # Inst issue rate +system.cpu.iq.fu_busy_cnt 118913096 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.350295 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 756328552 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 235151256 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 219171646 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 283366610 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 123646075 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 116917582 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 293624810 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 164754306 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5408815 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4251743 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7382 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 4251908 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7378 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12082 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2016854 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 2016857 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 126951 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 613385 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 126936 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 613330 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 861289 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1346418 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1223561 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 343298428 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 861284 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1350225 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1508994 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343299844 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89984018 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 84392471 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11590 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7654 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1216581 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewDispLoadInsts 89984183 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 84392474 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11589 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 7652 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1502014 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 12082 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 438027 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 454511 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 892538 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 337435973 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 89435470 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2029031 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 438026 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 454508 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 892534 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 337437017 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 89435625 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2029003 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1419 # number of nop insts executed -system.cpu.iew.exec_refs 172563167 # number of memory reference insts executed -system.cpu.iew.exec_branches 31555788 # Number of branches executed -system.cpu.iew.exec_stores 83127697 # Number of stores executed -system.cpu.iew.exec_rate 1.400376 # Inst execution rate -system.cpu.iew.wb_sent 336234414 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 336088100 # cumulative count of insts written-back -system.cpu.iew.wb_producers 151781597 # num instructions producing a value -system.cpu.iew.wb_consumers 263546089 # num instructions consuming a value -system.cpu.iew.wb_rate 1.394783 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.575921 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 14163176 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1418 # number of nop insts executed +system.cpu.iew.exec_refs 172563316 # number of memory reference insts executed +system.cpu.iew.exec_branches 31556143 # Number of branches executed +system.cpu.iew.exec_stores 83127691 # Number of stores executed +system.cpu.iew.exec_rate 1.380929 # Inst execution rate +system.cpu.iew.wb_sent 336235772 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 336089228 # cumulative count of insts written-back +system.cpu.iew.wb_producers 151786231 # num instructions producing a value +system.cpu.iew.wb_consumers 263562514 # num instructions consuming a value +system.cpu.iew.wb_rate 1.375413 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.575902 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 14164375 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 850428 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 235953046 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.389311 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.042233 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 850425 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 238692959 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.373364 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.035708 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 104793604 44.41% 44.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 67594704 28.65% 73.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 20883417 8.85% 81.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13239055 5.61% 87.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8655759 3.67% 91.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4517031 1.91% 93.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3019754 1.28% 94.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2590982 1.10% 95.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10658740 4.52% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 107534765 45.05% 45.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 67583251 28.31% 73.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 20880103 8.75% 82.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13256001 5.55% 87.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8658859 3.63% 91.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4515867 1.89% 93.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3014415 1.26% 94.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2598093 1.09% 95.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10651605 4.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 235953046 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 238692959 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037830 # Number of instructions committed system.cpu.commit.committedOps 327812212 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -664,96 +674,96 @@ system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 327812212 # Class of committed instruction -system.cpu.commit.bw_lim_events 10658740 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 567267171 # The number of ROB reads -system.cpu.rob.rob_writes 686142351 # The number of ROB writes -system.cpu.timesIdled 39413 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2818479 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 10651605 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 570015418 # The number of ROB reads +system.cpu.rob.rob_writes 686144847 # The number of ROB writes +system.cpu.timesIdled 39403 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3472611 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273037218 # Number of Instructions Simulated system.cpu.committedOps 327811600 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.882520 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.882520 # CPI: Total CPI of All Threads -system.cpu.ipc 1.133118 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.133118 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 325162337 # number of integer regfile reads -system.cpu.int_regfile_writes 134093699 # number of integer regfile writes -system.cpu.fp_regfile_reads 186638060 # number of floating regfile reads -system.cpu.fp_regfile_writes 131662989 # number of floating regfile writes -system.cpu.cc_regfile_reads 1279404689 # number of cc regfile reads -system.cpu.cc_regfile_writes 80058303 # number of cc regfile writes -system.cpu.misc_regfile_reads 1056730531 # number of misc regfile reads +system.cpu.cpi 0.894951 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.894951 # CPI: Total CPI of All Threads +system.cpu.ipc 1.117379 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.117379 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 325163205 # number of integer regfile reads +system.cpu.int_regfile_writes 134094196 # number of integer regfile writes +system.cpu.fp_regfile_reads 186638267 # number of floating regfile reads +system.cpu.fp_regfile_writes 131663703 # number of floating regfile writes +system.cpu.cc_regfile_reads 1279409265 # number of cc regfile reads +system.cpu.cc_regfile_writes 80058845 # number of cc regfile writes +system.cpu.misc_regfile_reads 1056731782 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1542807 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.846983 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 162052499 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1543319 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 105.002594 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 87321000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.846983 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999701 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999701 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1542799 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.841241 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 162053309 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1543311 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 105.003664 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 91635000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.841241 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999690 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999690 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 333478959 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 333478959 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 81039652 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 81039652 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80921351 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80921351 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 69633 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 69633 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 333480485 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 333480485 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 81040424 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 81040424 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80921391 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80921391 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 69631 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 69631 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10908 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10908 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 161961003 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 161961003 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 162030636 # number of overall hits -system.cpu.dcache.overall_hits::total 162030636 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2784011 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2784011 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1131348 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1131348 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 161961815 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 161961815 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 162031446 # number of overall hits +system.cpu.dcache.overall_hits::total 162031446 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2784008 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2784008 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1131308 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1131308 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3915359 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3915359 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3915377 # number of overall misses -system.cpu.dcache.overall_misses::total 3915377 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 45256653500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 45256653500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9138834402 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9138834402 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 184000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 54395487902 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 54395487902 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 54395487902 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 54395487902 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 83823663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 83823663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3915316 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3915316 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3915334 # number of overall misses +system.cpu.dcache.overall_misses::total 3915334 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 47872980500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 47872980500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9172353414 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9172353414 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 194000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 194000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 57045333914 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 57045333914 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 57045333914 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 57045333914 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 83824432 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 83824432 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 69651 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 69651 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 69649 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 69649 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10912 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10912 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 165876362 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 165876362 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 165946013 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 165946013 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033213 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.033213 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 165877131 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 165877131 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 165946780 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 165946780 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033212 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.033212 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013788 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.013788 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000258 # miss rate for SoftPFReq accesses @@ -764,54 +774,54 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.023604 system.cpu.dcache.demand_miss_rate::total 0.023604 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.023594 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.023594 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16255.917631 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16255.917631 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8077.827867 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8077.827867 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 46000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 46000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13892.848115 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13892.848115 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13892.784246 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13892.784246 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.705077 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.705077 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8107.742024 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8107.742024 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14569.790513 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14569.790513 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14569.723532 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14569.723532 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1086145 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1090477 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 136219 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 136210 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7.973521 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1542807 # number of writebacks -system.cpu.dcache.writebacks::total 1542807 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1461430 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1461430 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910604 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 910604 # number of WriteReq MSHR hits +system.cpu.dcache.avg_blocked_cycles::no_targets 8.005851 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 1542799 # number of writebacks +system.cpu.dcache.writebacks::total 1542799 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1461435 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1461435 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910564 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 910564 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2372034 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2372034 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2372034 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2372034 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322581 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1322581 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 2371999 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2371999 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2371999 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2371999 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322573 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1322573 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220744 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 220744 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1543325 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1543325 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1543336 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1543336 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25407816000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 25407816000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1834277181 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1834277181 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 705000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 705000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27242093181 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27242093181 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27242798181 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27242798181 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1543317 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1543317 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1543328 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1543328 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27142024000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27142024000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1845028694 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1845028694 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1269000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1269000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28987052694 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28987052694 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28988321694 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28988321694 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015778 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015778 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002690 # mshr miss rate for WriteReq accesses @@ -822,26 +832,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009304 system.cpu.dcache.demand_mshr_miss_rate::total 0.009304 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009300 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.009300 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19210.782553 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19210.782553 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8309.522257 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8309.522257 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 64090.909091 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 64090.909091 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17651.559575 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17651.559575 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17651.890568 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17651.890568 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 725593 # number of replacements -system.cpu.icache.tags.tagsinuse 511.815316 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 81471161 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 726105 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 112.203002 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 334835500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.815316 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999639 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999639 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20522.136774 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20522.136774 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8358.228056 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8358.228056 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 115363.636364 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 115363.636364 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18782.306353 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18782.306353 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18782.994732 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18782.994732 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 725588 # number of replacements +system.cpu.icache.tags.tagsinuse 511.809147 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 81470653 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 726100 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 112.203075 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 346654500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.809147 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999627 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999627 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id @@ -849,369 +859,370 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 243 system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 70 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 165134244 # Number of tag accesses -system.cpu.icache.tags.data_accesses 165134244 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 81471161 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 81471161 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 81471161 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 81471161 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 81471161 # number of overall hits -system.cpu.icache.overall_hits::total 81471161 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 732901 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 732901 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 732901 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 732901 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 732901 # number of overall misses -system.cpu.icache.overall_misses::total 732901 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 8031652441 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 8031652441 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 8031652441 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 8031652441 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 8031652441 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 8031652441 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 82204062 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 82204062 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 82204062 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 82204062 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 82204062 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 82204062 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008916 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008916 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008916 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008916 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008916 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008916 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10958.713989 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10958.713989 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10958.713989 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10958.713989 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10958.713989 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10958.713989 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 128534 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 100 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4274 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 165133459 # Number of tag accesses +system.cpu.icache.tags.data_accesses 165133459 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 81470653 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 81470653 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 81470653 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 81470653 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 81470653 # number of overall hits +system.cpu.icache.overall_hits::total 81470653 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 733019 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 733019 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 733019 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 733019 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 733019 # number of overall misses +system.cpu.icache.overall_misses::total 733019 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 8417582442 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 8417582442 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 8417582442 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 8417582442 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 8417582442 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 8417582442 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 82203672 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 82203672 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 82203672 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 82203672 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 82203672 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 82203672 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008917 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008917 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008917 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008917 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008917 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008917 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11483.443733 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 11483.443733 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 11483.443733 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 11483.443733 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 11483.443733 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 11483.443733 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 142274 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 124 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4376 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 30.073467 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 33.333333 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 725593 # number of writebacks -system.cpu.icache.writebacks::total 725593 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 6780 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 6780 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 6780 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 6780 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 6780 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 6780 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726121 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 726121 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 726121 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 726121 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 726121 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 726121 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7527879949 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 7527879949 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7527879949 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 7527879949 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7527879949 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 7527879949 # number of overall MSHR miss cycles +system.cpu.icache.avg_blocked_cycles::no_mshrs 32.512340 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 41.333333 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 725588 # number of writebacks +system.cpu.icache.writebacks::total 725588 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 6903 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 6903 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 6903 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 6903 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 6903 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 6903 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726116 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 726116 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 726116 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 726116 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 726116 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 726116 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7892899950 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 7892899950 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7892899950 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 7892899950 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7892899950 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 7892899950 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008833 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.008833 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.008833 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10367.252771 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10367.252771 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10367.252771 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 10367.252771 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10367.252771 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 10367.252771 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 402848 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 402975 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 113 # number of redundant prefetches already in prefetch queue +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10870.026208 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10870.026208 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10870.026208 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 10870.026208 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10870.026208 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 10870.026208 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 404432 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 404544 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 102 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 27937 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.pfSpanPage 28328 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 5253.562311 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1811987 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 6314 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 286.979252 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 5246.342429 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1813751 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 6313 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 287.304134 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 5154.206528 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 99.355783 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.314588 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006064 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.320652 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 5152.962075 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 93.380354 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.314512 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005699 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.320211 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1022 192 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 6122 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 12 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 6121 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::2 48 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 110 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 555 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1137 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 139 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4125 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 3 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 103 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 162 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 554 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1140 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 141 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4124 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011719 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.373657 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 70548606 # 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number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2449507500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16699402500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19148910000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2449507500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16699402500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 206471258 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19355381258 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.941176 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.941176 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003429 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003429 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040634 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040634 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172520 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172520 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040634 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148335 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.113878 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040634 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148335 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003307 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003307 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040637 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040637 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172525 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172525 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040637 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148322 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.113870 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040637 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148322 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.137742 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3466.834961 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3466.834961 # average HardPFReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.137871 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3790.758771 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3790.758771 # average HardPFReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15687.500000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15687.500000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70429.326288 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70429.326288 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70655.328452 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70655.328452 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65303.035881 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65303.035881 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70655.328452 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65319.987070 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65929.062028 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70655.328452 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65319.987070 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3466.834961 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55107.220969 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4537857 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2268434 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254467 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 51535 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51534 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88424.657534 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88424.657534 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 83022.895201 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 83022.895201 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72903.283416 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72903.283416 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83022.895201 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72952.782134 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74102.534335 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83022.895201 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72952.782134 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3790.758771 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61862.391277 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4537831 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2268421 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254469 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 51822 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51821 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 2048700 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 968253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1300147 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 55525 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 2048687 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 968244 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1300143 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 55841 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 220739 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 220739 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 726121 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322580 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2177753 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629479 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6807232 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92904448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197512064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 290416512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 55606 # Total snoops (count) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 726116 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322572 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2177738 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629455 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6807193 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92903808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197511040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 290414848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 55922 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 5184 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2324982 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.131629 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.338088 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 2325285 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.131736 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.338205 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2018948 86.84% 86.84% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 306033 13.16% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2018962 86.83% 86.83% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 306322 13.17% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2324982 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4537328500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 3.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1089458442 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2325285 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4537302500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 3.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1089460423 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2315007958 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2314997455 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 261068 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 253748 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 261072 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 253753 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 260294 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 260325 # Transaction distribution system.membus.trans_dist::UpgradeReq 16 # Transaction distribution -system.membus.trans_dist::ReadExReq 757 # Transaction distribution -system.membus.trans_dist::ReadExResp 757 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 260295 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522119 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 522119 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16707264 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 16707264 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 730 # Transaction distribution +system.membus.trans_dist::ReadExResp 730 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 260326 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522127 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 522127 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16707520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 16707520 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 261068 # Request fanout histogram +system.membus.snoop_fanout::samples 261072 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 261068 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 261072 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 261068 # Request fanout histogram -system.membus.reqLayer0.occupancy 329929457 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 261072 # Request fanout histogram +system.membus.reqLayer0.occupancy 329884354 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1377865586 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1377672131 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |