diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-30 03:42:27 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-30 03:42:27 -0400 |
| commit | d8f732273ecda73122ad3ba184e358ed265fa875 (patch) | |
| tree | 6ef605febd4e2299d75d76897386ff4ad7288fec /tests/long/se/30.eon | |
| parent | 6fac40ceb03d4ab5b13affac3927cd876947cc78 (diff) | |
| download | gem5-d8f732273ecda73122ad3ba184e358ed265fa875.tar.xz | |
stats: Update stats for clean eviction addition
Diffstat (limited to 'tests/long/se/30.eon')
| -rw-r--r-- | tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt | 1144 |
1 files changed, 572 insertions, 572 deletions
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 8a385b77d..c456278d9 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.112686 # Number of seconds simulated -sim_ticks 112686104500 # Number of ticks simulated -final_tick 112686104500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.112687 # Number of seconds simulated +sim_ticks 112687034500 # Number of ticks simulated +final_tick 112687034500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125538 # Simulator instruction rate (inst/s) -host_op_rate 150722 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51811162 # Simulator tick rate (ticks/s) -host_mem_usage 327864 # Number of bytes of host memory used -host_seconds 2174.94 # Real time elapsed on the host +host_inst_rate 126437 # Simulator instruction rate (inst/s) +host_op_rate 151802 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52182660 # Simulator tick rate (ticks/s) +host_mem_usage 327844 # Number of bytes of host memory used +host_seconds 2159.47 # Real time elapsed on the host sim_insts 273037220 # Number of instructions simulated sim_ops 327811602 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 187072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 112896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 167936 # Number of bytes read from this memory -system.physmem.bytes_read::total 467904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 169152 # Number of bytes read from this memory +system.physmem.bytes_read::total 468672 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 187072 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 187072 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 2923 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1764 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 2624 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7311 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1660116 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1001863 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 1490299 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4152278 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1660116 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1660116 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1660116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1001863 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 1490299 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4152278 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7311 # Number of read requests accepted +system.physmem.num_reads::cpu.data 1757 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2643 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7323 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1660102 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 997879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1501078 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4159059 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1660102 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1660102 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1660102 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 997879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1501078 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4159059 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7323 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7311 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7323 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 467904 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 468672 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 467904 # Total read bytes from the system interface side +system.physmem.bytesReadSys 468672 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -52,7 +52,7 @@ system.physmem.perBankRdBursts::3 520 # Pe system.physmem.perBankRdBursts::4 444 # Per bank write bursts system.physmem.perBankRdBursts::5 346 # Per bank write bursts system.physmem.perBankRdBursts::6 153 # Per bank write bursts -system.physmem.perBankRdBursts::7 252 # Per bank write bursts +system.physmem.perBankRdBursts::7 251 # Per bank write bursts system.physmem.perBankRdBursts::8 219 # Per bank write bursts system.physmem.perBankRdBursts::9 290 # Per bank write bursts system.physmem.perBankRdBursts::10 315 # Per bank write bursts @@ -60,7 +60,7 @@ system.physmem.perBankRdBursts::11 411 # Pe system.physmem.perBankRdBursts::12 547 # Per bank write bursts system.physmem.perBankRdBursts::13 678 # Per bank write bursts system.physmem.perBankRdBursts::14 615 # Per bank write bursts -system.physmem.perBankRdBursts::15 542 # Per bank write bursts +system.physmem.perBankRdBursts::15 555 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 112685946000 # Total gap between requests +system.physmem.totGap 112686876000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7311 # Read request sizes (log2) +system.physmem.readPktSize::6 7323 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,21 +94,21 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3986 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1457 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4012 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1463 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 466 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 286 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 198 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 66 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 170 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 170 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 54 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -190,79 +190,79 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1367 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 340.646672 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 198.022122 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 348.529599 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 486 35.55% 35.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 298 21.80% 57.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 139 10.17% 67.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 76 5.56% 73.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 63 4.61% 77.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 51 3.73% 81.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 27 1.98% 83.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 26 1.90% 85.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 201 14.70% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1367 # Bytes accessed per row activation -system.physmem.totQLat 102208518 # Total ticks spent queuing -system.physmem.totMemAccLat 239289768 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 36555000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13980.10 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1371 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 339.932896 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 197.349943 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 349.457617 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 486 35.45% 35.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 309 22.54% 57.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 132 9.63% 67.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 75 5.47% 73.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 64 4.67% 77.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 48 3.50% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 26 1.90% 83.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 25 1.82% 84.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 206 15.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1371 # Bytes accessed per row activation +system.physmem.totQLat 95174041 # Total ticks spent queuing +system.physmem.totMemAccLat 232480291 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36615000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12996.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32730.10 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.15 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31746.59 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.15 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.16 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.49 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.45 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5935 # Number of row buffer hits during reads +system.physmem.readRowHits 5943 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.18 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.16 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 15413205.58 # Average gap between requests -system.physmem.pageHitRate 81.18 # Row buffer hit rate, read and write combined +system.physmem.avgGap 15388075.38 # Average gap between requests +system.physmem.pageHitRate 81.16 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 4815720 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 2627625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 28657200 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 28641600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 7359880320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3231673425 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 64774920750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 75402575040 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.157389 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 107755851914 # Time in different power states +system.physmem_0.actBackEnergy 3233168820 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 64773630750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 75402764835 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.158858 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 107753956620 # Time in different power states system.physmem_0.memoryStateTime::REF 3762720000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1164613086 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1166688380 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5496120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2998875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 28064400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 5526360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3015375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 28126800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 7359880320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3295137510 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 64719250500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 75410827725 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.230627 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 107661884129 # Time in different power states +system.physmem_1.actBackEnergy 3309876000 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 64706325000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 75412749855 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.247655 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 107640832624 # Time in different power states system.physmem_1.memoryStateTime::REF 3762720000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1258279621 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1279848380 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 37742989 # Number of BP lookups -system.cpu.branchPred.condPredicted 20164516 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1746156 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18663196 # Number of BTB lookups -system.cpu.branchPred.BTBHits 17299233 # Number of BTB hits +system.cpu.branchPred.lookups 37743135 # Number of BP lookups +system.cpu.branchPred.condPredicted 20164607 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1746155 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18663607 # Number of BTB lookups +system.cpu.branchPred.BTBHits 17299273 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.691697 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7223653 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3816 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.689870 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7223670 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,95 +381,95 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 225372210 # number of cpu cycles simulated +system.cpu.numCycles 225374070 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12439138 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 334051202 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37742989 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24522886 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 210855691 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3510707 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1284 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 2593 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 89092155 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 21708 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 225054059 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.800470 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.229417 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12439227 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 334051995 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37743135 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24522943 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 210854521 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3510703 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1310 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 2474 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 89092353 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 21704 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 225052883 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.800484 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.229411 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 51374086 22.83% 22.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42891136 19.06% 41.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 30054592 13.35% 55.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 100734245 44.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 51372314 22.83% 22.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42891452 19.06% 41.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 30054577 13.35% 55.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 100734540 44.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 225054059 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.167470 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.482220 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 27837229 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63912010 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108618315 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 23065911 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1620594 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6880048 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 135198 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 363546099 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 6169805 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1620594 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 45200014 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 17874059 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 342377 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 113380979 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 46636036 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 355768136 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 2890465 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 6610669 # Number of times rename has blocked due to ROB full +system.cpu.fetch.rateDist::total 225052883 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.167469 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.482211 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 27836779 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63911722 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108618516 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 23065273 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1620593 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6880055 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 135197 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 363544847 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6170021 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1620593 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 45199707 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 17872689 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 341815 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 113380410 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 46637669 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 355768309 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 2890306 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 6609751 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 177931 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7803674 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 21223053 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 2890533 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 403406015 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2534023592 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 350247327 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 194894263 # Number of floating rename lookups +system.cpu.rename.LQFullEvents 7804271 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 21223751 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 2890543 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 403406246 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2534025265 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 350247395 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 194894231 # Number of floating rename lookups system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31175964 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 31176195 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 17016 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 17025 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 55505783 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 92416404 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 88498336 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1661010 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1846418 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 353252226 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 55506509 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 92416612 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 88498373 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1661373 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1847329 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 353252571 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 28026 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 346438238 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 2301579 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 25468650 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 73725461 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 346438287 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 2302047 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 25468995 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 73729207 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 5906 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 225054059 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.539356 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.099855 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 225052883 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.539364 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.099868 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 40665072 18.07% 18.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 78300215 34.79% 52.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 60997700 27.10% 79.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34882254 15.50% 95.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9557051 4.25% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 642945 0.29% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8822 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 40665148 18.07% 18.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 78299865 34.79% 52.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 60995131 27.10% 79.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34883362 15.50% 95.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9557615 4.25% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 642958 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8804 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 225054059 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 225052883 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9490410 7.63% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7314 0.01% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9490613 7.63% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7317 0.01% 7.64% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 7.64% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.64% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.64% # attempts to use FU when none available @@ -488,22 +488,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.64% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 7.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 255762 0.21% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 255761 0.21% 7.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 126866 0.10% 7.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 93218 0.07% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 126865 0.10% 7.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 93219 0.07% 8.02% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 68015 0.05% 8.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 721741 0.58% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 297231 0.24% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 683043 0.55% 9.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 721837 0.58% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 297231 0.24% 8.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 683044 0.55% 9.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 53642366 43.14% 52.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 58960700 47.42% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 53642383 43.14% 52.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 58959382 47.42% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 110655140 31.94% 31.94% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148362 0.62% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 110655137 31.94% 31.94% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148355 0.62% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.56% # Type of FU issued @@ -522,93 +522,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.56% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6798396 1.96% 34.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6798397 1.96% 34.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8668155 2.50% 37.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3332481 0.96% 37.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8668117 2.50% 37.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3332482 0.96% 37.99% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1592458 0.46% 38.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20930094 6.04% 44.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7182326 2.07% 46.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20930149 6.04% 44.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7182320 2.07% 46.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 7148962 2.06% 48.63% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 91923219 26.53% 75.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 85883359 24.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 91923270 26.53% 75.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 85883354 24.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 346438238 # Type of FU issued -system.cpu.iq.rate 1.537183 # Inst issue rate -system.cpu.iq.fu_busy_cnt 124346666 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.358929 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 757024395 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 251740362 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 223260150 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 287554385 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 127018791 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 117424955 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 303230405 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 167554499 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5064919 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 346438287 # Type of FU issued +system.cpu.iq.rate 1.537170 # Inst issue rate +system.cpu.iq.fu_busy_cnt 124345667 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.358926 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 757022758 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 251740405 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 223260402 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 287554413 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 127019437 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 117424930 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 303229780 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 167554174 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5064825 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6684129 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13573 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 10255 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6122719 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6684337 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13570 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 10254 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6122756 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 155303 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 607776 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 155338 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 607759 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1620594 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2118849 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 332046 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 353281117 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 1620593 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2118874 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 332196 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 353281462 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 92416404 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 88498336 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 92416612 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 88498373 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 16993 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 8049 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 338505 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 10255 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1220656 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 439058 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1659714 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 342448377 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 90703712 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3989861 # Number of squashed instructions skipped in execute +system.cpu.iew.iewLSQFullEvents 338656 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 10254 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1220664 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 439075 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1659739 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 342448688 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 90703769 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3989599 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 865 # number of nop insts executed -system.cpu.iew.exec_refs 175291126 # number of memory reference insts executed -system.cpu.iew.exec_branches 31752707 # Number of branches executed -system.cpu.iew.exec_stores 84587414 # Number of stores executed -system.cpu.iew.exec_rate 1.519479 # Inst execution rate -system.cpu.iew.wb_sent 340943800 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 340685105 # cumulative count of insts written-back -system.cpu.iew.wb_producers 153662327 # num instructions producing a value -system.cpu.iew.wb_consumers 266738216 # num instructions consuming a value +system.cpu.iew.exec_refs 175291174 # number of memory reference insts executed +system.cpu.iew.exec_branches 31752726 # Number of branches executed +system.cpu.iew.exec_stores 84587405 # Number of stores executed +system.cpu.iew.exec_rate 1.519468 # Inst execution rate +system.cpu.iew.wb_sent 340944051 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 340685332 # cumulative count of insts written-back +system.cpu.iew.wb_producers 153662647 # num instructions producing a value +system.cpu.iew.wb_consumers 266737544 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.511655 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.576079 # average fanout of values written-back +system.cpu.iew.wb_rate 1.511644 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.576082 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23082519 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23083260 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1611397 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 221328864 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.481109 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.050764 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 221327720 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.481117 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.050757 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 87530154 39.55% 39.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 70479011 31.84% 71.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 20814829 9.40% 80.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13433176 6.07% 86.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8801116 3.98% 90.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4514131 2.04% 92.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2986629 1.35% 94.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2449420 1.11% 95.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10320398 4.66% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 87528718 39.55% 39.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 70478843 31.84% 71.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 20814822 9.40% 80.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13433890 6.07% 86.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8801339 3.98% 90.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4513701 2.04% 92.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2986759 1.35% 94.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2449542 1.11% 95.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10320106 4.66% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 221328864 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 221327720 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037832 # Number of instructions committed system.cpu.commit.committedOps 327812214 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -654,92 +654,92 @@ system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 327812214 # Class of committed instruction -system.cpu.commit.bw_lim_events 10320398 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 561900676 # The number of ROB reads -system.cpu.rob.rob_writes 705518580 # The number of ROB writes -system.cpu.timesIdled 50864 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 318151 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 10320106 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 561900565 # The number of ROB reads +system.cpu.rob.rob_writes 705520050 # The number of ROB writes +system.cpu.timesIdled 50865 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 321187 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273037220 # Number of Instructions Simulated system.cpu.committedOps 327811602 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.825427 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.825427 # CPI: Total CPI of All Threads -system.cpu.ipc 1.211495 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.211495 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 331331443 # number of integer regfile reads -system.cpu.int_regfile_writes 136939322 # number of integer regfile writes -system.cpu.fp_regfile_reads 187108010 # number of floating regfile reads -system.cpu.fp_regfile_writes 132178699 # number of floating regfile writes -system.cpu.cc_regfile_reads 1297132712 # number of cc regfile reads -system.cpu.cc_regfile_writes 80241070 # number of cc regfile writes -system.cpu.misc_regfile_reads 1183128145 # number of misc regfile reads +system.cpu.cpi 0.825434 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.825434 # CPI: Total CPI of All Threads +system.cpu.ipc 1.211485 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.211485 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 331332035 # number of integer regfile reads +system.cpu.int_regfile_writes 136939352 # number of integer regfile writes +system.cpu.fp_regfile_reads 187107868 # number of floating regfile reads +system.cpu.fp_regfile_writes 132178738 # number of floating regfile writes +system.cpu.cc_regfile_reads 1297133606 # number of cc regfile reads +system.cpu.cc_regfile_writes 80241640 # number of cc regfile writes +system.cpu.misc_regfile_reads 1183127847 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes system.cpu.dcache.tags.replacements 1533845 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.844014 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 163642665 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 511.843427 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 163642817 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1534357 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 106.652275 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 82317000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.844014 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999695 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999695 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 106.652374 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 82681000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.843427 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999694 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999694 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336636785 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336636785 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 82609327 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 82609327 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80941037 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80941037 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 70495 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 70495 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 336637061 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336637061 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 82609464 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 82609464 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80941053 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80941053 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 70494 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 70494 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 163550364 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 163550364 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 163620859 # number of overall hits -system.cpu.dcache.overall_hits::total 163620859 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2796866 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2796866 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1111662 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1111662 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 163550517 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 163550517 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 163621011 # number of overall hits +system.cpu.dcache.overall_hits::total 163621011 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2796868 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2796868 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1111646 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1111646 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3908528 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3908528 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3908546 # number of overall misses -system.cpu.dcache.overall_misses::total 3908546 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 22404027000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 22404027000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8967503998 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8967503998 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3908514 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3908514 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3908532 # number of overall misses +system.cpu.dcache.overall_misses::total 3908532 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 22403262000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 22403262000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8965991000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8965991000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 189000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31371530998 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31371530998 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31371530998 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31371530998 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 85406193 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 85406193 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 31369253000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31369253000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31369253000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31369253000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 85406332 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 85406332 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 70513 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 70513 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 70512 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 70512 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 167458892 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 167458892 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 167529405 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 167529405 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 167459031 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 167459031 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 167529543 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 167529543 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032748 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.032748 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013548 # miss rate for WriteReq accesses @@ -750,38 +750,38 @@ system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.023340 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.023340 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023331 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023331 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8010.404145 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 8010.404145 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8066.754102 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8066.754102 # average WriteReq miss latency +system.cpu.dcache.overall_miss_rate::cpu.data 0.023330 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023330 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8010.124897 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 8010.124897 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8065.509164 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8065.509164 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37800 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37800 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 8026.431178 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 8026.431178 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 8026.394214 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 8026.394214 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 8025.877098 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 8025.877098 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 8025.840136 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 8025.840136 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1059827 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1060412 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 134751 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 134750 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7.865077 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7.869477 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 966339 # number of writebacks system.cpu.dcache.writebacks::total 966339 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1483173 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1483173 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 891007 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 891007 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1483175 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1483175 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 890991 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 890991 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2374180 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2374180 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2374180 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2374180 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2374166 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2374166 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2374166 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2374166 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313693 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1313693 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220655 # number of WriteReq MSHR misses @@ -792,16 +792,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1534348 system.cpu.dcache.demand_mshr_misses::total 1534348 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1534359 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1534359 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10622731000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10622731000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1827670779 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1827670779 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10623648000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10623648000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1826747781 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1826747781 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 681000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 681000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12450401779 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12450401779 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12451082779 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12451082779 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12450395781 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12450395781 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12451076781 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12451076781 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015382 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015382 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002689 # mshr miss rate for WriteReq accesses @@ -812,26 +812,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009163 system.cpu.dcache.demand_mshr_miss_rate::total 0.009163 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009159 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.009159 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8086.159399 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8086.159399 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8282.933897 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8282.933897 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8086.857432 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8086.857432 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8278.750905 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8278.750905 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61909.090909 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61909.090909 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8114.457593 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8114.457593 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8114.843253 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8114.843253 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8114.453684 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8114.453684 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8114.839344 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8114.839344 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 715634 # number of replacements -system.cpu.icache.tags.tagsinuse 511.830268 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 88370349 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 716146 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 123.397113 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 324802500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.830268 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999668 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999668 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 715635 # number of replacements +system.cpu.icache.tags.tagsinuse 511.829472 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 88370544 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 716147 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 123.397213 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 326419500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.829472 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999667 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999667 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id @@ -839,207 +839,207 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 246 system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 178900425 # Number of tag accesses -system.cpu.icache.tags.data_accesses 178900425 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 88370349 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 88370349 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 88370349 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 88370349 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 88370349 # number of overall hits -system.cpu.icache.overall_hits::total 88370349 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 721790 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 721790 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 721790 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 721790 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 721790 # number of overall misses -system.cpu.icache.overall_misses::total 721790 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 5973224944 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 5973224944 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 5973224944 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 5973224944 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 5973224944 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 5973224944 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 89092139 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 89092139 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 89092139 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 89092139 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 89092139 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 89092139 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 178900820 # Number of tag accesses +system.cpu.icache.tags.data_accesses 178900820 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 88370544 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 88370544 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 88370544 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 88370544 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 88370544 # number of overall hits +system.cpu.icache.overall_hits::total 88370544 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 721792 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 721792 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 721792 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 721792 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 721792 # number of overall misses +system.cpu.icache.overall_misses::total 721792 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 5973239447 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 5973239447 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 5973239447 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 5973239447 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 5973239447 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 5973239447 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 89092336 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 89092336 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 89092336 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 89092336 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 89092336 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 89092336 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008102 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.008102 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.008102 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.008102 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.008102 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.008102 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8275.571765 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8275.571765 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8275.571765 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8275.571765 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8275.571765 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8275.571765 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 62134 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8275.568927 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8275.568927 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8275.568927 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8275.568927 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8275.568927 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8275.568927 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 62302 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2178 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2158 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.528007 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.870250 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 31.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 5643 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 5643 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 5643 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 5643 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 5643 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 5643 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 716147 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 716147 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 716147 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 716147 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 716147 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 716147 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5549831453 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 5549831453 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5549831453 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 5549831453 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5549831453 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 5549831453 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 5644 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 5644 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 5644 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 5644 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 5644 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 5644 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 716148 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 716148 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 716148 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 716148 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 716148 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 716148 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5551358955 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 5551358955 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5551358955 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 5551358955 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5551358955 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 5551358955 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008038 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008038 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008038 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.008038 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008038 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.008038 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7749.570204 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7749.570204 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7749.570204 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7749.570204 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7749.570204 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7749.570204 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7751.692325 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7751.692325 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7751.692325 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7751.692325 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7751.692325 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7751.692325 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 404667 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 404963 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 238 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 405270 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 405390 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 107 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 28037 # number of prefetches not generated due to page crossing +system.cpu.l2cache.prefetcher.pfSpanPage 28146 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 5979.453401 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3840411 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 7285 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 527.166918 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 5987.985640 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3840429 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 7297 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 526.302453 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2575.206017 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2680.661219 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 617.502494 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 106.083671 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.157178 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.163615 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.037689 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006475 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.364957 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 494 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 2575.177185 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2680.633084 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 617.470420 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 114.704950 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.157176 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.163613 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.037687 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.007001 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.365478 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 506 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 6791 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::2 344 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 112 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 124 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 772 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 128 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 773 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 127 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5749 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.030151 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.030884 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.414490 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 68225284 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 68225284 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 68225328 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 68225328 # 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number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 57082000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 57082000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 199290000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 199290000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 76381000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 76381000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 199290000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 133463000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 332753000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 199290000 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 200811500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 133346500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 334158000 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 966339 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 966339 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 220653 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 220653 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 715241 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 715241 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 715242 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 715242 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1313704 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 1313704 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 715241 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 715242 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 1534357 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2249598 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 715241 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2249599 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 715242 # 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number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 35037 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 188993302 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 188993302 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1757 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 30427 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 35107 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 180653766 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 180653766 # number of HardPFReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 17000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 17000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 50613500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 50613500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 181139000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 181139000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 68370000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 68370000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 181139000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 118983500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 300122500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 181139000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 118983500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 188993302 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 489115802 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49936000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49936000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 182660500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 182660500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 69288000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 69288000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 182660500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 119224000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 301884500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 182660500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 119224000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 180653766 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 482538266 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003354 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003354 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003313 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003313 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004087 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004087 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000779 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000779 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000781 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000781 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004087 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001150 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.002083 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001145 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.002080 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004087 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001150 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001145 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.015575 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6227.126919 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 6227.126919 # average HardPFReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.015606 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5937.284846 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 5937.284846 # average HardPFReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68396.621622 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68396.621622 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61970.236059 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61970.236059 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66767.578125 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66767.578125 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61970.236059 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67450.963719 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64032.963516 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61970.236059 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67450.963719 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6227.126919 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13959.979507 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68311.901505 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68311.901505 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62490.762915 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62490.762915 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67532.163743 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67532.163743 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62490.762915 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67856.573705 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64505.235043 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62490.762915 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67856.573705 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5937.284846 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13744.787820 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 2029851 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2029852 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 966339 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1033895 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 31761 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1033896 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 31809 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 220653 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 220653 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 716147 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 716148 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1313704 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2122577 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2122580 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4377763 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6500340 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45775424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6500343 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45775488 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160044544 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205819968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 32667 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4531746 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.007009 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.083423 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 205820032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 32715 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4531796 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.007019 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.083485 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4499985 99.30% 99.30% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 31761 0.70% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4499987 99.30% 99.30% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 31809 0.70% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4531746 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3216331500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4531796 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3216332500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1074485469 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1074486969 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2301553965 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2301554963 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 6571 # Transaction distribution +system.membus.trans_dist::ReadResp 6592 # Transaction distribution system.membus.trans_dist::UpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 740 # Transaction distribution -system.membus.trans_dist::ReadExResp 740 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 6571 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14624 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14624 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 467904 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 467904 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 731 # Transaction distribution +system.membus.trans_dist::ReadExResp 731 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 6592 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14648 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14648 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 468672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 468672 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7312 # Request fanout histogram +system.membus.snoop_fanout::samples 7324 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7312 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7324 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7312 # Request fanout histogram -system.membus.reqLayer0.occupancy 9348857 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7324 # Request fanout histogram +system.membus.reqLayer0.occupancy 9437390 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 38261400 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 38347412 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |